JP2002024057A - System reset method for distributed processing electronic equipment and device therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute system reset by automatically detecting runaway of one microcomputer by the other microcomputer when one microcomputer causes the runaway. SOLUTION: A monitoring process 5a of notification signal and a generation process 5d of the system reset to function as a system reset signal generating means input physical information to maintain a prescribed behavior or prescribed timewise change tendency or a prescribed value among signals or commands or pieces of data to be outputted from the target microcomputer during a normal operation of the microcomputer and generate a signal to reset the system including the microcomputer when the physical information stops maintaining the prescribed behavior or the prescribed timewise change or the prescribed value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system reset method and apparatus for distributed processing electronic equipment, and more particularly to a system reset method suitable for a distributed processing electronic still camera equipped with a plurality of microcomputers. Regarding the device.

[0002]

2. Description of the Related Art An electronic still camera is a CCD (Charge Cou).
(pled Device) can be recorded electronically on a storage device such as a flash memory, or displayed on a liquid crystal display for on-the-spot confirmation. It is one of the widely used portable electronic devices.

[0003] In general, portable electronic devices are small and compact.
In addition to being lightweight, the life of the battery is required to be long. However, mounting a large-capacity battery contradicts the demand for small size and light weight. Therefore, a system is designed to minimize internal power consumption as much as possible.

[0004] The following are known techniques for designing an electronic still camera effective for power saving. That is, of the various processing functions required for the operation of the electronic still camera, the function required only for the standby state is assigned to the first microcomputer, and the other functions are assigned to the second microcomputer. Things. This can be said to be one form of a distributed processing type. By operating only the first microcomputer during standby, at least the power consumption of the second microcomputer can be suppressed. Further, by using a low-power type microcomputer as the first microcomputer, it is possible to further improve power saving.

[0005]

However, in a distributed processing type electronic still camera having a plurality of microcomputers as described above, the system reset measures at the time of microcomputer runaway are insufficient, and there is a problem to be solved. .

Here, the runaway of the microcomputer means that an abnormal operation is performed out of a predetermined program procedure. Although there are various causes of the abnormality, for example, it is conceivable that data in a register or a main memory of the microcomputer changes due to an influence of charged particles such as static electricity, a strong electric field, or a solar wind. In general, for an abnormal operation that can be expected, a predetermined error trap routine is incorporated in a program, so that a software reset can be performed to reset the system.

However, since it is physically impossible to trap all errors, it is not possible to completely prevent runaway of a microcomputer, and when a plurality of microcomputers are provided, it is proportional to the number of microcomputers. As a result, the probability of runaway will naturally increase, so measures to reset the system during runaway are indispensable to maintain system stability.However, in the conventional case, if one microcomputer goes The system cannot be reset by automatically detecting the runaway, so that there is no other way but to perform an artificial reset operation, which is troublesome and troublesome.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a distributed processing system in which when one microcomputer goes out of control, the other microcomputer can automatically detect the runaway and reset the system. It is an object of the present invention to provide a method and an apparatus for resetting a system of an electronic device.

[0009]

According to the present invention, a signal, a command or data output from a target microcomputer is provided with a predetermined behavior or a predetermined temporal change tendency or a predetermined time change during normal operation of the microcomputer. Of the microcomputer and other microcomputers when the physical information does not maintain the predetermined behavior, the predetermined temporal change tendency, or the predetermined value. Generate a signal to perform Alternatively, the microcomputer may determine whether the processing load being executed is light or heavy, and prohibit generation of a signal for resetting the system when the heavy processing load is determined.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings, taking an electronic still camera as an example. First, the processing function of the electronic still camera will be described by dividing it into several systems. FIG. 1 is a processing function diagram of the electronic still camera 1. The imaging system 1a captures an image of a subject and converts it into an image signal, and includes an aperture mechanism, a CCD, a timing generator, and the like. The image processing system 1b converts an image signal from the imaging system 1a into a color image signal or converts the image signal into a predetermined image format. Including a format conversion circuit. The recording system 1c records and holds the format-converted image data in a readable manner, and includes a storage device such as a flash memory and its peripheral circuits. The display system 1d is for confirming the composition at the time of photographing and displaying the photographed image and the through image.
It includes a display device for a finder, a display device of about several inches for image confirmation, and its peripheral circuits. The key operation system 1e performs various key operations such as shooting, image confirmation, and system setting, and includes switches such as a shutter key and various function keys and peripheral circuits thereof. The other system 1f is a group of other processing systems for convenience, and includes, for example, a power supply and an external interface. Note that the above system classification is merely an example,
Of course, it is not limited to this.

FIG. 2 is a conceptual diagram in the case where the processing of each system described above is shared by two microcomputers. First microcomputer 2
Are, for example, an imaging system 1a, an image processing system 1b, and a recording system 1c.
In addition, the second microcomputer 3 is in charge of the processing of the display system 1d (however, the finder section), and in this example, the display system 1d (however, except for the finder section), the key operation system 1e, and other systems. In charge of 1f processing.

In normal use, the first microcomputer 2 and the second microcomputer 3 are both activated to make all the above-mentioned systems operable.
Only the active state is activated to save power. In short, the processing in charge of the second microcomputer 3 may be the minimum processing necessary for maintaining the standby state. Therefore, the second
Since the microcomputer 3 of low power consumption can be used, the power saving performance during standby can be improved, and the battery life can be extended.

Here, an object of the present invention is to make it possible that, when one microcomputer goes out of control, the other microcomputer can automatically detect the runaway and perform a system reset.

FIG. 3 is a conceptual diagram of a system according to an embodiment for achieving the object. In the figure, two figures surrounded by a dashed line represent one microcomputer (corresponding to the “target microcomputer” described in the summary of the invention).
And other microcomputers 5 are schematically shown. One microcomputer 4 and another microcomputer 5 are the first microcomputer 2 in FIG.
And the second microcomputer 3. For example, when the second microcomputer 3 detects a runaway of the first microcomputer 2, one microcomputer 4 becomes the first microcomputer 2 and the other microcomputer 5 becomes the second microcomputer 3. Or, in the opposite case, one microcomputer 4 becomes the second microcomputer 3 and the other microcomputer 5 becomes the first microcomputer 2.

An important point of one microcomputer 4 is that a notification signal for notifying an operation state of the microcomputer 4 is externally output. The notification signal may be, for example, a signal (a signal having a predetermined temporal change tendency) that periodically repeats a predetermined logical state (for convenience, set to H level) during the normal operation of the microcomputer 4. The notification signal may be generated by causing the microcomputer 4 to execute a notification signal generation process programmed in advance periodically (for example, at one-second intervals). This is because, if one microcomputer 4 goes out of control, the execution of the above process is stopped and the periodic logical change of the notification signal is not externally observed.

However, the notification signal is not limited to only a signal having a predetermined temporal change tendency. In short, any signal that maintains a predetermined behavior, a predetermined time-dependent change tendency, or a predetermined value during normal operation of one microcomputer 4 may be used, and any of these signals may be the physical information described in the gist of the invention. (Or a command or data). In the figure, reference numeral 4a denotes a notification signal process (corresponding to physical information output means described in the gist of the invention).
b indicates the periodic execution of the process, and 4c indicates the notification signal generated by the process.

On the other hand, another important point of the microcomputer 5 is that the notification signal output from the one microcomputer 4 is monitored.
Then, the operation state of one microcomputer 4 is determined based on the signal, and when an abnormal operation (runaway) is determined, a system reset signal is generated and output to the system reset unit 6. In the figure, 5a represents the monitoring process of the notification signal, 5b represents the periodic execution of the process,
5c represents the result of the operation determination of one microcomputer 4 by the process, 5d represents the process of generating a system reset at the time of abnormal operation determination, and 5e represents the system reset signal. The notification signal monitoring process 5a and the system reset generation process 5d correspond to the system reset signal generation means described in the gist of the invention. These processes (5a, 5c, 5d) in the other microcomputer 5 may be realized by software or may be realized by dedicated hardware.

According to such a configuration, one microcomputer 4
Runs out of control, the periodic execution of the notification signal generation process 4a is not performed, so that the notification signal 4c maintains the L level state. As a result, in the notification signal monitoring process 5a of the other microcomputer 5, the L level maintaining state of the notification signal 4c is detected, and the runaway of one microcomputer 4 is detected. Therefore, a system reset signal 5e is generated in the system reset process 5d of the other microcomputer 5, and this system reset signal 5e is output to the system reset unit 6, so that the microcomputer 4 and the other microcomputer 5 and other peripheral circuits can be used. Since the system reset can be executed by performing the reset notification 6a, there is no need to perform an artificial reset operation, and there is a unique merit that the usability can be improved without any trouble.

By the way, in the case of the above configuration, it may be difficult to periodically execute the notification signal generation process 4a depending on the processing state of one microcomputer 4. For example,
When the processing load is large, the execution of the notification signal generation process 4a may be waited. In such a case,
Since the notification signal 4c output from one microcomputer 4 keeps the L level for a long time, the notification signal monitoring process 5a of the other microcomputer 5 makes an erroneous determination.
This causes an operational inconvenience that an unintended system reset is performed.

FIG. 4 shows an improved example of the above embodiment.
The inconvenience is avoided. In the figure, two figures surrounded by a dashed line schematically show one microcomputer (corresponding to “a target microcomputer” in the gist of the invention) 7 and another microcomputer 8. One microcomputer 7 and another microcomputer 8 correspond to the first microcomputer 2 and the second microcomputer 3 in FIG.
For example, when the second microcomputer 3 detects a runaway of the first microcomputer 2, one microcomputer 7 becomes the first microcomputer 2 and the other microcomputer 8 becomes the second microcomputer 3. Or, in the opposite case, one microcomputer 7 becomes the second microcomputer 3 and the other microcomputer 8 becomes the first microcomputer 2.

One important point of one microcomputer 7 is that a notification signal for notifying the operation state of the microcomputer 7 is externally output as in the above embodiment. The notification signal can be, for example, a signal that periodically repeats a predetermined logical state (for convenience, set to H level). The generation of the notification signal is performed by a notification signal generation process programmed in advance by the microcomputer. Periodic at 7 (eg 1 second period)
May be performed. One microcomputer 7
Runaway, the above process stops running,
This is because a periodic logical change of the notification signal is not externally observed.

Another important point of the microcomputer 7 is that a processing state signal indicating the operation load of the microcomputer 7 can be output. As this processing state signal, for example, a signal for notifying the state of the bus cycle to the outside (specifically, a bus status signal of V30 or 80486 architecture) can be used. This is because if the address bus or the data bus is used frequently, the processing load of the microcomputer 7 can be considered to be large. However, the processing state signal is not limited to this example (bus status signal). In short, any signal may be used as long as it roughly represents the actual processing load of one microcomputer 7, and may be, for example, a chip temperature signal.

In the figure, 7a represents a notification signal process, 7b represents the periodic execution of the process, and 7c represents a notification signal generated by the process.
7d represents a process (or hard logic) for generating a process state signal, and 7e represents a process state signal generated by the process.

On the other hand, one important point of the other microcomputer 8 is that, similarly to the above embodiment, a notification signal output from one microcomputer 7 is monitored (monitored), and one microcomputer is monitored based on the signal. The operation state of the microcomputer 7 is determined, and when an abnormal operation (runaway) is determined, a system reset signal is generated. Another important point is that one microcomputer 7
Is to determine the magnitude of the processing load on one microcomputer 7 based on the processing state signal from the microcomputer 7 and if the heavy processing is being executed, the system reset signal is masked.

In the figure, 8a represents a process of monitoring a notification signal, 8b represents a periodic execution of the process, 8a
c represents the result of the operation determination of one microcomputer 7 by the process, 8d represents a process of generating a system reset when an abnormal operation is determined, and 8e represents a system reset signal. 8f represents a load determination process for determining the magnitude of the processing load of the microcomputer 7 based on the processing state signal from one microcomputer 7, and 8h masks the system reset signal 8e when determining a heavy load. This shows a mask process. Notification signal monitoring process 8a, system reset generation process 8d, load determination process 8f
The mask process 8h corresponds to system reset signal generating means described in the gist of the invention, and the mask process 8h corresponds to system reset signal inhibiting means.

Note that these processes (8a, 8c, 8d, 8f, 8h) in the other microcomputer 8 may be realized by software or may be realized by dedicated hardware. Is also good.

According to such a configuration, one microcomputer 7
When the notification signal 7c from the CPU maintains the L level for a long time, the notification signal monitoring process 8a of the other microcomputer 8 performs
One microcomputer 7 is provisionally determined to be in a runaway state, and a system reset signal 8e is generated in a system reset process 8d. However, the processing load of one microcomputer 7 is concurrently determined in a load determination process 8f of another microcomputer 8. And if the processing is determined to be heavy, the system reset signal 8e is masked. If not, a non-masked system reset signal 8i is output to the system reset unit 9 so that one microcomputer 7 or another microcomputer 8 And a reset notification 9a to other peripheral circuits to execute a system reset.

Therefore, according to the improved embodiment, even if the notification signal 7c from one microcomputer 7 keeps the L level state for a long time while one microcomputer 7 is performing heavy processing, By masking the system reset signal 8e, the reset notification 9a to one microcomputer 7 or another microcomputer 8 and other peripheral circuits can be prohibited, and a unique advantage in operation stability that an unintended system reset is not performed is obtained. Can be

FIG. 5 is a block diagram showing an electronic still camera according to the present invention, particularly showing a main part related to a microcomputer. In this figure, the main microcomputer unit 10 is the first (see FIG. 2) described above.
The sub-microcomputer unit 20 corresponds to the second microcomputer 3, and each unit of the electronic still camera includes, for example, an imaging system 1a, an image processing system 1b, and a recording system 1.
When the system is divided into c, display system 1d, key operation system 1e, and other system 1f, the main microcomputer unit 10 includes, for example, an imaging system 1a, an image processing system 1b, a recording system 1c, and a display system 1d (however, a finder unit). The sub-microcomputer unit 20 is responsible for the remaining processing, in this example, the display system 1
d (excluding the finder section), the key operation system 1e and the other system 1f. In addition, the code | symbol of each system respectively corresponds to the code | symbol of FIG.

During normal use, the main microcomputer 10
And the sub-microcomputer unit 20 are both activated to make all the above-mentioned systems operable, while at the time of standby, only the sub-microcomputer unit 20 is activated to save power. In short, the processing in charge of the sub-microcomputer unit 20 may be the minimum processing required to maintain the standby state. Therefore, since a sub-microcomputer unit 20 that consumes less power can be used, power saving performance during standby can be improved.

Here, the main microcomputer unit 10 corresponds to the one microcomputer (see reference numeral 4 in FIG. 3 or reference numeral 7 in FIG. 4), and the sub-microcomputer unit 20 corresponds to the other microcomputer (reference numeral 5 in FIG. 4 (8)). That is, the sub microcomputer 20 (other microcomputer) can detect runaway of the main microcomputer 10 (one microcomputer). Here, in addition to the main microcomputer section 10 and the sub-microcomputer section 20, a clock section 30 and a system reset section 40 are shown in the drawing, and the clock section 30 is a periodic signal (for example, a signal at Ta second intervals; The system reset section 40 resets each section of the system in response to an internal reset signal (RSTa, RSTb, RSTc) from each of the microcomputers 10 and 20. RST
It has a function of generating _SYS.

<System Reset by Watchdog Timer> The main microcomputer unit 10 and the sub-microcomputer unit 20 include the watchdog timer units 17 and 27, respectively.
Built-in (or external). As is well known, the watchdog timer units 17 and 27 each include a counter of several bits and an overflow detection circuit, and sequentially update the counter value in synchronization with a periodic signal such as a system clock. When an overflow occurs (or when a predetermined value is reached), an internal reset signal (RSTa in the main microcomputer unit 10, the sub microcomputer unit 2)
If it is 0, RSTb) is generated.

However, the counter value can be initialized by software or hardware. For example, assuming that the time from the initial value to the overflow value (or a predetermined value) is Tx, the counter value is at least within Tx. By periodically initializing the counter value with time, the generation of the internal reset signal (RSTa in the main microcomputer unit 10 and RSTb in the sub-microcomputer unit 20) can be prohibited.

The "other units 11 and 26" of the main microcomputer unit 10 and the sub microcomputer unit 20 include the microcomputers 10 and 2 respectively.
0 is a schematic representation of the processing function assigned to the watchdog timer unit 1 from “Other units 11 and 26”.
The signals S1a and S1b output to the counters 7 and 27 are initialization signals for the counter value which are periodically generated at least within a period of time Ta while the respective processing functions are normally executed.

Therefore, according to the main microcomputer unit 10 and the sub-microcomputer unit 20 provided with the watchdog timer units 17 and 27, if one of the processing functions is not normally executed, the watch on the abnormal side When the counter value of the dog timer unit (17 or 27) is no longer initialized and the Tx time has elapsed from the immediately preceding initialization time, an internal reset signal (RSTa in the main microcomputer unit 10, the sub microcomputer unit 20) In this case, since RSTb) occurs, the system reset unit 40 can generate the system reset signal RST_SYS in response to the internal reset signal.

FIG. 6 is a flowchart of a system reset by the watchdog timer. FIG. 6A relates to the internal reset signal RSTa of the main microcomputer unit 10.
(B) shows the internal reset signal RST of the sub microcomputer unit 20.
b. As can be understood from these flowcharts, the watchdog timers (watchdog timer sections 17, 27) of the main microcomputer section 10 or the sub microcomputer section 20 are always cleared (initialized or returned to a predetermined value) before overflow. (Step S1
1 and step S21) if the main microcomputer unit 1
If the assigned processing function of the sub microcomputer unit 20 is not executed normally, the clear operation is not performed, and the overflow occurs (or reaches a predetermined value). Signal RSTa
In addition, the sub-microcomputer unit 20 generates the internal reset signal RSTb, and as a result, the system can be forcibly reset (step S12 or step S22).

Next, the main microcomputer section 10 and the sub microcomputer section 20 have the following configuration (software) in addition to the function of generating the internal reset signals RSTa and RSTb using the watchdog timer sections 17 and 27. (Including those realized).

That is, the main microcomputer unit 10 further includes a normal operation signal generation unit 12, a normal operation signal output unit 13, a forced reset mask unit 14, a normal operation communication command generation unit 15, and a normal operation communication command output. Part 16
The sub-microcomputer unit 20 further includes a normal operation signal input unit 21, a forced reset control unit 22, a normal operation communication command input unit 23, a runaway determination unit 24, and a one-second interval detection unit 25. Each of these units has a function of determining runaway of the main microcomputer unit 10 by the sub-microcomputer unit 20 and generating an integrated internal reset signal RSTc based on the determination result.

Hereinafter, the internal reset signal RSTc will be referred to as an integrated internal reset signal RSTc for convenience, and will be distinguished from the internal reset signals RSTa and RSTb by the watchdog timer.

As can be understood from the drawing, the integrated internal reset signal RSTc is an output signal of the runaway determination unit 24.
Runaway determination unit 24 operates in synchronization with a periodic signal from 1 second interval detection unit 25 (a signal at Ta intervals generated based on the time signal of clock unit 20; here, a signal at 1 second intervals for convenience). Based on the three signals S2a to S2c from the normal operation signal input unit 21, the forced reset control unit 22, and the normal operation communication command input unit 23, the main microcomputer unit 10 makes a runaway determination. The integrated internal reset signal RSTc is output, and the output of the integrated internal reset signal RSTc is prohibited (masked) when a predetermined condition is satisfied.

More specifically, runaway determination section 24 makes a runaway determination of main microcomputer section 10 (hereinafter, referred to as "first runaway determination") based on signal S2a from signal input section 21 during normal operation, or , The main microcomputer unit 1 based on the signal S2c from the communication command input unit 23 during normal operation.
A runaway determination of 0 (hereinafter referred to as “second runaway determination”) is performed. When the result of the first runaway determination or the second runaway determination is “runaway”, if the signal S2b is active with reference to the signal S2b from the forced reset control unit 22, the first runaway is performed. While the determination result of the runaway determination or the second runaway determination is ignored, if inactive, the integrated internal reset signal RS is determined in accordance with the determination result.
Tc is output.

<First Runaway Determination> First, the first runaway determination will be described. The periodic signal S3 generated by the normal signal generation unit 12 of the main microcomputer unit 10 is input to the normal operation signal input unit 21 via the normal operation signal output unit 13. This signal S3 is a periodic signal with a Ta interval (Ta = 1 second) synchronized with the time signal of the clock unit 30, and the clock unit 30 operates normally and the main microcomputer unit 10 operates normally. As long as the periodicity of the signal S3 is not lost.

FIG. 7 is a timing chart of the signal S3.
FIG. 7A is a diagram when a constant period (Ta) is maintained, and FIG. 7B is a diagram when the periodicity is lost. The first runaway determination by the runaway determination unit 24 is, in short, to monitor the periodicity of the signal S3 and to determine when the periodicity is lost (for example, when the state becomes as shown in FIG. It is determined that an abnormality (runaway, for example) has occurred in 10.

That is, as shown in FIG. 8A, the main microcomputer section 10 generates a normal operation signal and outputs the signal to the sub microcomputer section 20 (step S31). Monitor the periodicity of the signal,
An operation abnormality of the main microcomputer unit 10 is determined (step S3
2) In addition, since it is possible to perform a system reset at the time of abnormality determination (step S33), it is possible to take measures against a system reset in a microcomputer runaway in a distributed processing type electronic still camera including a plurality of microcomputers.

<Second Runaway Determination> Next, the second runaway determination will be described. Communication command input section 23 during normal operation
The periodic communication command S4 generated by the normally operating communication command generating unit 15 of the main microcomputer unit 10 is input via the normally operating communication command output unit 16. This communication command S4 is an arbitrary command having a periodicity of Ta interval (Ta = 1 second) synchronized with the time signal of the clock unit 30, the clock unit 30 operates normally, and the main microcomputer unit 10 As long as it operates normally, the periodicity of the communication command S4 is not lost.

In the second runaway determination by the runaway determination unit 24, in short, when the periodicity of the communication command S4 is monitored and the periodicity is lost, an abnormality (for example, runaway) occurs in the main microcomputer unit 10. It is to judge by considering it.

That is, as shown in FIG. 8B, the main microcomputer section 10 generates a communication command during normal operation and outputs it to the sub microcomputer section 20 (step S41). By monitoring the periodicity of the middle communication command, it is possible to determine the operation abnormality of the main microcomputer unit 10 (step S42), and to perform a system reset when the abnormality is determined (step S4).
3) Therefore, this also makes it possible to take measures against a system reset in the case of microcomputer runaway in a distributed processing type electronic still camera having a plurality of microcomputers.

<Mask Processing> As described above, the runaway determination unit 24 does not immediately perform a system reset even if it determines that the main microcomputer unit 10 is abnormal in the first runaway determination or the second runaway determination. Reset signal RST
c is not output). While the integrated internal reset signal RSTc is allowed to be output when the signal S2b from the forced reset control unit 22 is inactive, the integrated internal reset signal RSTc is enabled when the signal S2b is active, regardless of the determination result.
The output of STc is prohibited (masked).

The mask signal S5 is input to the forced reset control unit 22 from the forced reset mask unit 14 of the main microcomputer unit 10. The mask signal S5 is transmitted to the "other unit 11" (main microcomputer) of the main microcomputer unit 10. This is a signal (for example, the above-described bus status signal) that becomes active when the load state signal S6 input from the processing function execution unit in charge of the unit 10 indicates a high load state. The forced reset control unit 22 includes a main microcomputer unit 10
Signal S2b when the mask signal S5 from
Is activated, and the signal S2b is made inactive when the mask signal S5 is inactive.

Therefore, runaway determination section 2 of the present embodiment
According to FIG. 4, when an abnormality (for example, runaway) of the main microcomputer unit 10 is determined in the first runaway determination or the second runaway determination, the target CPU (in this case, the main microcomputer 10 ) Processing load is heavy,
Specifically, it is determined whether or not the signal S2b is active (processing of the main microcomputer unit 10 is heavy) (steps S51 and S52). If the signal S2b is active, the output of the integrated internal reset signal RSTc is prohibited ( (Step S53), the system reset can be prevented from being performed. On the other hand, if the system is inactive, the output of the integrated internal reset signal RSTc is permitted (if RSTa is masked, the mask is released). (Step S
54) A system reset can be performed.

As a result, an erroneous system reset can be avoided even if a loss of periodicity of a normally operating signal or a normally operating communication command is observed during execution of heavy processing by the main microcomputer unit 10. In addition, a unique advantage is obtained in that the reliability and stability of the system operation can be improved.

[0052]

According to the present invention, any one of a signal, a command, and data output from a target microcomputer is given a predetermined behavior or a predetermined temporal change tendency or a predetermined value during normal operation of the microcomputer. When the physical information does not maintain the predetermined behavior, the predetermined temporal change tendency, or the predetermined value, the system including the microcomputer and other microcomputers is reset. For example, an abnormal operation of the target microcomputer can be determined by another microcomputer incorporated in the system together with the microcomputer, and a signal for resetting the system can be generated.

Therefore, the other microcomputer can automatically detect an operation abnormality (runaway or the like) of one microcomputer (target microcomputer) and reset the system. For example, a plurality of microcomputers are provided. It is possible to provide a system reset method and a device suitable for use in a distributed processing type electronic device such as an electronic still camera.

Alternatively, if the processing load being executed by the microcomputer is determined to be light or heavy, and if a heavy processing load is determined, generation of a signal for resetting the system is prohibited. Even if an erroneous abnormality is determined based on physical information from one microcomputer (target microcomputer), unintended system reset can be prevented from being performed, improving system reliability and stability. Can be achieved.

[Brief description of the drawings]

FIG. 1 is a processing function diagram of an electronic still camera 1.

FIG. 2 is a conceptual diagram in a case where processing of each system of the electronic still camera 1 is shared by two microcomputers.

FIG. 3 is a conceptual diagram of a system according to the embodiment.

FIG. 4 is a system conceptual diagram showing an improved example of the embodiment.

FIG. 5 is a configuration diagram showing a main part of the electronic still camera according to the present invention, particularly, a microcomputer-related part.

FIG. 6 is a flowchart of a system reset by a watchdog timer.

FIG. 7 is a timing chart of a signal S3.

FIG. 8 is a flowchart of a system reset based on a normal operation signal or a normal operation communication command.

FIG. 9 is a flowchart of a system reset mask process.

[Explanation of symbols]

4 One microcomputer (target microcomputer) 4a Notification signal process (physical information output means) 5a Notification signal monitoring process (system reset signal generation means) 5d System reset generation process (system reset signal generation means) 7 one microcomputer (Target microcomputer) 8a Notification signal monitoring process (system reset signal generation means) 8d System reset generation process (system reset signal generation means) 8f Load determination process (system reset signal generation means) 8h Mask process (system reset signal) Generation means, system reset signal prohibition means) 10 Main microcomputer section (target microcomputer)

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H04N 5/232 G06F 1/00 350B

Claims (7)

[Claims] 1. A method according to claim 1, wherein a signal, a command, or data output from a target microcomputer is given as physical information maintaining a predetermined behavior, a predetermined temporal change tendency, or a predetermined value during normal operation of the microcomputer. A signal for resetting a system including the microcomputer and other microcomputers is generated when the physical information does not maintain the predetermined behavior, the predetermined temporal change tendency, or the predetermined value. Including a system reset signal generating step,
System reset method for distributed processing electronic equipment. 2. A signal or a command or data output from a target microcomputer is output as physical information maintaining a predetermined behavior, a predetermined temporal change tendency, or a predetermined value during normal operation of the microcomputer. A physical information output unit that outputs a signal for resetting a system including the microcomputer and other microcomputers when the physical information does not maintain the predetermined behavior or the predetermined temporal change tendency or a predetermined value. And a system reset signal generating means for generating the system reset signal. 3. The system reset signal generating step includes:
2. The method according to claim 1, further comprising determining a lightness of a processing load being executed by the microcomputer, and prohibiting generation of a signal for resetting the system when determining a heavy processing load. Also, a system reset method for a distributed processing type electronic device. 4. The system reset signal generating means includes:
3. The method according to claim 2, further comprising: judging the lightness of the processing load being executed by the microcomputer, and prohibiting generation of a signal for resetting the system when judging a heavy processing load. Also, a system reset device for distributed processing type electronic equipment. 5. The system reset signal generating means,
3. The device according to claim 2, wherein the microcomputer is included in the other microcomputer.
A system reset device for a distributed processing type electronic device according to claim 1. 6. A signal or a command or data output from a target microcomputer as physical information that maintains a predetermined behavior, a predetermined temporal change tendency, or a predetermined value during normal operation of the microcomputer. A system reset signal generation for generating a signal for resetting the system including the microcomputer when the physical information does not maintain the predetermined behavior, the predetermined temporal change tendency, or the predetermined value. And a system reset signal prohibiting step of prohibiting generation of a signal for resetting the system when judging the lightness of the processing load being executed by the microcomputer and judging a heavy processing load. A system reset method for a distributed processing type electronic device. 7. A signal or a command or data output from a target microcomputer is output as physical information that maintains a predetermined behavior, a predetermined temporal change tendency, or a predetermined value during normal operation of the microcomputer. A physical information output unit for performing a reset for generating a signal for resetting a system including the microcomputer when the physical information does not maintain the predetermined behavior, the predetermined temporal change tendency, or the predetermined value. Signal generating means, and system reset signal prohibiting means for prohibiting generation of a signal for resetting the system when judging the processing load being executed by the microcomputer and judging a heavy processing load. A system reset device for a distributed processing type electronic device.