JP2002016881A - Digital signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital signal processor for commonly using circuits and elements by a selectively recording process to data storage media and a selectively reproducing process to a display. SOLUTION: The digital signal processor selectively inputs data streams from terminals (a) and (b)or data streams reproduced by data storage media to demultiplexers 4 and 5 by a selector 3, and selectively outputs from the demultiplexers 4 and 5 or a bypass from the selector 3 by a selector 6 when recording in the media.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording process for recording, on a data storage medium, a data stream obtained by multiplexing a partial stream composed of compression-encoded video data, audio data, and accompanying system data. The present invention relates to a digital signal processor that performs playback processing for display on a display.

[0002]

2. Description of the Related Art MPEG (Moving Picture Expe
(rts Group) in a digital TV broadcasting system that encodes and distributes television signals using the compression encoding method of video and audio signals, and receives demultiplexed compressed data packets in which programs (programs) are multiplexed. A receiving apparatus that performs (multiplex separation) and allows a user to select and reproduce video and audio signals belonging to a desired program has been developed and put into practical use. In addition, for example,
As disclosed in Japanese Patent Application Laid-Open No. 50227/1990, there are provided two transmission path interfaces (hereinafter referred to as transmission path I / F; corresponding to a tuner / demodulation unit in the above-mentioned publication) and one demultiplexer for digital broadcasting signals The digital broadcast signal to be viewed is demodulated by a demultiplexer and supplied to a display device. For recording, a data stream including a partial stream of a desired program different from the program to be viewed is recorded on a VTR. It is supplied and recorded.

Some digital TV broadcast programs distribute still image data compressed by JPEG (Joint Photograhic Experts Group), graphic data encoded by graphic codes, and the like. Decrypt and display.

[0004]

The conventional VT
In R, since a data stream including a partial stream of a desired program is recorded, even when only a desired program is to be recorded, a data stream including a partial stream of the desired program must be recorded.
The tape is wasted. Further, there may be a case where a data stream including a partial stream of a desired program is recorded for the time being as in the past, and only a reproduced program desired to be viewed later is extracted and reproduced. Therefore, it is convenient if the user can select.

When a desired program is to be reproduced, not only reproduction from a data stream but also reproduction from a data storage medium such as a VTR tape, and data to be reproduced are performed.
It is convenient to realize a so-called back program recording where the data stream differs from the task stream, or a so-called time shift function where the same program recorded immediately before is recorded while a desired program is recorded. It is.

In addition, it is desirable to share circuits and elements as much as possible between the recording processing on the data storage medium and the reproduction processing on the display in order to reduce the cost.

It is an object of the present invention to provide a digital signal processing device that shares circuits and elements for selective recording processing on a data storage medium and selective reproduction processing on a display.

[0008]

According to the present invention, a transmission data stream obtained by multiplexing a partial stream composed of compression-encoded video data, audio data, and accompanying system data is input, and a set of video data is transmitted. A demultiplexer for extracting a partial stream composed of audio data and accompanying system data; an interface connected to a data storage medium for recording and reproducing at least a partial stream of the transmission data stream;
A first selector for selecting an input to the demultiplexer from the transmission data stream and a stored data stream reproduced by the data storage medium; and an input to the interface means for the demultiplexer. A second selector for selecting between an output from a multiplexer and an output from the first selector, and when recording on the data storage medium, the second selector
An output from the demultiplexer or an output from the first selector is selected and input to the interface means. When reproducing the partial stream, the first
Wherein the selector selects the stored data stream or the transmission data stream and inputs the selected data stream to the demultiplexer.

In the present invention, the demultiplexer includes a main demultiplexer for extracting a set of video data and audio data, and a sub demultiplexer for extracting associated system data. And selecting and inputting an input to the connection means for connecting to the data storage medium from an output from the main demultiplexer and an output from the sub demultiplexer and an output from the first selector. A digital signal processor characterized by the following.

In the present invention, at least a compression code decoder for decoding an output of the main demultiplexer and a still picture decoder for decoding an output of the sub demultiplexer are provided. A digital signal processing device for outputting a video signal and an audio signal.

In the present invention, the main buffer for converting the speed of the output of the main demultiplexer, the sub-buffer for converting the speed of the output of the sub-demultiplexer, and the outputs of the main buffer and the sub-buffer are multiplexed. A digital signal processing device comprising: a multiplexing unit, wherein an output of the multiplexing unit is input to the compression code decoder when the partial stream is reproduced.

[0012] In the present invention, there is provided a still picture decoder for decoding an output of the sub-demultiplexer, and outputs a decoded video signal and audio signal when reproducing the partial stream. Processing device.

In the digital signal processing apparatus according to the present invention, the demultiplexer, the connection means, the first selector and the second selector are formed on a semiconductor integrated circuit.

According to the present invention, a transmission data stream obtained by multiplexing a partial stream composed of compression-encoded video data and audio data and accompanying system data is input, and a set of video data and audio data is extracted. Storage media interface means having a connection terminal for a demultiplexer, a sub-demultiplexer for extracting compression-encoded accompanying system data, and a data storage medium for recording and reproducing at least a partial stream of the transmission data stream; An input to a multiplexer, said transmission data stream from an input terminal;
A first selector for selecting between a storage data stream from the storage media interface unit and a recording input to the storage media interface unit;
A second selector for selecting between an output from the main demultiplexer and the sub demultiplexer, an output from the first selector, a compression code decoder for decoding an output from the main demultiplexer, and An output terminal for inputting the output of the multiplexer to a still image decoder, a decoding input terminal from the output of the still image decoder,
A synthesizing means for synthesizing an output of the compression code decoder and an input from the decoding input terminal; and synthesizing output terminal means for outputting a synthesized output, the main demultiplexer, the sub demultiplexer, and the storage media interface. Digital signal processing wherein the means, the first selector, the second selector, the input terminal, the connection terminal, the output terminal, and the decoding input terminal are configured on a semiconductor integrated circuit. Device.

According to the present invention, a transmission data stream obtained by multiplexing a partial stream composed of compression-encoded video data and audio data and accompanying system data is input, and a set of video data and audio data is extracted. Storage media interface means having a connection terminal for a demultiplexer, a sub-demultiplexer for extracting compression-encoded accompanying system data, and a data storage medium for recording and reproducing at least a partial stream of the transmission data stream; An input to a multiplexer, said transmission data stream from an input terminal;
A first selector for selecting between the storage data stream, a recording input to the storage media interface means, an output from the main demultiplexer and a sub demultiplexer, and a bypass output from the first selector. A first output terminal for inputting the output of the main demultiplexer to a compression code decoder, and a second output terminal for inputting the output of the sub demultiplexer to a still picture decoder. Terminals, the main demultiplexer, the sub demultiplexer, the storage media interface means, the first selector, the second selector, the input terminal, the connection terminal, the first output terminal, and the second output terminal. A digital signal processing device characterized in that the output terminal is formed on a semiconductor integrated circuit. It is.

[0016]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention. A data packet in the form of a transport stream (hereinafter simply referred to as TS), which is defined in the MPEG system and is a data stream, is transmitted via a transmission path I / F1 and a transmission path I / F2.
It is input to the selector 3. Here, the transmission path I / F1 and the transmission path I / F2 indicate interfaces including a tuner circuit, a demodulation circuit, an error correction circuit, and a descrambling circuit, respectively. The TS is composed of a plurality of programs composed of video, audio or graphic data and packets containing system information. Then, the independent or the same TS is input to the selector 3 from the transmission line I / F1 and the transmission line I / F2 via the input terminals a and b of the semiconductor integrated circuit 15. The selector 3 further receives a TS supplied from a data storage medium 13 such as a VTR or a hard disk device via transmission path connection terminals c and d such as IEEE 1394 and a storage medium I / F 7. Therefore, selector 3
Has three inputs and the selector 3 has three outputs. The main demultiplexer 4, the sub demultiplexer 5, and the
And a selector 6 connected to the storage media I / F 7.

Therefore, when recording on the data storage medium 13, the selector 3 selects the input from the input terminals a and / or b, and the selector 6 selects the outputs of the main demultiplexer 4 and the sub demultiplexer 5. Or the bypass output from the selector 3 is selected.

When reproducing to the terminal g of the main demultiplexer 4 and the sub demultiplexer 5, the selector 3
And force terminals a and / or b and storage media I / F
7 is selected as the reproduction signal.

The main demultiplexer 4 has a partial stream MP corresponding to a desired program selected by the user.
The EG image / audio packet is extracted, that is, filtered, and sent to the MPEG decoder 9.

FIG. 2 is a diagram showing the structure of an MPEG TS packet together with its hierarchical structure. One TS packet has a fixed length of 188 bytes and includes a TS header portion and a payload portion. The TS header portion has a PID (packet I
D) is included, and the user's program selection is performed by setting the PID to be filtered in the demultiplexer. The TS header also includes time stamp information, which is supplied to the clock recovery circuit 8 so that an input / output signal from a terminal f of a VCO (Voltage Controlled Oscillator) 14 allows a PLL (phase locked loop) to be used. ) And MP
The operation clock in the EG system is reproduced.

Two types of data formats are allowed for the payload portion of the TS packet, one of which is PES (Packetized E-mail).
lementary Stream) packet, and the other is a section. The PES packet is composed of a PES header and MPEG E
It is composed of PES data composed of coded image / audio data that is an S (elementary stream). Where P
The ES header includes a PES packet length and a type stamp indicating a decoding / display time.

Each section is added with a section header, section data, and an error check code for detecting an error in the section. Here, the section header includes an ID indicating a section length and a section type, and the section data includes data necessary for system operation such as a program map table and program content information, or additional data and data itself unique to each program. In the case of distribution as broadcast contents, graphic data such as still images and graphic information are included.

In FIG. 1, the MPEG decoder 9 has a T
It includes both system decoding for receiving an S packet and decomposing it into an MPEG image / audio ES, and MPEG video / audio decoding for decoding the MPEG image / audio ES into the original image / audio signal. The MPEG decoder 9 uses a decoder buffer 10 via a terminal e as a buffer memory for decoding. The sub demultiplexer 5 has M
A TS packet containing data other than PEG image / audio
It is supplied to the graphic decoder 11.

The graphic decoder 11 takes out and decodes still image data which has been subjected to compression encoding such as JPEG and graphic data which has been symbolized by a graphic code or compressed by a run-length code. Alternatively, when the data is audio data, processing such as decoding to PCM samples or conversion of sample frequency is performed. The graphic decoder 11 may include a memory, or the decoder buffer 10
May be shared. The image / audio signals decoded by the respective decoders are combined and output by the mix circuit 12, and supplied to a display device (not shown) via a terminal g. In the case of an image, a window display or an overlay display in a playback screen is performed, and in the case of an audio, switching and downmixing are performed.

The difference between the main demultiplexer 4 and the sub demultiplexer 5 is that the main demultiplexer 4 reproduces a system clock serving as a time base for MPEG decoding, whereas the sub demultiplexer 5 does not have that function. It is. Therefore, since the MPEG decoder 9 can perform decoding in synchronization with the system clock, that is, in synchronization with the input TS, there is no skip or repetition of image / audio caused by input / output frequency drift. On the other hand, the sub-demultiplexer 5 inputs a TS having a different time axis from that of the main demultiplexer 4 and, when operating asynchronously, synchronizes the still image output from the graphic decoder 11 before synthesizing and displaying it.

One of the outputs from the main demultiplexer 4 and the sub demultiplexer 5 and the bypass output not passing through the main demultiplexer 4 and the sub demultiplexer 5 is selected by the selector 6, and the storage media interface 7 and the connection terminals c, The data is input to the data storage medium 13 via d and recorded.

FIG. 3 shows an example of a recording and reproducing function by a selective combination of the input selector 3 of the main demultiplexer 4 and the sub demultiplexer 5 and the input selector 6 of the storage medium I / F 7 in FIG. It is the figure shown every.

In FIG. 3, transmission lines I / F1 and I / F1
The TS inputs from F2 are symbolized as (A) and (B), and the corresponding decoding results are symbolized as (a) and (b), respectively. (A), (B), (a)
Since (b) and (b) are respectively symmetrical, a combination in which these are replaced is omitted.

The features of each mode will be described below.

Mode 1: All programs of the TS are recorded while monitoring and reproducing (a) and (b) during reception decoding. That is, the normal recording monitor mode or the back program recording mode of another TS.

Mode 2: Only the same TS is recorded while monitoring (a) and (b) during reception decoding. The recording time can be longer than in mode 1.

Mode 3: While monitoring (a) and (b) during reception decoding, only the same TS is recorded. That is, the recording time can be made longer than in mode 1.

Mode 4: Monitor (a) during reception and decoding, and perform T
Record all S programs. In other words, it is possible to display the previously stored data combined with the received decoded moving image. In this case, it is assumed that the storage media can record and play back simultaneously.

Mode 5: (a) during reception decoding is monitored, and only the same TS (a) is recorded while reproducing and displaying the reproduction data of the recording medium. In other words, it is possible to display the previously stored data combined with the received decoded moving image. In this case, it is assumed that the storage media can record and play back simultaneously. That is, the recording time can be longer than in mode 4.

Mode 6: The reproduction data from the storage medium is decoded, and all the programs of the TS are recorded while being displayed in combination with the data (a) being received and decoded. It is possible to reproduce moving image data related to data (a) from storage media. That is, a so-called time shift function for shifting the viewing time. In this case, it is assumed that the storage media can record and play back simultaneously.

Mode 7: Only the TS of (a) is recorded while decoding the reproduction data from the storage medium. That is, a time shift function. In this case, it is assumed that the storage media can record and play back simultaneously.

For modes 4 to 7, transmission path I
Even when there is one / F, the functions described in each case can be realized. The transmission paths I / F1 and I / F2 may include a tuner corresponding to satellite / terrestrial / cable TV or may include an interface with a communication network.

In FIG. 1, the dotted frame indicates the boundary when the present invention is constructed on the semiconductor integrated circuit 15. That is, in the present embodiment, the selector 3, the main demultiplexer 4, the sub demultiplexer 5, the selector 6, the storage medium I / F 7, the clock reproduction circuit 8, the MPEG decoder 9, the graphic decoder 11, and the mix circuit 12
, Input terminals a and b, connection terminals c and d, and terminals e, f, and g
Are formed on the semiconductor integrated circuit 15.

FIG. 4 is a block diagram showing the configuration of the second embodiment of the present invention. In FIG. 4, the same parts as those in FIG. 1 indicate the same reference numerals. In FIG. 4, the graphic decoder 11 is arranged outside the conductor integrated circuit 15, and the output of the sub demultiplexer 5 is connected to the terminal of the semiconductor integrated circuit 15. g, the signal is input to the graphic decoder 11, and the output of the graphic decoder 11 is input to the mix circuit 12 via the terminal j of the conductor integrated circuit 15. Also,
The MPEG decoder 9 is connected via a terminal i of the semiconductor integrated circuit 15 to a decoder buffer 10 arranged outside the conductor integrated circuit 15. Here, the main demultiplexer 4, the sub demultiplexer 5, and the storage media I / F
7, the selector 3, the selector 6, the input terminals a and b, the connection terminals c and d, and the terminal h
Configured above.

FIG. 5 is a block diagram showing the configuration of the third embodiment of the present invention. In FIG. 5, the same parts as those in FIG. 4 indicate the same symbols, and the MPEG decoder 9 and the mix circuit 12 are further provided outside the semiconductor integrated circuit 15 in FIG. Is output via a terminal k of the semiconductor integrated circuit 15.
The signal is input to the MPEG decoder 9 and the sub-demultiplexer 5
Is input to the graphic decoder 11 via the terminal h of the semiconductor integrated circuit 15. Here, the main demultiplexer 4, the sub demultiplexer 5, and the storage medium I
The / F7, the selector 3, the selector 6, the input terminals a and b, the connection terminals c and d, the terminal g, and the terminal h are formed at least on the semiconductor integrated circuit 15.

FIG. 6 is a block diagram showing the configuration of the fourth embodiment of the present invention. 6, the same parts as those in FIG. 1 indicate the same reference numerals. In the present embodiment, after the main demultiplexer 4 and the sub demultiplexer 5,
The speed conversion buffers 18 and 19 are connected, respectively, and the outputs of the speed conversion buffers 18 and 19 are multiplexed by a multiplexer 20, and the output is supplied to the MPEG decoder 9 and the selector 6.

FIG. 7 is a diagram showing the timing of packet multiplexing. V1, A1, and S1 are video, audio,
It means a packet of the system, and the subscript indicates the program number. With reference to a packet slot formed based on the clock generated from the main demultiplexer 4,
A packet is written from the main demultiplexer 4 to the speed conversion buffer 18 in FIG. 8 (a). Although the output (b) of the sub-demultiplexer 5 is asynchronous with respect to this, double-speed reading is performed by the speed conversion buffers 18 and 19, and the output timing of both is adjusted based on the packet slot reference (c),
(D), and the output (e) of the multiplexer 20 is obtained.

To decode two types of programs,
As shown in FIG. 8, the contents of the decoder buffer 10 are such that the main demultiplexer 4 and the sub demultiplexer 5 share a memory space. In the temporal decoding schedule division, as shown in FIG. 9, slots of a decoding period are assigned based on a video frame on the main demultiplexer 4 side, and video or audio is decoded within each period. The output of the multiplexer 20 is added to the input of the selector 6, and the multiplexed TS packet can be recorded at double speed. At this time, since the arrival time information of the TS packet on the main demultiplexer 4 side is stored,
When the data storage medium 13 is normally played back and supplied to the main demultiplexer 4 and the sub demultiplexer 5, a multiplexed output is also obtained.

With such a configuration, it is possible for the user to select MPEG images / sounds from a series of TS packets input from different transmission paths, and to combine and display two types of moving images. Others are the same as the embodiment of FIG.

FIG. 10 is a block diagram showing the configuration of the fifth embodiment of the present invention. FIG. 10 shows a configuration in which the graphic decoder 11 is added to the configuration of FIG. 6 and the output of the sub-demultiplexer 5 is supplied to the input. Thus, the combined display of the two moving images or the combined display of the moving image and the graphic data can be performed. The rest is the same as the embodiment of FIG.

[0046]

According to the present invention, the selective recording process on the data storage medium and the selective reproduction process on the display are
A digital signal processing device that shares a circuit and an element can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of an MPEG TS packet together with its hierarchical structure.

FIG. 3 shows an example of a recording and reproducing function by a selective combination of an input selector 3 of a main demultiplexer 4 and a sub demultiplexer 5 and a selector 6 of an input of a storage medium I / F 7 in FIG. FIG.

FIG. 4 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a fourth exemplary embodiment of the present invention.

FIG. 7 is a diagram showing the timing of packet multiplexing.

FIG. 8 is a conceptual diagram showing the contents of a decoder buffer.

FIG. 9 is a diagram showing timings when a plurality of decodings are performed.

FIG. 10 is a block diagram showing a configuration of a fifth exemplary embodiment of the present invention.

[Explanation of symbols]

1, 2, transmission line interface, 3, 6, selector, 4
... Main demultiplexer, 5 ... Sub demultiplexer, 7 ...
Storage media interface, 8 clock recovery circuit,
9 MPEG decoder, 10 16 decoder buffer, 11 graphic decoder, 12 mix circuit, 13 data storage medium, 14 VCO, 15
Semiconductor integrated circuit, 18, 19 ... buffer, 20 ... multiplexer, a, b ... input terminal, c, d ... connection terminal, e,
f, g, h, i, j, k, l, m ... terminals.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroaki Shirane 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi Image Information Systems Co., Ltd. (72) Eiji Yamamoto 5--22, Josuihoncho, Kodaira-shi, Tokyo No. 1 Inside Hitachi Ultra-LSE Systems Co., Ltd. (72) Inventor Satoshi Motosu 3-16-6 Shinmachi, Ome-shi, Tokyo F-term in the Hitachi, Ltd. Device Development Center Co., Ltd. F term (reference) 5C053 FA20 FA21 FA23 GA08 GA11 GB06 GB11 GB12 GB36 GB37 JA07 JA22 LA06 5D044 AB05 AB07 BC01 CC03 CC05 DE14 DE49 EF03 FG10 FG21 GK07 HH07 HL04 JJ06 JJ07 5K028 AA08 BB04 CC05 EE03 EE08 KK01 KK03 KK32 NN32 PP02 PP03 SS15 SS17

Claims (8)

[Claims] An input is a transmission data stream obtained by multiplexing a partial stream composed of compression-encoded video data, audio data, and accompanying system data.
A demultiplexer for extracting a partial stream composed of a set of video data, audio data, and accompanying system data; an interface connected to a data storage medium for recording and reproducing at least a partial stream of the transmission data stream; A first selector for selecting an input to the demultiplexer from the transmission data stream and a stored data stream reproduced by the data storage medium; and an input to the interface means for the demultiplexer. A second selector for selecting between an output from a multiplexer and an output from the first selector; and when recording on the data storage medium, the second selector selects the demultiplexer. And an output from the first selector. Digital data input to the demultiplexer by selecting the stored data stream or the transmission data stream by the first selector when reproducing the partial stream. Signal processing device. 2. The data storage medium according to claim 1, wherein said demultiplexer comprises a main demultiplexer for extracting a set of video data and audio data, and a sub demultiplexer for extracting associated system data. During the recording, the input to the connection means for the data storage medium is selected from among the output from the main demultiplexer and the output from the sub demultiplexer, and the output from the first selector. A digital signal processing device characterized by inputting a digital signal. 3. The apparatus according to claim 2, further comprising a compression code decoder for decoding an output of said main demultiplexer, and a still picture decoder for decoding an output of said sub demultiplexer. A digital signal processing device for outputting a decoded video signal and audio signal. 4. The apparatus according to claim 2, wherein a main buffer for converting the speed of the output of the main demultiplexer, a sub-buffer for converting the speed of the output of the sub-demultiplexer, the main buffer and the sub-buffer. Multiplexing means for multiplexing the output of the digital signal processing apparatus, wherein an output of the multiplexing means is input to the compression code decoder when the partial stream is reproduced. 5. The apparatus according to claim 4, further comprising: a still image decoder for decoding an output of said sub-demultiplexer, and outputting a decoded video signal and an audio signal when reproducing said partial stream. Digital signal processor. 6. The digital signal processing apparatus according to claim 1, wherein said demultiplexer, said connection means, said first selector and said second selector are formed on a semiconductor integrated circuit. . 7. A transmission data stream obtained by multiplexing a partial stream composed of compression-encoded video data, audio data, and accompanying system data is input.
A main demultiplexer for extracting a set of video data and audio data; a sub-demultiplexer for extracting compression-encoded accompanying system data; and a data storage medium for recording and reproducing at least a partial stream of the transmission data stream. A storage media interface having a terminal; a first selector for selecting an input to the demultiplexer from the transmission data stream from an input terminal and a storage data stream from the storage media interface; A second selector for selecting a recording input to the storage media interface means from an output from the main demultiplexer and the sub demultiplexer and an output from the first selector; and an output from the main demultiplexer. Compressed code to decode An output terminal for inputting the output of the sub-demultiplexer to a still image decoder; a decoding input terminal from the output of the still image decoder; an output of the compression code decoder and an input from the decoding input terminal. And a combining output terminal for outputting a combined output. The main demultiplexer, the sub-demultiplexer, the storage media interface, the first selector, and the second selector. A digital signal processing device, wherein the input terminal, the connection terminal, the output terminal, and the decoding input terminal are configured on a semiconductor integrated circuit. 8. A transmission data stream formed by multiplexing a partial stream composed of compression-encoded video data, audio data, and accompanying system data is input.
A main demultiplexer for extracting a set of video data and audio data; a sub-demultiplexer for extracting compression-encoded accompanying system data; and a data storage medium for recording and reproducing at least a partial stream of the transmission data stream. A storage media interface having a terminal; a first selector for selecting an input to the demultiplexer from the transmission data stream from an input terminal and the storage data stream; A second selector for selecting a recording input from an output from the main demultiplexer and the sub demultiplexer and a bypass output from the first selector; and inputting an output of the main demultiplexer to a compression code decoder A first output terminal for performing A second output terminal for inputting an output of the sub-demultiplexer to a still image decoder, the main demultiplexer, the sub-demultiplexer, the storage media interface means, the first selector, and the second selector A digital signal processing device, wherein the input terminal, the connection terminal, the first output terminal, and the second output terminal are configured on a semiconductor integrated circuit.