JP2002016489A - Programmable logic circuit device and information processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce both a non-used resource area and global wiring delay in a reconfigurable programmable logic circuit device. SOLUTION: A programmable logic circuit device 24 is configured by alternately and two-dimensionally locating an S cell group 102 composed of plural S cells 100S in small size (small grain size) and an L cell group 106 composed of plural L cells 100L in a large size (large grain size). Thus, the non-used resource area can be reduced rather than the large grain size of cells, a global wiring number is reduced rather than the small grain size of cells and delay time to be generated on global wiring can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable logic circuit device and an information processing system, and more particularly, to a programmable logic circuit device having a plurality of logic cells for generating an arbitrary logic function by changing an internal circuit configuration. The present invention relates to a programmable logic circuit device that reconfigures at least a part of circuit functions by updating a circuit configuration inside a cell and a connection state between the logic cells, and an information processing system.

[0002]

2. Description of the Related Art In recent years, in the field of digital logic circuit products, particularly application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) and programmable logic devices (PLDs) have been developed in order to shorten the development period of products.
Such programmable logic circuit devices are widely used.

[0003] These programmable logic circuit devices (hereinafter referred to as "programmable logic circuits") are capable of freely configuring internal logic circuits and connections between the logic circuits by reading circuit information describing the logic circuits. Can be. This eliminates the need for integrated circuit fabrication time of several weeks to several months after the circuit design, which was required before the use of the programmable logic circuit. In particular, as in the invention disclosed in U.S. Pat.No. 4,700,187,
2. Description of the Related Art Electrically reconfigurable programmable logic circuits have the advantage that once fabricated circuits can be freely changed as many times as necessary, and are becoming more and more widely used.

Here, the structure of a partially reconfigurable programmable logic circuit will be described. FIG. 13 shows a general structure of a programmable logic circuit.

As shown in FIG. 13, a programmable logic circuit 200 includes a plurality of two-dimensionally arranged logic cells (hereinafter referred to as “cells”) 202 and an input / output terminal 2.
04 and a wiring area 206.

Each cell 202 can generate an arbitrary logic function by changing the internal circuit configuration. In the wiring area 206, the space between each cell is set vertically and horizontally (horizontally and vertically)
A cell-to-cell wiring bus for connecting the cells is provided (so-called global wiring). The wiring in the wiring region 206 allows the connection between the cells 202 and each logical cell 2
02 and the input / output terminal 204 can be arbitrarily connected.

[0007] The programmable logic circuit 200
As shown in FIG. 14, a configuration memory 208 for storing circuit information is provided. The configuration memory 208 includes rewritable memory elements such as SRAMs and DRAMs provided in the cells 202 and the wiring area 204.

This configuration memory 208
, And the data of the new circuit information is stored, the circuit configuration in the cells 202 and the input / output terminals 204 between the cells 202 and between the cells 202 are stored in accordance with the circuit information.
The connection state of the wiring region 206 interconnecting them is reconfigured. This series of operations is called a configuration.

In the programmable logic circuit 200, a part of a configuration memory (not shown) is rewritten, so that even if the programmable logic circuit 200 is operating, a circuit function (hereinafter, referred to as "hardware") is partially performed. It can be reconfigured. In the programmable logic circuit 200, data to be processed is input to the circuit element 210 formed by this reconfiguration, and the processing result is output.

As described above, on the programmable logic circuit, there is a cell in which a circuit having a programmable function is formed as a block as a unit constituting hardware. A part of hardware is configured in this cell, and each wiring of an inter-cell wiring bus (so-called global wiring) is switched by switching between other cells as needed to form one piece of hardware. The cell size (granularity) varies depending on the type of programmable logic circuit and the manufacturer of the programmable logic circuit.

There are advantages in the size of the cell. When the cell granularity is large, that is, when the number of transistors included in one cell is large, the scale of a circuit that can be realized with only one or a small number of cells increases.
Therefore, it is possible to reduce a delay time due to a stray capacitance or the like when driving a global wiring, which is generally regarded as a problem in realizing a high-speed circuit, in which a global wiring extending between cells is used less frequently. . Further, since a large number of wirings are performed in a cell, it is possible to reduce the number of global wirings required to connect all the cells on one programmable device.

On the other hand, when the cell granularity is small, that is, when the number of transistors included in one cell is small,
Under a partially rewritten situation, it is possible to reduce unused resources. In a programmable logic circuit, even if a cell uses only a few percent of the cell, the entire cell is used. Therefore, the smaller the granularity, the more the area where the circuit is not configured is rewritten. Therefore, there is a high possibility that it can be effectively used as a storage area.

[0013]

However, the merit due to the size of the cell granularity is, in other words, a two-sided relationship with the demerit. When the cell granularity is large, a small area of the cell can be used as a circuit. Even if the cell is used to configure the cell, the cell becomes unusable unless the circuit information is erased, so that the possibility of leaving a large amount of unused resource areas increases compared to the case where the cell granularity is small. There was a problem that it would.

On the other hand, when the granularity of the cells is small, the number of cells formed on one programmable logic circuit is large, and the number of global wirings necessary to connect the cells is large when the granularity of the cells is large. However, there is a problem that the number increases in comparison with the case of

Further, in order to configure hardware of the same size as when the cell granularity is large, more cells are required, so that the number of global wirings connected to realize the function of the hardware is limited. Will increase. Accordingly, there is a problem that the total delay time of wiring generated when driving the global wiring becomes large, which is particularly fatal when the configured hardware is driven at high speed.

In order to reduce the wiring delay when the granularity of the cell is small, as shown in FIG. 15, there is a device in which the configuration of the cell and the wiring is devised (for example, model number AT40K manufactured by Atmel, USA) The programmable device shown in the above, for details, Atmel's specifications "AT40K FPGAs
with FreeRAM ").

That is, a plurality of cells 220 (sixteen in FIG. 15) having a small particle size are grouped together to form a cell group 222, and each cell group 222 is connected to all the cells 220 in the cell group 222. By providing a bus 224 for adjacent wiring which can be called a quasi-global wiring, and connecting the cell groups 222 with a global wiring 226 which is a long-distance wiring, wiring delay is suppressed.

However, there is a limit to the reduction of the wiring delay by using the quasi-global wiring and the global wiring together, and it is not sufficient to meet the demand for further higher speed in the future.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a programmable logic device capable of realizing both a reduction in an unused resource area in a reconfigurable programmable logic circuit and a reduction in global wiring delay. It is an object to provide a circuit device and an information processing system.

[0020]

According to a first aspect of the present invention, there is provided an image processing apparatus comprising: a plurality of logic cells for generating an arbitrary logic function by changing an internal circuit configuration; A programmable logic circuit device that reconfigures at least a part of circuit functions by updating a circuit configuration inside a logic cell and a connection state between the logic cells, wherein the plurality of logic cells have a plurality of sizes. It is characterized by being constituted by a combination of logic cells.

According to the first aspect of the present invention, the programmable logic circuit device is constituted by logic cells of a plurality of sizes (hereinafter, simply referred to as "cells"). The cell used for the configuration of the circuit function can be selected from a plurality of sizes.

As a result, the unused resource area can be reduced as compared with the case where the programmable logic circuit device is composed of only cells of a large size, and the number of global wirings can be reduced as compared with the case where the programmable logic circuit device is composed of only cells of a small size. Thus, it is possible to reduce the delay time generated in the global wiring.

The size and arrangement of cells constituting the programmable logic circuit device are not particularly limited, and cells of any size may be arranged. For example, the aspect ratio may be different for each size, or cells of each size may be randomly arranged.

In particular, as described in claim 2,
The size of each of the logic cells is determined by N of the smallest size logic cell.
It is good to have a size of × N (N is a natural number).

Further, as described in claim 3,
The arrangement position of each of the plurality of logic cells is such that the logic cells of the same size are two-dimensionally arranged, and the size of each of the logic cells is M × M (M is a natural number) of the maximum size logic cells. It is preferable that a logic cell group is formed, and the logic cell groups are arranged at two-dimensionally arranged positions such that the sizes of the logic cells constituting the adjacent logic cell groups are different from each other.

According to a fourth aspect of the present invention, there is provided an information processing apparatus comprising the programmable logic circuit device according to any one of the first to third aspects and executing a series of processes specified by a predetermined program. A system, wherein at least a part of the series of processes is executed by the programmable logic circuit device.

According to a fourth aspect of the present invention, the programmable logic circuit device according to any one of the first to third aspects is incorporated in an information processing system,
The programmable logic circuit device can execute at least a part of the processing performed by the information processing system (hereinafter, the processing performed by the programmable logic circuit is referred to as Processing)). That is, the circuit function of the programmable logic circuit device is reconfigured so that the hardware process can be executed, and the programmable logic circuit device executes the hardware process.

At this time, since the programmable logic circuit device is composed of cells of a plurality of sizes as described above, it is necessary to select and reconfigure cells necessary and sufficient for execution of hardware processing from the plurality of sizes. Can be. As a result, the time required for the reconfiguration of the programmable logic circuit device and the reduction of the processing time when information processing is performed by the programmable logic circuit device can be simultaneously realized, and the speed of processing based on the application program in the information processing system can be increased. Can be achieved.

[0029]

Next, an example of an embodiment according to the present invention will be described in detail with reference to the drawings.

(First Embodiment) <System Configuration> FIG. 1 shows a hardware configuration of an information processing system incorporating a programmable logic circuit device to which the present invention is applied.

As shown in FIG. 1, in this information processing system 10, a main memory 18 composed of, for example, a DRAM is connected to a host bus 14 of a CPU 12 via a memory controller (not shown) included in a chip set 16. It is connected.

The host bus 14 is connected to the chip set 1
6 is connected to the PCI bus 20 via a host-PCI bus bridge (not shown). The PCI bus 20 has a programmable logic circuit interface 2
2 and a programmable logic circuit device (hereinafter, referred to as “programmable logic circuit”) 24. The details of the programmable logic circuit 24 will be described later.

The host bus 14 is connected to a hard disk drive 28 via a hard disk interface 26. Furthermore, by being connected to a network 32 such as an external LAN or the Internet via the communication interface 30, it is also connected to an external storage device.

An application program 50 for performing information processing in the information processing system 10 is stored in the hard disk read / written by the hard disk drive 28.
Is stored (see FIG. 2).

The storage device 34 stores circuit information (hereinafter, referred to as "hardware module") 52 for reconfiguring the programmable logic circuit 24 (FIG. 2).
reference). Note that the application program 50 may be stored in the storage device 34.

The hardware module 52 obtained from the storage device 34 is temporarily stored in the hard disk of the hard disk drive 28 or the main memory 18. Note that the programmable logic circuit 2
4 may be provided with a local memory, and the hardware module 52 obtained from the storage device 34 may be stored in the local memory.

The hardware module 52 stored in the hard disk of the hard disk drive 28 or the main memory 18 in the information processing system 10 is used for reconfiguring the programmable logic circuit 24 as needed. By this reconfiguration, hardware (a circuit function based on the hardware module 52) is configured on the programmable logic circuit 24, and the programmable logic circuit 24 can execute information processing.

In the information processing system 10, when the application program 50 is started and the CPU 12 executes various types of information processing instructed by the application program 50, the CPU 12 causes the programmable logic circuit 24 to execute some processing, It is designed to be faster.

<Configuration of Application Program and Hardware Module> Next, the application program 50 and the hardware module 52 will be described.

The application program 50 divides a series of processes executed by the program into a plurality of processes, and is configured as a module for each of the separated processes (hereinafter, a module of each process). This is called a “processing module”). That is, in the information processing system 10, processing of each information module constituting the application program 50 is performed by the CPU 12 or the programmable logic circuit 24 for each processing module.

Each processing module constituting the application program 50 is a software program 54 in which the processing executed by the CPU 12 is described in a programming language (hereinafter, the software program for each processing module is referred to as a “software module”) 54. (See FIG. 2). Therefore, the application program 50 has a set of a plurality of software modules 54.

On the other hand, the hardware module 52
It describes circuit information for configuring on the programmable logic circuit 24 hardware that performs the same processing as that performed by the PU 12 according to each software module 54. Therefore, the hardware module 52
Are prepared for each software module.

In this case, the application program 5
In the case of 0, it is necessary to associate the software module 54 and the hardware module 52 that perform the same processing with each other. For this reason, in the present embodiment, a software module 54 and a hardware module 52 that perform the same processing are provided in the application program 50.
And an identification code for associating them with each other.

More specifically, as shown in FIG. 3, the main unit 56 composed of a set of a plurality of software modules 54 and the identification of the hardware modules 52 corresponding to the respective software modules 54 as described above. The application program 50 is constituted by the header section 60 constituted by the reference numeral 58.

In the header section 60, the identification code 58 of the hardware module 52 corresponding to the software module 54 of the main body section 56 is described in accordance with the execution order of the processing modules by the application program 50. Therefore, when there is a software module 54 to be repeatedly processed, the identification code 58 of the hardware module 52 corresponding to the software module is repeatedly described repeatedly.

The identification code 58 is included in the horizontal direction and the vertical direction when the circuit information described in the hardware module 52 and the hardware module 52 are rectangularly represented on the programmable logic circuit 24. The number of PFUs (Programmable Function Units), which are components of the programmable logic circuit 24, are described.

<Functional Configuration> Next, the information processing system 10
Will be described. FIG. 2 shows a functional configuration when the processing of the application program 50 of the information processing system 10 is executed.

The information processing system 10 includes a hardware module acquisition unit 80 and an execution module determination unit 82
It has the function of In the present embodiment, it is assumed that the hardware module acquisition unit 80 and the execution module determination unit 82 are implemented as software as one function of the OS of the information processing system 10.

The hardware module acquisition means 80
An acquisition request sending unit 84 and an acquisition reconfiguring unit 86 are provided.

The acquisition request sending means 84 issues an acquisition request for the hardware module 52 necessary for processing of the application program 50, and acquires the hardware module 52 from the storage device 34.

The acquisition reconfiguration means 86 reconfigures hardware (circuit function) on the programmable logic circuit 24 based on the acquired hardware module 52. At this time, the identification code 58 of the hardware module 52 used for the reconstruction is recorded in the identification code recording means 88. Note that storage devices in the system (such as the hard disk of the hard disk drive 28 and the main memory 18)
Function as identification code recording means 88.

The execution module determining means 82 determines whether the processing of the application program 50 is to be performed by a software module or a hardware module for each processing module. That is, it is determined whether the processing is performed by the CPU 12 or the programmable logic circuit 24. Also, the processing of the processing module is executed by the determined module (software module / hardware module).

A selection condition setting means is provided in the execution module determination means 82, and various selection conditions such as processing time by software modules and hardware modules, memory consumption, reconfiguration time of the programmable logic circuit 24, and the like are set in advance. Items may be set, and at least one of the items may be used as a condition for determining an execution module.

<Detailed Configuration of Programmable Logic Circuit> FIG. 4 shows a programmable logic circuit 24 to which the present invention is applied.
It is shown.

As shown in FIG. 4, the programmable logic circuit 24 includes a plurality of small-sized (small-grain) cells (hereinafter, referred to as “S cells”) 100S and S cells 1
00S are two-dimensionally arranged in 4 rows × 4 columns (4 × 4),
In other words, a plurality of large-size (large-grain) logic cells (hereinafter, referred to as “L cells”) having a function equivalent to 16 S cells 100 are provided.

The number of S cells 100S is 64 in 8 rows × 8 columns (8
2 × 8) to form the S cell group 102,
The L cells 100L are two-dimensionally arranged in two rows × 2 columns (2 × 2) to form an L cell group 104, and the S cell group 102 and the L cell group 104 are alternately arranged in a checkered pattern. Are located in

The programmable logic circuit 24 also has a configuration memory (not shown), as in the prior art, and has a programmable function with the S cell 100S and the L cell 100L.

In the following, when the S cell 100S and the L cell 100L are described without distinction, they will be collectively called the cell 100.

In general, the size (granularity) of a logic cell is defined by the number of transistors included in cell 100.
Hereinafter, the structures of the S cell 100S and the L cell 100L will be described in detail. FIG. 5 shows an example of the S cell 100S and the L cell 100L.

As shown in FIG. 5A, the S cell 100S has an input section 110 composed of four input terminals and an output section 112 composed of one output terminal. The S cell 100S includes, for example, a circuit 114 shown in a dotted frame.
A circuit, such as A or a circuit 114B, for selectively switching the wiring by a control signal (CNT) is configured.

On the other hand, as shown in FIG. 5B, the L cell 100L includes 16 S circuits 120 having the same function as the S cell 100S.
Are two-dimensionally arranged in 4 rows × 4 columns. Also, L cell 1
The 00L input section 122 has 16 input terminals, and the output section 124 has 4 output terminals.

Note that not all 16 S circuits 120 in the L cell 100L have input / output terminals to the outside of the L cell 100L. It is connected to another S circuit 120 by an internal wiring 126 connecting the S circuits 120 inside the cell 100L.

Further, the programmable logic circuit 24
Between the cell group 102 and the L cell group 104, each cell group 102,
Each cell 100 in both the vertical and horizontal directions between cells 100 in 104
In order to connect the cells, an inter-cell wiring bus (global wiring bus) 130 that can be connected to the input / output terminal of each cell 100 is wired. In the programmable logic circuit 24, by switching each wiring (global wiring) of the inter-cell wiring bus 130 by switching, an arbitrary cell 1
00 are connected (that is, some or all of the circuit functions can be reconfigured).

More specifically, in the S cell group 102, as shown in FIG. 6, intercell wiring buses 130 are wired in both vertical and horizontal directions between the two-dimensionally arranged S cells 100S.
The inter-cell wiring bus 130 in the S cell group 102 includes
All terminals of cell 100S (4 input terminals and 1 output terminal
5 wirings are provided for connection with a total of 5 wirings.

In the L cell group 106, similarly, FIG.
As shown in FIG. 7, intercell wiring buses 130 are wired in both the vertical and horizontal directions between the two-dimensionally arranged L cells 100L. Twenty wires are prepared on the inter-cell wiring bus 130 in the L cell group 106 to connect to all the terminals of the L cell 100L (a total of 20 input terminals and 4 output terminals). I have.

<Operation> Next, the operation of the first embodiment will be described. First, processing in the information processing system 10 will be described.

In the information processing system 10, the application program 50 is read from the hard disk drive 28, and the application program 50 is started.

When the application program 50 is started, first, the acquisition request sending means 84 issues an acquisition request for the hardware modules 52 corresponding to all the identification codes 58 written in the header section 60 of the application program 50. The data is transmitted to the storage device 34.

Thus, all the identification codes 58 written in the header section 60 of the application program 50 are obtained.
, Ie, the hardware modules 52 corresponding to all the software modules 54 in the application program 50 are acquired from the storage device 34, and are stored in the storage device (the hard disk of the hard disk drive 28, the main memory 18, etc.) in the system. ).

Next, with respect to each hardware module 52 obtained by the obtaining and reconfiguring means 86, the hardware based on the hardware module is already configured in the programmable logic circuit 24 with reference to the storage contents of the identification code recording means 88. Is determined.

More specifically, if the obtained identification code 58 of the hardware module 52 is stored in the identification code recording means 88, it is determined that the hardware based on the hardware module 52 is already configured in the programmable logic circuit 24. I do. If the acquired identification code 58 of the hardware module 52 is not stored in the identification code recording means 88, it is determined that the hardware based on the hardware module 52 is not configured.

The acquisition and reconfiguration means 86 reconfigures the hardware based on the hardware module 52 in the programmable logic circuit 24 only when it is determined that the hardware module 52 is not configured, and replaces the identification code 58 of the hardware module 52 with the identification code. The information is recorded in the recording means 88.

The execution module (hardware module 52 / software module 54) of each processing module constituting the application program 50 is determined by the execution module determining means 82 in the order of execution of the processing by the application program 50. The processing of the processing module in which the hardware module 52 is determined as the execution module is executed by hardware based on the hardware module configured in the programmable logic circuit 24, and the processing of the processing module in which the software module 54 is determined as the execution module Causes the CPU 12 to perform processing based on the software module 54.

As described above, in the information processing system 10,
Since the processing of each processing module is performed after the execution module is determined, the processing suitable for the processing by the CPU 12 and the processing suitable for the processing by the programmable logic circuit 24 are separated and the processing of the application program 50 is performed. Can be executed. For example, by causing the programmable logic circuit 24 to execute a processing module that is repeatedly executed, the information processing system 1
0 can be performed efficiently.

Further, since the hardware module 52 is obtained from the storage device 34 and the programmable logic circuit 24 can be reconfigured, the programmable logic circuit 24 always has the optimum processing capability.

In the above description, it is assumed that the execution module of each processing module is determined at the time of executing the application program 50. Therefore, the hardware corresponding to all the identification codes 58 described in the header section 60 of the application program 50 is assumed. Although the case where the acquisition request of the wear module 52 is transmitted and acquired from the storage device 34 has been described as an example, the present invention is not limited to this.

The execution module may be determined before the execution of the application program 50. In this case, only the acquisition request of the hardware module 52 corresponding to the processing module to be executed by the hardware module 52, that is, determined to be processed by the programmable logic circuit 24, may be transmitted.

Next, a comparison will be made between the programmable logic circuit of this embodiment and a conventional programmable circuit composed of only cells of the same size.

FIG. 8 shows the programmable logic circuit 24 of this embodiment, FIG. 9 shows a programmable logic circuit 200A composed of only L cells 100L, and FIG.
Programmable logic circuit 200 composed of only 00S
On B, a conceptual diagram when hardware of the same scale (1.5 rows × 1.5 columns of the L cell 100L) is configured based on the hardware module 52 is shown. 8 to 10, the hardware module 52
The configuration area of the hardware H configured based on the above is indicated by a dotted line.

In the programmable logic circuit 200A composed of the L cell 100L, as shown in FIG. 9, when the hardware H having a size of 1.5 rows × 1.5 columns of the L cell 100L is constructed, four All the L cells 100L are in use. Therefore, although there is an unused area (shaded area) in the area of the four L cells 100L, other hardware cannot be configured and used in this unused area, and the unused resource area is not used. Will remain as. The unused resource area at this time is the L cell 100
This corresponds to 1.75 L's.

On the other hand, in the programmable logic circuit 24 according to the present embodiment, by arranging the hardware H as shown in FIG. (Shaded area) can be reduced.

On the other hand, in the programmable logic circuit 200B composed of the S cells 100S, as shown in FIG. 10, all areas other than the hardware H can be used for other hardware modules. However, in the programmable logic circuit 200B formed by the S cell 100S, the programmable logic circuit 200B formed by the L cell 100L is used.
More cells 100 are used to configure the hardware H than A, and the number of global wirings increases. Specifically, the programmable logic circuit 200
In B, 36 cells 100 are used for hardware H. Further, the number of cells 100 on the programmable logic circuit is also large.

On the other hand, the programmable logic circuit 2
4, as shown in FIG. 8, the number of cells 100 required to configure the hardware H may be only 14. Also, a programmable logic circuit 200B composed of S cells 100S
Needless to say, when the size of the programmable logic circuit 24 is the same as that of the programmable logic circuit 200B, the total number of cells 100 is smaller than that of the programmable logic circuit 200B.

That is, by using the programmable logic circuit 24 of the present embodiment, the total number of global wirings and the connection when configuring the hardware H are improved as compared with the case where the entire programmable function is configured by the S cell 100S. Global wiring number can be reduced.

As described above, in the first embodiment, the S cell group 102 including a plurality of S cells 100S and the L cells
By configuring the programmable logic circuit 24 with the L cell group 106 composed of the cells 100L, the unused resource area can be reduced as compared with the case where the cell granularity is large, and the number of global wirings can be reduced as compared with the case where the cell granularity is small. And the delay time generated in the global wiring can be reduced.

Further, by incorporating the programmable logic circuit 24 having such characteristics into the information processing system 10 and using it, the time required for reconfiguring the programmable logic circuit 24 and the time required for performing information processing by the programmable logic circuit 24 are reduced. The processing time can be reduced at the same time. Further, by reducing the unused resource area, the number of hardware that can be configured on the programmable logic circuit 24 can be increased. That is, it is possible to speed up processing based on the application program 50 in the information processing system 10.

The essential point of the present invention is to reduce the unused resource area and the delay time by configuring the programmable logic circuit 24 with cells of a plurality of sizes. The present invention is not limited to the one described in the first embodiment.

That is, in the first embodiment, an L cell group 106 in which four L cells 100L are two-dimensionally arranged in 2 rows × 2 columns, and 64 S cells 100S are arranged in 8 rows × 8 columns. Although the programmable logic circuit 24 including the S cell group 102 arranged in a dimension is described as an example, the present invention is not limited to this.

The size of each cell group (the number of cells 100) is
Depending on the size of the programmable logic circuit and the size, type, performance, etc. of the hardware module 52 (hardware configured on the programmable logic circuit 24), it can be configured in various sizes. It is not limited.

In the first embodiment, the L cell 10
0L or S cell 100S is replaced with L cell group 106 or S cell group 10.
2, the case where two-dimensional arrangement is performed alternately in a checkered pattern has been described as an example, but the present invention is not limited to this. The size of the programmable logic circuit and the hardware module 52 (programmable logic circuit 2
For example, the number of arrays may be changed, or one side of the programmable logic circuit may be composed of small cells and the other side may be composed of large cells, depending on the size, type, performance, etc. .

In the first embodiment, the L cell 10
Although the description has been made using two types of cells, that is, 0L and S cell 100S, the present invention is not limited to this. It goes without saying that a programmable function can be realized above.

In the first embodiment, the L cell 10
Although the case where 0L has a circuit function integrating 16 functions of the S cell 100S has been described as an example, the present invention is not limited to this. L cell 100L and S cell 100
It goes without saying that even if there is no correlation between the functions of S, various cell sizes can be applied based on the difference in the cell size and the difference in the number of global wirings.

(Second Embodiment) Next, as a second embodiment, a case will be described in which a programmable logic circuit device is formed using cells of four different sizes. FIG. 11 shows the configuration of this programmable logic circuit device.

As shown in FIG. 11, a programmable logic circuit device (hereinafter referred to as "programmable logic circuit")
24A are S cells 10 in order from the smallest cell size.
0S, MA cell 100MA having the same function as four S cells 100S, MB cell 100MB having the same function as 16 S cells 100S, and functions equivalent to 64 S cells 100S. L cell 100L and 4
It includes a cell 100 of a kind.

In order to realize the same scale of function as the L cell 100L, four MB cells 100MB are two-dimensionally arranged in 2 rows × 2 columns to form an MB cell group 150. Similarly, the MA cells 100MA are two-dimensionally arranged in 16 rows and 4 columns to form an MA cell group 152, and the S cells 100S
Is a two-dimensional array of 64 cells in 8 rows × 8 columns, and S cell group 1
54.

The programmable logic circuit 24A has one L cell 100L, one MA cell group 152, one MB cell group 150, and one S cell group 154, which are two-dimensionally arranged in 2 rows × 2 columns.

In the programmable logic circuit 24A, as in the first embodiment, in order to connect the cells 100, an inter-cell wiring bus 130 connectable to the input / output terminal of each cell 100 is provided. (The details are omitted because they are almost the same as the first embodiment.)

The programmable logic circuit 24A is used by being incorporated in the information processing system 10, for example, in place of the programmable logic circuit 24 described in the first embodiment.

Next, the operation of the second embodiment will be described.
A description will be made in comparison with a conventional programmable circuit including only cells of the same size.

FIG. 12 shows a programmable logic circuit 24A of the present embodiment on the same scale (L cell 100L) as that of FIGS.
(1.5 rows × 1.5 columns) hardware H is configured.

Programmable logic circuit 2 of the present embodiment
In 4A, by arranging the hardware H as shown in FIG. 12, all the unused areas can be used for other hardware configurations. That is, the unused resource area can be eliminated.

As described above, increasing the number of types of cell sizes is more effective in reducing unused resource areas on the programmable logic circuit. In other words, by configuring the programmable logic circuit with cells of a larger number of cell sizes in order to reduce the unused resource area, it is possible to flexibly cope with hardware of various scales.

In the programmable logic circuit 24A, the cells 10 used to configure the hardware H
The number of 0s is 27, which is smaller than the case where only the S cell 100S is used (36).

In the first and second embodiments,
With the minimum cell size (S cell 100S) as a basic unit, the size of each cell 100 is calculated as N rows × N
Although a case where the size is equivalent to the size of a column (N is a natural number: 1, 2, 3,...) Has been described as an example, the present invention is not limited to this. For example, N × M basic units (N and M are natural numbers and N ≠ M) may be used, or may not be a natural number times the basic unit.

However, in consideration of the delay time due to global wiring, it is preferable that the hardware of the programmable logic circuit is formed in a rectangular shape. By setting the size of each cell 100 to be N × N of the basic unit, Each cell 100 can be arranged so as to easily divide an area into a rectangular shape.

In the first and second embodiments,
Cells 100 of the same size are two-dimensionally arranged to form a cell group of a size corresponding to M × M cells (M is a natural number) of L cells 100 of the maximum size for each size. The case where the cell groups are two-dimensionally arranged so that the sizes of the constituent cells 100 are different from each other has been described as an example, but the present invention is not limited to this.

However, by forming a cell group as described above and arranging it two-dimensionally, when configuring a hardware module on a programmable logic circuit, its configuration area is minimized so that an unused resource area is minimized. Is easier to determine.

[0108]

As described above, the present invention has an excellent effect that both the reduction of the unused resource area and the reduction of the global wiring delay in the reconfigurable programmable logic circuit device can be realized. Having.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a hardware configuration of an information processing system according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a functional configuration of the information processing system according to the first embodiment of the present invention.

FIG. 3 is a conceptual diagram showing a configuration of an application program.

FIG. 4 is a diagram showing a configuration of a programmable logic circuit device according to the first embodiment of the present invention.

5A is a diagram showing a detailed configuration of a small cell (S cell), and FIG. 5B is a diagram showing a detailed configuration of a large cell (L cell).

FIG. 6 is a diagram showing wiring of an inter-cell wiring bus in an L cell group.

FIG. 7 is a diagram illustrating wiring of an inter-cell wiring bus in an S cell group.

FIG. 8 is a conceptual diagram showing a case where a hardware module is configured on the programmable logic circuit device according to the first embodiment.

FIG. 9 is a conceptual diagram showing a case where a hardware module is configured on a conventional programmable logic circuit device configured only with large cells (L cells).

FIG. 10 is a conceptual diagram showing a case where a hardware module is configured on a conventional programmable logic circuit device configured only with small cells (S cells).

FIG. 11 is a configuration diagram of a programmable logic circuit device according to a second embodiment of the present invention.

FIG. 12 is a conceptual diagram showing a case where a hardware module is configured on a programmable logic circuit device according to a second embodiment.

FIG. 13 is a diagram showing a configuration of a conventional general programmable logic circuit device.

FIG. 14 is a conceptual diagram for describing a configuration memory and its operation (configuration) in a programmable logic circuit device.

FIG. 15 is a diagram showing a configuration of a programmable logic circuit device in which a configuration of a conventional cell and wiring is devised.

[Explanation of symbols]

Reference Signs List 10 information processing system 12 CPU 24, 24A programmable logic circuit device 32 network 34 storage device 50 application program 52 hardware module 54 software module 80 hardware module acquisition means 82 execution module determination means 100 cell 100S S cell 100L L cell 100MA MA cell 100 MB MB cell 102 S cell group 104 L cell group 130 Inter-cell wiring bus 150 MB cell group 152 MA cell group 154 S cell group

Claims (4)

[Claims] A plurality of logic cells for generating an arbitrary logic function by changing an internal circuit configuration, and updating a circuit configuration inside the logic cell and a connection state between the logic cells, A programmable logic circuit device configured to reconfigure at least a part of circuit functions, wherein the plurality of logic cells are configured by a combination of logic cells of a plurality of sizes. 2. The programmable logic circuit device according to claim 1, wherein each size of said logic cell is a size of N × N (N is a natural number) of logic cells having a minimum size. 3. The arrangement position of each of the plurality of logic cells is such that the logic cells of the same size are two-dimensionally arranged, and M × M (M × M) logic cells of the maximum size are provided for each size. Is a natural number), and is a position where each logic cell group is two-dimensionally arranged so that the sizes of logic cells constituting adjacent logic cell groups are different from each other. The programmable logic circuit according to claim 1 or 2, wherein: 4. An information processing system comprising: the programmable logic circuit device according to claim 1, wherein the information processing system executes a series of processes specified by a predetermined program. An information processing system, wherein at least a part of the processing is executed by the programmable logic circuit device.