JP2002015968A - Automatic recognition method for input/output board of semiconductor manufacturing apparatus, and semiconductor manufacturing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing apparatus for automatically identifying an input/output(I/O) board, to which a main control part inside an apparatus controller is connected via an interface for communication. SOLUTION: This semiconductor manufacturing apparatus is provided with the interface for communication for communicating data between the main control part and the I/O board, and the address of the I/O space of the interface for communication is allocated to a port on the I/O board. Information regarding the specifications of the board is set to the port on the I/O board, the address of the I/O space corresponding to the port on the I/O board is accessed from the main control part, and the information on the specifications of the board are read out of the I/O board. Thus, the main control part prepares device configuration information from the read information on the specifications for the board.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control input / output (I / O) mounted on an apparatus such as a semiconductor manufacturing apparatus.
O) The present invention relates to a method for obtaining information on board specifications such as the board type and the number of input / output points on the main control side of the apparatus, and a semiconductor manufacturing apparatus for realizing this method.

[0002]

2. Description of the Related Art In general, for example, in a semiconductor manufacturing apparatus for performing a film forming process, an etching process, and the like on a semiconductor wafer, a motor, a vacuum gauge, a gas flow meter, various sensors, an actuator, and the like incorporated in the semiconductor manufacturing device are used. It is necessary to control accurately and quickly obtain a detection value from each sensor.

The number of control objects or detection objects increases to several hundreds as the semiconductor manufacturing equipment becomes highly complicated, and the main control unit (master side) of the whole equipment and the control objects or detection objects are changed. Device terminal corresponding to the target (slave side)
Therefore, it is necessary to perform information transmission at a higher speed because the amount of information transmission between the two increases.

[0004] Further, a semiconductor manufacturing apparatus is combined with various processing chambers for performing each step of manufacturing a semiconductor device, and is provided between processing chambers and between a cassette accommodating a large number of wafers and a processing chamber. And a transfer mechanism for transferring the wafer. An apparatus controller is provided in each of the plurality of processing chambers and the transfer mechanism so as to realize a desired operation according to an order specification of a semiconductor manufacturing apparatus and a use purpose of a user.

In such a multi-chamber semiconductor manufacturing apparatus including a plurality of processing chambers and a transfer mechanism, a multi-device controller or a multi-CPU
In order to safely, reliably and efficiently perform complicated and complicated work, it is desired to control each device controller in an integrated manner. It is also desirable that independent maintenance and independent control of the processing chamber can be performed to reduce system downtime. Therefore, a loosely coupled control system in which each device controller is connected via a network such as Ethernet (registered trademark) has been developed.
In particular, the loosely-coupled control system is provided with a device controller as a higher-level controller for the device controller in order to control the entire semiconductor device as a whole. In the case of such a loosely-coupled control system, communication is performed between the controllers according to a communication protocol according to a network used, and a program and parameters for operating the processing chamber or the transport mechanism, control information, and the like are provided. Communicated over a network. As described above, in a cluster device provided with a plurality of chambers, the amount of information transmission in the entire device further increases, so that a higher speed of transmission between the main control unit and the device terminal is required.

Therefore, in order to speed up information transmission between the main control unit and a plurality of device terminals, when digital information is encoded and transmitted via a transmission line including a plurality of lines, a predetermined interval is required. Each time, the signal state of one of the plurality of lines is changed, and the changed line is given a predetermined meaning to realize high-speed information transfer, and
There has been proposed a communication interface configured to read or write information from or to an apparatus terminal within one bus cycle of a main control unit (Japanese Patent Laid-Open No. 7-2124).
07 and JP-A-7-212369).

In a semiconductor manufacturing apparatus using a proposed communication interface, an I / O board for handling analog quantities such as flow rate, temperature and pressure, and an I / O for handling digital quantities such as valve opening / closing and on / off sensors. Board, I / O board for motor control, I / O such as dual port memory
O boards and the like are designed and manufactured for each application. The I / O board selected according to the application at the customer site is connected to a main control unit in the device controller of the semiconductor manufacturing device via a communication interface. In such a semiconductor manufacturing apparatus, the main control unit in the apparatus controller needs to hold information on the types and points of I / O boards that can be changed according to the application.

For this reason, in the conventional semiconductor manufacturing apparatus, information about the type and the number of I / O boards connected via a communication network in the apparatus controller is set and held in the main control unit in advance.

[0009]

However, as in the prior art, a semiconductor manufacturing apparatus of a type in which information relating to the type and number of I / O boards connected to the main control unit is set and held in the main control unit in advance. Then, when the device configuration including the configuration change of the I / O board is changed, not only the physical configuration of the I / O board is changed, but also the information held in the main control unit is changed according to the configuration change. It needs to be rewritten. Therefore, it takes time to correctly set parameters representing the device configuration. Also, when setting parameters manually,
There is a risk that parameter setting errors may occur.

In view of the above-mentioned problems of the prior art, the present invention relates to a semiconductor manufacturing apparatus, in which a main controller in an apparatus controller is connected via an interface for communication.
It is an object of the present invention to provide a method for automatically identifying an O board and a semiconductor manufacturing apparatus for implementing the method for automatically identifying an I / O board.

[0011]

In order to achieve the above object, the present invention sets board information in an I / O space of an I / O board, and allows a main control unit to access the I / O space. By acquiring board information, an I / O board is automatically identified.

According to a first aspect of the present invention, there is provided at least one machine for executing a semiconductor manufacturing process, a main control unit for controlling the machine, and at least one machine for inputting and outputting data between the machine. A board, and an apparatus including a communication interface for communicating data between the main control unit and the input / output board, wherein an address of the input / output space of the communication interface is assigned to a port on the input / output board In a semiconductor manufacturing apparatus including a controller, information on board specifications is set to a port of the input / output board, and an address of the input / output space corresponding to the port of the input / output board is accessed from the main control unit. Reading information on the specifications of the board from the input / output board, and reading the board read by the main control unit. An automatic recognition method of the input and output boards in a semiconductor manufacturing apparatus characterized by the information on the specifications to create the device configuration information of the device controller.

According to a second aspect of the present invention, there is provided at least one machine for executing a semiconductor manufacturing process, a main control unit for controlling the machine, and at least one machine for inputting and outputting data between the machine. An input / output board, and a communication interface for communicating data between the main control unit and the input / output board, and an address of the input / output space of the communication interface is assigned to a port on the input / output board. The input / output board has a port in which information on board specifications is set, and the main control unit corresponds to the port of the input / output board. Means for accessing an address of a writing output space and reading information relating to the specifications of the board from the input / output board; A semiconductor manufacturing apparatus, characterized in that the information regarding specifications and means for creating a device configuration information of the device controller.

As described above, according to the first and second aspects of the present invention, information on board specifications is set in the ports of the input / output board accessible from the main controller. The main control unit can download information on the input / output board from the input / output board without storing the information on the input / output board in advance. Accordingly, the main control unit can automatically recognize the device configuration, particularly, the input / output board configuration, and can change the device configuration without editing the setting information on the main control unit side. .

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the semiconductor manufacturing apparatus according to the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is an external view showing a semiconductor manufacturing apparatus according to one embodiment of the present invention,
2 is a block diagram showing a communication system applied to the semiconductor manufacturing apparatus according to one embodiment of the present invention shown in FIG. 1, and FIG. 3 is a block diagram showing a high-speed communication interface unit used in the communication system shown in FIG. It is.

As shown in FIG. 1, this semiconductor manufacturing apparatus
A plurality (for example, three) of the same or different processing devices 26
This is a so-called cluster tool in which A, 26B, and 26C are collected and combined. Each processing apparatus has a transfer arm (not shown) therein and a centrally disposed common transfer chamber 2.
8 are communicably connected to each other by a gate valve or the like. The common transfer chamber 28 includes two cassette chambers 30A, 3
0B is also communicably connected. A cassette 32 for accommodating unprocessed or processed wafers is disposed in front of each of the cassette chambers 30A and 30B, and a front panel of the apparatus is provided with an input to each device in the apparatus via a central processing unit (CPU). An input device 34 and a display 36 are provided.

In such an apparatus, the transfer of wafers to each processing apparatus is all performed via the common transfer chamber 28, thereby improving the processing efficiency. Then, control of a vacuum gauge, a gas flow meter (MFC), various sensors, various actuators, various motors, and the like in each processing apparatus, and a supply / exhaust system of the common transfer chamber 28 and the cassette chambers 30A and 30B, movable parts, and spaces. Since it is necessary to centrally control the gate valves and the like for partitioning the master, a single master-side control unit 3 including a CPU module
8 are provided. The I / O in each processing apparatus, the common transfer chamber, the cassette chamber, and the like are modularized to be a plurality of slave-side control units 40A and 40B. 40
C or the like is formed. Each of these slave side control units 40
It is connected to the master-side controller 38 via a serial line 42 and is centrally managed by the master-side controller 38. In the figure, as an example, a master-side controller (CPU module) 38 and first and second slave-side controllers (chamber I / O control modules) 38A and 38B are shown. Although the number of these slave-side control units depends on the scale of the entire apparatus, for example, up to about 31 modules can be connected. The size of the entire device is less than several meters in length, width, and height, and the transmission line 42 connecting the modules is not so long. Done.

As shown in FIG. 2, each module 38, 4
Known bus interfaces 46M and 46S including high-speed communication interface units 44M and 44S for performing communication between modules and port interfaces are provided in 0A, 40B and 40C. The bus interface 46M on the master side is connected to the CPU by the CPU bus 48, and each bus interface 46S or the port interface on the slave side controls a motor control I / O, a vacuum gauge, a gas flow meter, or the like by AD (analog digital) or DA (DA). It is connected to an I / O to be converted (digital / analog), a memory, a digital I / O such as a sensor or an actuator, or the like. Each slave-side control unit is sequentially line-connected to form a network, that is, multi-drop, and finally the bus terminator 50 is connected.

The configuration of the high-speed communication interface units 44M and 44S for performing characteristic communication between modules will be described with reference to FIG. All the high-speed communication interface units 44M and 44S have the same structure.
It is integrated on one chip. The high-speed communication interface section is roughly divided into a master / slave block (MS block) and a communication block.

The master / slave block (MS block) is an interface between the master CPU and the master CPU (in master mode).
And I / F with slave I / O bus (in slave mode)
This block mainly generates an I / F (interface) with the outside of the chip, a communication request signal, transmission message / data, and interprets and executes a received message.
Each constituent block of the S block will be described. In the figure, [M] indicates an element that operates only in the master mode.
[S] indicates a device that operates only in the slave mode,
[R] indicates the one that operates only in the repeater mode.

The master sequencer 52 performs address reception and data transmission / reception.
This block has a function of controlling all operations of the MS block and returning a response to an access from the U.
The slave sequencer 54 is a block having a function of controlling all operations of the MS block and returning a response to a request from the communication block in the slave mode.

The address decoder / data selector 56 connected to the master sequencer 52 and the slave sequencer 54 determines whether the request from the master sequencer 52 or the slave sequencer 54 is a register / counter 58, a communication, or a slave I / O bus access. Is a block for issuing an access request to each functional block.

The address decoder / data selector 5
6 are connected to a control / error / status register, a timer, a DM, and the like.
A (Direct Memory Access) transfer circuit counter
This is a block composed of a counter. There is also a DI / DO port that operates in the slave port mode. An access request to a communication block has the following four requesters, and the requester block operates only in the master mode.

The slave bus requester 60 is a block for issuing a communication access request to a slave directly in response to a request from the CPU. There are slave registers or slave I / O buses and slave port access. The interrupt polling requester 62 is a block that issues a communication access request at a set interval in order to confirm the interrupt occurrence status on the slave side. This request is made automatically irrespective of the access from the CPU.

DMA Ch. 0 requester 64 is DM
This is a block for realizing the A transfer. The presence or absence of a DMA request from a slave is automatically confirmed at a set interval, and necessary data transfer is performed. It also has a DMA I / F function with the outside of the chip. DMA Ch. 1 requester 66 is the DMA Ch. It is a block having the same function as 0.

Each of the requesters 60, 62, 64, 66
A communication bus arbiter 68 connected to the arbiter is a block for arbitrating a communication access request from each requester. By the arbitration function of the block 68, two or more accesses to the communication block do not occur at the same time.

The message / data formatter 70 connected to the slave sequencer 54 and the communication bus arbiter 68 converts the address and data to be transmitted into a body according to a prescribed communication format, It has a function to decompose the body part into addresses and data. The communication message includes a header section, a body section, a CRC section, and a recovery section.
The body part therein is composed of an address and data configuration, but the configuration must be adjusted because the body length is changed by a communication command.

An access request to the slave I / O bus has the following two requesters, ie, repliers. These reply blocks operate only in the slave mode. One I / O bus reply 72 is
This block issues a bus access request to the I / O bus arbiter 76 in response to a slave I / O bus access request from the high-speed communication interface chip on the master side. The other DMA reply 74 is a block for realizing DMA transfer with the master. DMA with outside chip
And a function for responding to the confirmation of the presence or absence of a DMA request from the master side and performing necessary DMA data transfer.

The I / O bus arbiter 76 connected to the I / O bus replier 72, the DMA replier 74 and the slave bus I / F 78 described below waits for the request of each of the replier 72, 74 for a specified time or more. Sometimes has the function of generating a bus hold timeout error. The access request to the slave bus I / F 78 includes the two replies and the secondary bus master (2nd CPU) outside the chip. The slave bus also has a function of arbitrating the slave bus in response to these requests.

The slave bus I / F 78 sends an address, sends and receives data, and sends and receives digital data.
In addition to the basic function of the I / F for accessing the slave I / O bus, a funneling function that matches the data width of the I / O bus and the replyer, a bus timeout when an acknowledgment does not return from the I / O bus for more than a specified time Has the function of generating an error.

In contrast to the above-described MS block, the communication block is a block that controls network communication of the high-speed communication interface unit, and exchanges messages and data in parallel with the MS block. Input / output signals with the outside of the chip are: 4 transmission lines, 4 reception lines,
One transmission enable signal. The communication block includes a flow controller 80, a transmitter 82, a line state detector 84, a receiver 86, a repeater 88, a break /
It is configured by an emergency generation section 90. less than,
The function of each component block of the communication block will be described.

First, the flow controller 80 is a block for controlling the flow of communication transmission / reception.
Here, a process of generating a header part for the communication message data and passing it to the transmission block (transmitter) together with the body part from the MS block is performed. In addition, it interprets the body part of the communication message data from the receiving block (receiver) and judges the message addressed to itself, the retransmission message, the retransmission request, the error message, etc.
Do the processing.

The transmitter 82 connected to the flow controller 80 and the break / emergency generation circuit 90 transmits a transmission request and transmission message data from the flow controller 80 to GCC4 / GCC2 (gray
The transmission is performed by changing the transmission line according to the settings of the coded coding 4/2) and the MMC (Modified Manchester coding) mode. These GCC / MMC codes are designed to be used for communication inside the device, and the GCC code is used, for example, to extend the I / O bus in the device at a relatively short distance. An object of the present invention is to perform high-speed data transfer by using a transmission line to minimize the circuit load of each node. Further, the MMC code aims to provide an efficient and simple bit-oriented synchronous communication means based on the Manchester code under use conditions free from collisions such as opposition and multidrop. These coding schemes are implemented in this transmitter.

The line state detector 84 is connected to the flow controller 80 and is a block that constantly monitors line states such as break, emergency, no line bit change, and line / space state. The receiver 86 is a block that is connected to the flow controller 80 and receives message / data of the transmission line together with the line state detection block 84.
Although normal reception confirmation at the bit level is performed, whether the received message is significant is determined by the flow controller 8.
Leave it to 0. Further, the encoding method described in the transmitter 82 is also implemented in the receiver 86.

The repeater 88 is connected to the flow controller 80, the line state detector 84, and the receiver 86. The repeater 88 is a block that operates in the repeater mode in the network form of the high-speed communication interface unit. Generate a communication direction control signal. In this mode, the chip also functions as a monitor of the transmission line, outputting message data on the line and a signal for monitoring the line state. In the repeater mode, the flow controller 80 and the transmitter 82 do not operate.

The break / emergency generating section 90
The break / emergency signal is input, and a break / emergency signal is output to the transmitter 82.
Requests for transmission of these abnormal signals are made in this block separately from the regular route to prevent accidents.

According to one embodiment of the present invention, in the communication system of the semiconductor manufacturing apparatus as shown in FIG. 2, the master-side control unit 38 is connected to the slave-side control unit via the serial line 42, that is, The board information such as the I / O type and the number of I / O points of the chamber I / O control module is automatically collected, and the connected module is automatically recognized.

Therefore, for example, a slave-side control unit,
For example, the slave-side control unit 40A for the chamber I / O control module # 1, as shown in FIG.
The board information port 100 has an address assigned to the / O space.
Board information regarding the chamber I / O control module # 1 is stored in an accessible form.

For example, the chamber I / O shown in FIG.
The board information relating to the control module # 1 includes: a business ID for identifying a process in which the board is used;
(Eg, information identifying the manufacturer of the processing chamber) Board ID (eg, motor control I / O, AD / DA, etc.) to distinguish boards within the same business ID
And information indicating that the board has a DI / DO). ・ Revision number of the board. ・ Information indicating the number of I / O points mounted on the board.

On the other hand, the master-side control unit 38 includes high-speed communication interfaces 44M and 44S and a serial line 4M.
2 to the chamber I / O from the slave side control unit 40A.
In order to read board information regarding the control module # 1, a driver program 110 executed by the CPU of the master-side control unit 38 is provided.

The driver program accesses the port information port 100 of the chamber I / O control module # 1 allocated to the I / O space defined by the high-speed communication interface, and executes the above-mentioned type of board for this module. Get information.

A champ I / O control module, that is, a port 100 for holding information on an I / O type and the number of I / O points on an I / O board is provided by an FPGA.
This is realized by forming a memory inside the O board or providing a dip switch on the I / O board. Then, the addresses of these memories or dip switches are assigned to predetermined offset addresses in the I / O board. When the I / O board is connected to the serial line 42 using the communication interface, the head address is allocated in the I / O space in the communication interface.
An address obtained by adding a predetermined offset address to the head address is assigned. Therefore, for example, when writing is performed from the master-side control unit 38 to the first address of the board information port on the I / O board, the I / O board information is obtained from the second address.

FIG. 4 shows a master controller 3 of an apparatus controller of a semiconductor manufacturing apparatus according to another embodiment of the present invention.
8 is a flowchart of a driver program automatically generated by the device configuration information, which is executed by the CPU 8;

Step 1: The master-side control unit 38 first sets the address of the board information port of the I / O board to be accessed. This address is determined, for example, from the start address of the address space of the I / O board to be accessed first and the fixed offset address of the board information port.

Step 2: The master-side control unit 38 accesses the set address via the communication interface unit 44M.

Step 3: In order to determine whether or not there is an I / O board corresponding to the address accessed by the master-side control unit 38, it is determined whether or not a bus timeout has occurred for the access from the master-side control unit 38. Checked. If there is an I / O board, an ACK signal is detected, and the process proceeds to step 4. If there is no I / O board, a timeout occurs, and the process proceeds to step 6.

Step 4: The master-side control unit 38
The board information including the above elements is read from the board information port 100 of the O board.

Step 5: The master-side control unit 38 creates an I / O map, that is, device configuration information, using the read board information. When an already created I / O map exists, the newly read board information is added to the I / O map. Thus, the device parameters are automatically updated.

Step 6: The master-side control section 38 determines whether or not all the board information ports that can exist in the address space of the communication interface have been accessed.
If there is a board information port address that has not been accessed yet, the process proceeds to step 7.

Step 7: Next I / O to be accessed
The address of the board information port on the O board is calculated and set in the address space of the communication interface, and the process returns to step 2.

If it is determined in step 6 that all ports have been accessed, the process is terminated.

In this way, the master-side control unit 38
Device configuration information is automatically created using polling of communication interface and detection of timeout.

The present invention is not limited to the above embodiments, but can be variously modified and applied within the scope of the claims.

[0054]

As described above, according to the present invention, the control I
The board information such as the I / O type and the number of I / O points of the board is stored in the / O board, and the main control unit collects each board information from each control I / O board. It is possible to automatically recognize the configuration of the control I / O board. This makes it possible to immediately determine the difference between the device parameter representing the device configuration and the actual board connection state. That is, a board connection error or a device parameter setting error can be easily detected.

Further, since it becomes possible to automatically set the device parameters based on the automatically recognized device configuration, the number of device parameters relating to the I / O board is reduced. Further, automatic recognition of an I / O board can be performed using an I / O access procedure conforming to an existing communication interface, so that an I / O check is realized without preparing special software. You.

[Brief description of the drawings]

FIG. 1 is an external view of a semiconductor manufacturing apparatus according to one embodiment of the present invention.

FIG. 2 is a block diagram of a communication system applied to the semiconductor manufacturing apparatus according to one embodiment of the present invention.

FIG. 3 is a block diagram of a high-speed communication interface used in a communication system of the semiconductor manufacturing apparatus according to one embodiment of the present invention.

FIG. 4 is a flowchart of a driver program for automatically creating device configuration information executed in a semiconductor manufacturing device according to another embodiment of the present invention.

[Explanation of symbols]

 26A, 26B, 26C Processing device 28 Common transfer room 30A, 30B Cassette room 32 Cassette 34 Input device 36 Display 38 Master side control unit 40A, 40B, 40C Slave side control unit 42 Serial line (transmission line) 44M, 44S High speed communication Interface unit 46M, 46S bus interface 48 CPU bus 50 bus terminator 100 board information port 110 driver

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F045 BB08 BB10 DQ14 EB08 EE04 EG02 EN04 GB06 GB15 5H220 AA04 BB07 CC03 CC09 CX05 CX09 EE09 JJ02 JJ17 JJ19 JJ26

Claims (2)

[Claims] At least one machine for executing a semiconductor manufacturing process, a main control unit for controlling the machine, at least one input / output board for inputting and outputting data to and from the machine, and A semiconductor controller including a communication interface for communicating data between a control unit and the input / output board, and a device controller in which an address of the input / output space of the communication interface is assigned to a port on the input / output board In the manufacturing apparatus, information on the board specifications is set to the port of the input / output board, and the main control unit accesses the address of the input / output space corresponding to the port of the input / output board, and The information on the specifications of the board is read out, and the information on the specifications of the board read out in the main control unit is read out. Automatic recognition method of the input and output boards in a semiconductor manufacturing apparatus characterized by creating a device configuration information Luo said device controller. 2. A machine for executing a semiconductor manufacturing process, at least one machine, a main control unit for controlling the machine, at least one input / output board for inputting and outputting data to and from the machine, and A semiconductor controller including a communication interface for communicating data between a control unit and the input / output board, and a device controller in which an address of the input / output space of the communication interface is assigned to a port on the input / output board A manufacturing apparatus, wherein the input / output board has a port in which information on board specifications is set, and the main control unit accesses an address of the input / output space corresponding to the port of the input / output board. Means for reading information on the specifications of the board from the input / output board; and Means for creating device configuration information of a device controller.