JP2002015580A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce current consumption in a sense amplifier or the like, even when a clock signal is not at L level, when a clock signal is stopped to reduce current consumption, in a synchronous semiconductor integrated circuit. SOLUTION: In a mode, in which power consumption, is reduced by stopping a clock signal, a semiconductor integrated circuit, having timer detecting circuits 2, 3 outputting a power-down signal PD1 by detecting that a clock signal is fixed, and control circuits 7, 8 for controlling an internal clock signal CLK5 to a fixed state of L level by the power down signal PD1, and to conduct power- down of an internal circuit 9 reduces current consumption, independently of the level of the clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a reduction in power consumption of a synchronous semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit using a control circuit for stopping an external control clock signal.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits have been operating at higher speeds with higher integration density. In particular, the increase in the arithmetic processing speed of the MPU and the increase in the data input / output of the storage device that exchanges data with the MPU are remarkable. In a general synchronous semiconductor memory device, a clock signal is input from the outside,
Input signals such as control signals, address signals, and data signals are captured inside the chip in synchronization with the rising edge of the clock signal, and the operation from outside is defined as one cycle until the next rising edge of the clock signal. Is done. That is, as long as the clock signal is input while switching between the H level and the L level in a certain cycle, some operation is repeated and the internal circuit consumes current.

In such a synchronous semiconductor memory device, for example, a mode called a stop clock for reducing power consumption is defined. This is to temporarily stop the switching operation of the clock signal between the H level and the L level for the externally input clock signal and keep the signal level fixed at the L level, thereby controlling the internal operation of the circuit. Is also provided to reduce the current consumption of the semiconductor memory device.

In practice, an external clock signal CLK1 is input to a clock input circuit 50 as shown in FIG.
The internal clock signal CLK2 is output from the clock input circuit 50 to the internal circuit 51 that operates in synchronization with the clock signal in the semiconductor memory device. Further, the timer detection circuit 52 is connected to the clock input circuit 50, and measures a period during which the internal clock signal CLK2 output from the clock input circuit 50 is fixed at a constant potential.

Here, when it is detected that the signal is fixed at the L level for a predetermined time longer than a normal cycle time, the power down signal PD is activated.
This power-down signal PD deactivates the individual circuit 53 that can be stopped. However, the external clock signal CLK
When 1 starts moving again, it is necessary to immediately resume operation of the apparatus and resume normal operation. For this reason, it takes time to recover to a normal operation state, and a circuit that causes a problem in returning to operation cannot be an individual circuit, and power down of such a circuit cannot be achieved.

Here, in the individual circuit, the internal clock signal is fixed, data transfer between registers is not performed internally, and the signal level of the logic circuit does not change. In addition to saving current consumption, the circuit that consumes DC current is inactivated by the power-down signal. Further, in the case of a circuit using general CMOS logic, the current consumption of the static digital circuit portion is extremely small. Therefore, if the logic is fixed, almost no current is consumed.

Here, the H level or L level of external clock signal CLK1 and the internal operation of the semiconductor memory device will be described. As an example, a write operation such as writing captured input data to a specified address as an operation related to a captured input signal or a read operation such as sensing data from a specified address and storing the data in an output register is performed by an external device. Clock signal C
A case where the operation is performed in one cycle period defined by LK1 will be described with reference to a timing chart of FIG.

FIG. 8 shows a case of a late write, so that the input of write data is fetched one cycle later than the address / control input, and the actual write operation in the semiconductor memory device is performed externally. Although one cycle behind the specified cycle, there is no difference in terms of operation within the cycle. In the write cycle, the cycle starts from the rise of the external clock signal CLK1, and once falls,
A cycle until it starts up again corresponds to one cycle.

In practice, the next external clock signal CLK1
The write operation and the write recovery initialization / precharge operation are sequentially performed during one cycle period of. Next, in a read cycle corresponding to one cycle of the external clock signal CLK1, a read operation and a read recovery initialization / precharge operation are sequentially performed. In the read operation, one cycle starts from the cycle designated to be read externally.
Data within the semiconductor memory device is output to the outside with a cycle delay.

Here, in order to perform the operation at a high speed, it is necessary to select a word line or a bit line for the fetched address at a high speed. Therefore, in a circuit for decoding an address signal, a circuit threshold of a gate circuit such as an inverter is inclined to speed up a signal transmission delay for selection, increase a speed up to cell selection, and transfer data to a cell. Writing or starting the sensing of cell data as fast as possible is performed.

Here, to incline the circuit threshold means, for example,
As shown in FIG. 9, in a three-stage serially connected inverter circuit, this refers to speeding up the rising operation from the L level to the H level and smoothing the falling operation from the H level to the L level. The ratio of the P-channel transistor size to the N-channel transistor size of each inverter is larger than the normal ratio.
5 has a large N-channel transistor size, and the third inverter 56 has an unbalanced size ratio so that the size of the P-channel transistor is large.

To increase the size of the transistor,
Generally, it can be set by increasing the channel width.
In this case, conversely, the non-selected speed is disadvantageous because the circuit threshold of the gate circuit is inclined so as to be disadvantageous.
Signaling to return the selected decode path to its original unselected logic state is slow.

Therefore, as shown in FIG. 10, the address is reset to a non-selected state at the time of completion of writing or sensing triggered by the falling edge of the external clock signal CLK1, which is an intermediate point in one cycle. Is performed. This is because when operations such as writing and sensing performed in the selected state of the cell are completed and address information is no longer required to be held, it takes a long time before the new address is taken in at the start of the next cycle. That is, decoding of selection is performed, and preparation is made for a new address fetch at the next rising of the external clock signal CLK1 and the start of the next cycle.

In the write operation, the operation of driving the write data line and the drive of the write buffer according to the data, the activation of the sense amplifier in the read operation, and the transfer of data to the output are performed in the same manner as the address reset. The falling edge of the signal CLK1 is used as a trigger to deactivate when the timing at which deactivation is possible has elapsed, and operations such as initialization and precharge are performed in preparation for the operation in the next cycle. As a result, the operation in the next cycle is sped up to increase the speed performance. In this case, in the first half of the cycle, that is, when the external clock signal CLK1 is at the H level, the inside is in the operating state, and in the second half of the cycle, that is, when the external clock signal CLK1 is at the L level, the inside is in the inactive state. become.

Next, a case of a specification called a double data rate (DDR) will be described with reference to FIG. In the case of a normal synchronous operation, the input signal is taken in at the timing of the rising edge of the external clock signal CLK1. On the other hand, the DDR has a specification that data input or output is performed using not only the rising edge but also the falling edge timing of the external clock signal CLK1 for the input and output of the data signal.

By fetching data with a shift of half a cycle, a double data transfer rate can be realized.
In the semiconductor memory device, if the address space is divided into two and the parallel processing is performed on the doubled data, there is no need to change the conventional internal operation speed. This specification is used especially when high speed is required.
Double data is exchanged with LK1.

Here, as shown in FIG. 12, the semiconductor memory device itself is synchronized with the data output timing,
A function of outputting a clock signal called an echo clock signal ECLK from OUT3 and notifying the MPU receiving data of the timing of setting the strobe of data may be provided (ISSCC2000 digest P2).
67, An 833MHz 1.5W 18Mb CM
OS SRAM with 1.67Gb / S / pin
reference).

In FIG. 12, a plurality of sense amplifiers 61 and 62 are connected to a memory cell 60,
Multiplexers 64 and 65 are connected to 1 and 62, respectively. In addition, a multiplexer 66 having one input terminal connected to the power supply potential and the other input terminal connected to the ground potential is provided. Outputs from the multiplexers 64, 65, 66 are connected to input / output terminals 70, 71, 72 via buffers 67, 68, 69, respectively, and signals are output from the semiconductor memory device to the outside. Here, the echo clock signal ECLK is output to the outside from the input / output terminal 72 via the buffer 66 from the multiplexer 66, for example. The multiplexer 66 outputs a ground level signal from the input / output terminal 72 when the clock signal CK is at the H level, and outputs a power supply level signal from the input / output terminal 72 when the clock signal CK is at the L level.

As shown in FIG. 10, the timing of the echo clock signal ECLK is H at the timing when the semiconductor memory device outputs data as shown in FIG.
It was common to transition between levels and L levels.
However, as the frequency increases, it may be more convenient to make the transition timing of the echo clock signal ECLK not at the same time as the transition of the output data but at an intermediate timing of the data transition as shown in FIG. Was.

In this case, the timing at which the data output switches and the timing at which the echo clock ECLK switches are shifted from each other by a quarter of the cycle of the external clock signal CLK1 in the case shown in FIG. Become. Now, the timing of the 1/4 cycle length directly affects the timing margin of MPU data capture, so that accurate timing control is required.

Here, from the external clock signal CLK1,
To generate a clock signal with a length of 1/4 period,
The frequency of the clock is doubled inside the semiconductor memory device, and the PLL
It must be controlled by a synchronous circuit such as
This can be a heavy burden on the semiconductor memory device. So, when you need such an echo clock,
It has been proposed to provide an external clock at twice the normal frequency as shown in FIG.

In this case, since external clock signal CLK3 is applied at twice the period, it is halved in the semiconductor memory device.
, An internal operation clock having a normal cycle can be obtained. On the other hand, the timing of the rising edge and the falling edge of the external clock signal CLK3 is used to control the echo clock. Thus, it is possible to easily and accurately generate a timing of 1/4 of the internal cycle without using a synchronous circuit.

[0023]

The following problems occur in the above-mentioned conventional semiconductor integrated circuit.

When an analog circuit such as a sense amplifier is used in a semiconductor integrated circuit, a current is continuously supplied in a DC manner, and the current is supplied as long as the circuit is activated, even if the potential level of the clock signal is fixed. Continue to consume. Therefore, in the semiconductor integrated circuit having the internal operation as described above, even if the clock signal is stopped and fixed, the current consumption increases in the first half of the cycle when the circuits such as the sense amplifier are activated as compared with the latter half of the cycle. A problem that the In the case of using the stop clock mode, there is a constraint that the clock signal is stopped in an L level state, that is, in a state where the internal circuit is inactivated.

Also, consider the case where the stop clock mode is set for a semiconductor integrated circuit in which the frequency of the external clock signal is given at twice the frequency of the internal operation. For the divided internal clock signal, as described above, it is assumed that the internal circuit is activated in the first half of the cycle of the clock signal and inactivated in the second half of the cycle of the clock signal.

In this case, as shown in FIG. 11, the external clock signal CLK3 can be at either the H level or the L level in both the first half and the second half of the internal cycle. Therefore, as shown in FIG. In the state where the external clock signal CLK1 is at the H level / L level, it is not possible to distinguish between activation and deactivation of the internal circuit. Even if there is a restriction that the clock signal is stopped at the L level, the internal circuit may not operate. It is not always in a deactivated state, and the effect of reducing current consumption is hindered.

FIG. 1 of Japanese Patent Application Laid-Open No. H10-303725 shows that the clock input terminal of the latch circuit is connected to the clock input terminal of the latch circuit so that the latch does not transmit the glitch when the input buffer shifts from the power save state to the normal state. A technique is described in which an OR circuit and a delay circuit are provided between a save signal and a save signal.

An object of the present invention is to solve the above-mentioned problems of the prior art.

In particular, an object of the present invention is to reduce the current consumption when the external clock signal is stopped to reduce the current consumption, regardless of whether the potential of the clock signal is at the H level or the L level. An object of the present invention is to provide a semiconductor integrated circuit that can return to a normal operation without a special sequence when a clock is restarted.

[0030]

In order to achieve the above-mentioned object, the present invention is directed to a first embodiment in which the input level of an externally input first clock signal is fixed to one of a first potential level and a second potential level. Is measured, and when it is detected that the input state of the first clock signal is fixed at the first potential level or the second potential level for a predetermined time or more, the state becomes the activation level, and in other cases, it is not activated. A timer circuit for outputting a first activation signal at an activation level; and when the activation signal at the first activation signal is inputted, the first clock signal is inputted as a second potential level. And a control circuit for outputting a second clock signal at the potential level of the first clock signal when the first activation signal at the inactivation level is inputted. When the external clock is stopped to reduce the current consumption, the current consumption can be reduced even if the potential of the clock signal is H level or L level, and the potential change of the clock signal is restarted. It is possible to provide a semiconductor integrated circuit that can sometimes return to normal operation without a special sequence.

According to another aspect of the present invention, the time during which the input level of the first clock signal input from the outside is fixed to one of the first potential level and the second potential level is determined. When the measurement is performed and it is detected that the input state of the first clock signal is fixed to the first potential level or the second potential level for a predetermined period or more, the first clock signal becomes the activation level, and otherwise becomes the inactivation level. A timer circuit for outputting the first activation signal, and a potential level when the first clock signal is inputted as the second potential level when the first activation signal of the activation level is inputted. A control circuit for outputting a second clock signal at the potential level of the first clock signal when the first activation signal at the inactivation level is input;
When the first activation signal at the activation level is input, the activation level becomes an activation level after a predetermined delay time, and when the first activation signal at the inactivation level is input,
A delay circuit for outputting a second activation signal which becomes inactive at the same time as the input of the first activation signal. According to this aspect, when the external clock signal is stopped to reduce the current consumption, the potential of the clock signal becomes H level.
It is possible to provide a semiconductor integrated circuit that can reduce current consumption regardless of the level or the L level and can return to normal operation without a special sequence when the potential change of the clock signal is restarted.

Further, according to another aspect of the present invention, a frequency divider for dividing a first clock signal input from the outside and outputting a second clock signal; A time period during which the potential is fixed to one of the first potential level and the second potential level is measured, and the potential level of the second clock signal is set to the first potential level for a predetermined period or more.
A timer circuit that outputs a first activation signal that is an activation level when it is detected that the potential is fixed to the potential level or the second potential level, and is an inactivation level in other cases; A third clock signal having a potential level equal to the second clock signal when the activation signal is at the activation level; and a second potential level when the first signal is at the inactive level. And a control circuit for outputting the same. According to this aspect, when the current consumption is reduced by stopping the external clock signal, the current consumption can be reduced even if the potential of the clock signal is at the H level or the L level, and the potential change of the clock signal is restarted. It is possible to provide a semiconductor integrated circuit that can sometimes return to normal operation without a special sequence.

Further, according to another aspect of the present invention, a frequency divider for dividing the externally input first clock signal and outputting a second clock signal; The time of the period fixed to one of the one potential level and the second potential level is measured, and the potential level of the second clock signal is fixed at the first potential level or the second potential level for a predetermined period or more. A timer circuit that outputs a first activation signal that is an activation level when it is detected that the activation signal has been activated, and is an inactivation level in other cases; and a timer circuit that outputs the first activation signal when the first activation signal is an activation level. A control circuit for outputting a third clock signal having a potential level equal to the second clock signal when the first signal is at an inactive level; Activity of 1 From it the activation level of the signal is inputted, it becomes the active level after a predetermined delay time, if the inactive level of said first activation signal is input,
A delay circuit that outputs a second activation signal that is at the inactivation level simultaneously with the input of the first activation signal. According to this aspect, when the current consumption is reduced by stopping the external clock signal, the current consumption can be reduced even if the potential of the clock signal is at the H level or the L level, and the potential change of the clock signal is restarted. It is possible to provide a semiconductor integrated circuit that can sometimes return to normal operation without a special sequence.

[0034]

Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. (First Embodiment) A semiconductor integrated circuit according to a first embodiment of the present invention will be described with reference to FIG.

As shown in FIG. 1, the external clock signal C
LK3 is input to the clock input circuit 1 and output as the first internal clock signal CLK4. The first timer detection circuit 2 is connected to the clock input circuit 1, and the first internal clock signal CLK4, which is the output of the clock input circuit 1, is low.
The period during which the level is fixed at a constant potential is measured.

Here, when it is detected that the signal is fixed at the L level for a predetermined time longer than a normal cycle time, a signal for instructing power down is output. Further, the second timer detection circuit 3 is connected to the clock input circuit 1, and measures a period during which the first internal clock signal CLK4, which is the output of the clock input circuit 1, is fixed at the H level constant potential.

Here, if it is detected that the signal is fixed at the H level for a predetermined time longer than a normal cycle time, a signal for instructing power down is output. A NOR circuit 4 to which a signal for instructing power down, which is an output of the first timer detection circuit 2, and a first internal clock signal CLK4 are input is provided. Further, the first internal clock signal CLK4 to which the signal for instructing power down and the first internal clock signal CLK4, which are the outputs of the second timer detection circuit 3, are input.
An AND circuit 5 is provided. Outputs of the NOR circuit 4 and the first AND circuit 5 are input to an OR circuit 6. The first power-down signal PD1 output from the OR circuit 6 is input to the inverter 7, and its input potential level is inverted and input to one input terminal of the second AND circuit 8.
Further, the first internal clock signal CLK4 is input to the other input terminal of the second AND circuit 8. The output of the second AND circuit 8 is input as a second internal clock signal CLK5 to an internal circuit 9 that operates in synchronization with the clock signal.

The second internal clock signal CLK5 is at the H level only when the first internal clock signal CLK4 is at the H level and the first power down signal PD1 is at the L level, and is at the L level otherwise. . The first power-down signal PD1 is input to the delay circuit 10 including a plurality of even-numbered inverter elements. The delay circuit 10 delays and outputs the input first power-down signal PD1 for a predetermined time. The delayed first power down signal PD1 and the undelayed first power down signal PD1
Is input to the third AND circuit 11, and only when both of these two input signals are at the H level, the second
The power down signal PD2 is output, and in other cases, the L level second power down signal PD2 is output. The second power-down signal PD2 deactivates the plurality of individual circuits 12 that can be stopped.

Here, the first timer detection circuit 2 includes, for example, an even-numbered inverter having a P-channel transistor and an N-channel transistor connected in series between the power supply potential and the ground potential shown in FIG. It is connected to and configured. In FIG. 2, an inverter having a resistance element between transistors connected in series is illustrated using a transistor symbol, and the other inverters are illustrated using an inverter symbol.

In the first timer detection circuit 2, the first internal clock signal CLK4 is input to the first inverter 30. The output of the first inverter 30 is input to the second inverter 31. Similarly, the outputs of the preceding inverters are sequentially input to the third to eighth inverters 32, 33, 34, 35, 36, and 37. Here, the first to fifth resistance elements 38, 39, 40, 41, 42 are connected between the P-channel transistor and the N-channel transistor of each of the third to seventh inverters.
The first to third N-channel transistors 43 and 44 each having a source connected to the ground potential and a gate connected to the output of the second inverter 31 at the inputs of the fourth, sixth and eighth inverters 33, 35 and 37. , 45 are connected one by one in sequence. The sources of the fifth and seventh inverters 34 and 36 are connected to the power supply potential, and the drains of the first and second P-channel transistors 46 and 47 whose gates are connected to the output of the first inverter 30 are sequentially connected to one each. Connected. The output of the eighth inverter 37 and the internal clock signal CLK4 are both input to the NOR circuit 4, and the NOR operation is performed to perform the first OR operation.
A signal serving as the power down signal PD1 is output to the OR circuit 6.

That is, using the inverters connected in multiple stages, the first internal clock signal CLK4 is detected to be at the L level for a predetermined time, and is input to one input terminal of the NOR circuit 4, and after the first time, The internal clock signal CLK4 is directly input to the other end of the NOR circuit 4, and when both inputs are at L level, the first power-down signal PD1 at H level
Is output. Here, the first to fifth resistance elements 38, 3
Reference numerals 9, 40, 41, and 42 are for tilting the circuit threshold of each inverter. The resistance value of each resistance element may be, for example, the same resistance value.

In the third inverter 32, the first resistance element 38 is provided on the P-channel transistor side with respect to the output terminal of the inverter. Therefore, even if an L-level signal is input to the input terminal of the inverter and the P-channel transistor is turned on, the first resistance element 38
Makes it difficult to output an H-level signal from the output terminal. Conversely, when an H-level signal is input to the input terminal of the inverter and the N-channel transistor is turned on, an L-level signal is likely to be output from the output terminal. Thus, the third inverter 32 has its circuit threshold lowered.

On the other hand, in the fourth inverter 33,
The second resistance element 39 is provided on the N-channel transistor side with respect to the output terminal of the inverter. Therefore, even if an H-level signal is input to the input terminal of the inverter and the N-channel transistor is turned on, the second resistance element 3
9 makes it difficult to output an L-level signal from the output terminal. Conversely, when the L-level signal is input to the input terminal of the inverter and the P-channel transistor is turned on, the H-level signal is likely to be output from the output terminal. Thus, in the fourth inverter 33, the transmission threshold value is raised.

From the next stage onward, the circuit thresholds are alternately inclined to the seventh inverter and connected in series to obtain a signal delay with a small number of logic stages. Here, when the inverter whose circuit threshold value is lowered so that the delay when the L level is input is larger than the delay when the H level is input is used more frequently, and the L level input is performed, A delay operation is performed.

Here, the individual circuit 12 is a circuit included in the internal circuit 9 and is, for example, an input first-stage circuit as shown in FIG. The input first stage circuit has a source connected to the power supply potential, a gate to which a power down signal PD is input, a first P-channel transistor 13, a drain connected to the first P-channel transistor 13, and a source connected to the gate. The second P-channel transistor 14 to which the input signal IN is input, and the reference potential VREF to the gate.
And the third P-channel transistor 15 to which is input. In addition, the drain of the first N-channel transistor 16 is connected to the drain of the second P-channel transistor 14. This first N-channel transistor 1
6 has a source connected to the ground potential, and a gate connected to the drain of the third P-channel transistor 14. The drain and source of the second N-channel transistor 17 are connected to the gate of the first N-channel transistor 16, and the source is connected to the ground potential. Further, the input terminal of the inverter 18 is connected to the drain of the second P-channel transistor 14 and the drain of the first N-channel transistor 16, and outputs the output signal OUT to another circuit in the internal circuit.

With this circuit, the second power down signal P
When D2 is at the L level, the power supply potential is not input to the individual circuit, and the current consumption of the individual circuit is reduced. Such an individual circuit is applied to a circuit in which a direct current flows, such as a programmable impedance and a sense amplifier, in addition to the illustrated input first-stage circuit.

As described above, two signals are provided for instructing power down, that is, when the first internal clock signal CLK4 is fixed at the L level and when the first internal clock signal CLK4 is fixed at the H level. Make a difference. Then, the potential level of the internal clock signal is controlled by using one of the systems that is activated earlier, that is, the signal that instructs power-down, and when one of the signals that instructs power-down is activated. , The second internal clock signal C
LK5 is set to L level. By doing so, as shown in FIG. 4, even if the clock input from the outside is fixed at the H level (broken line A in the figure), the clock is internally changed from the H level to the L level (in the figure, Assuming that the transition has been made to the solid line B), the circuit operation transitions to the inactive state in the latter half of the cycle.

The second power down signal PD1 causes the second
If the internal clock signal CLK5 is fixed, data transfer between registers is not performed internally, and the signal level of the logic circuit does not change, so that current consumption caused by logic transition is eliminated and AC current consumption is saved. . Further, in the case of a circuit using general CMOS logic, the current consumption of the static digital circuit portion is extremely small. Therefore, if the logic is fixed, almost no current is consumed.

Here, the case where the level of the external clock signal CLK3 is fixed beyond a certain period is detected, a power down signal is generated, and the power down of the individual circuit 12 is activated at the other end. This is performed using the second power-down signal PD2. Now, the difference between the timings at which these two power-down signals are activated is set to be equal to or more than の of the cycle time Tcy of the normal operation using the delay circuit 10. With this setting, the second internal clock signal CLK
2 is powered down, and the internal circuit 9 transitions to the inactive state in the latter half of the cycle, and is maintained in the inactive state for more than 1/2 cycle, that is, for the same period or more as the normal second half cycle, A transition is made to the power down state of the individual circuit 12 in the stop clock mode.

As described above, although the external clock signal CK3 is fixed at the H level in the internal operation,
When the external clock signal CK3 transitions to the L level and preparations for the next cycle such as precharge and initialization in the latter half of the cycle are completed, it can be regarded as the same as executing power down in the stop clock mode. Further, even when the potential level of the external clock signal CKL3 starts again, since the external clock signal transitions from the H level to the L level, the internal circuit 9 is continued in the latter half cycle, and the operation contradicts. There is no.

H in the first half of the cycle of the clock signal
At the level, the sense operation and the write operation of the sense amplifier in the semiconductor integrated circuit are performed, and it takes time. Therefore, the rising operation in the first half cycle of the second internal clock signal CLK5 is set fast, and a sufficient time is secured. are doing. In the latter half cycle of the second internal clock signal CLK5, a precharge operation and a reset operation are performed.
Since these operations can be performed in a relatively short time, the falling operation of the internal clock signal is slower than the rising operation.

Here, since any power-down signal needs to be deactivated at the same time as the restart of the clock,
The delay to the later activation signal is such that a delay is added only when the logic is activated. By doing as described above, the same effect as when the stop clock mode is performed at the L level can be obtained regardless of whether the potential level at the time of fixing the external clock signal is at the H level or the L level. No restrictions are added.

Further, even when the potential level of the external clock signal starts to move and returns from the stop clock mode state to the normal operation state, the state before the clock stop is continued without any contradiction without any special control. The operation will be restored. Further, although a timer for detecting a fixed state only on the L level side is provided in the related art, this embodiment includes a timer for detecting that the clock signal is fixed at the H level state. Therefore, in addition to the case where the clock signal is fixed at the L level and the case where the clock signal is fixed at the H level, a stop clock signal is output to a circuit which does not need to operate and the operation is stopped. Power consumption can be reduced. (Second Embodiment) A semiconductor device according to a second embodiment of the present invention will be described with reference to FIG.

Here, the present invention is applied when the external clock signal is given at twice the frequency. As shown in FIG. 5, the external clock signal CLK3 is input to the clock input circuit 1, and is output as the first internal clock signal CLK4. The first internal clock signal CLK4 is input to the frequency divider 19, and is output as a third internal clock signal CLK6 which is a half cycle clock signal. The first timer detection circuit 2 is connected to the frequency divider 19, and measures a period during which the third internal clock signal CLK6, which is the output of the frequency divider, is fixed at a constant L level potential.

The frequency divider 19 specifically has a configuration as shown in FIG. 6, for example. Here, the first internal clock signal CLK4 is transmitted from the clock input circuit 1 to the register 4
8 and outputs the third internal clock signal CLK6 from the output terminal of the register 48. The third internal clock signal CLK6 is fed back to the first input terminal of the NOR circuit 49 and input. This NOR circuit 4
9 is an inverted signal of an enable signal ENB at its second input terminal.
Is entered. The NOR circuit 49 outputs the output to the register 48 as data. In the NOR circuit, the inverted signal ENB of the input enable signal is fixed at the L level, and a signal having an inverted level of the output of the register 48 is output to the register 48.

The register 48 stores the first internal clock signal CL
The data is updated at the rising edge of K4. For this reason, since the output signal of the register 48 is inverted and input from the NOR circuit 49, each time the first clock signal CLK4 rises, the level changes from L level to H level, L level,
The H level and the data are sequentially taken into the register 48 and output. As a result, the output of the register 48 becomes a third internal clock signal CLK6 that performs a clock operation at a cycle twice that of the first internal clock signal CLK4.

Here, when it is detected that the signal is fixed at the L level for a predetermined time longer than a normal cycle time, a signal for instructing power down is output. Further, the second timer detection circuit 3 is connected to the frequency divider 19, and the third internal clock signal C
The period during which LK6 is fixed at the H level constant potential is measured. Here, when it is detected that the signal is fixed at the H level for a predetermined time longer than a normal cycle time, a signal for instructing power down is output.

The signal for instructing power down, which is the output of the first timer detection circuit 2, and the third internal clock signal CL
A NOR circuit 4 to which K6 is input is provided. Further, there is provided a first AND circuit 5 to which a signal for instructing power down, which is an output of the second timer detection circuit 3, and a third internal clock signal CLK6 are input. Outputs of the NOR circuit 4 and the first AND circuit 5 are input to an OR circuit 6. The third power-down signal PD3, which is the output of the OR circuit 6, is input to the inverter 7, and its input potential level is inverted and input to one input terminal of the second AND circuit 8. Further, the third internal clock signal CLK6 is input to the other input terminal of the second AND circuit 8. The output of the second AND circuit 8 is the fourth internal clock signal CLK.
7 is input to an internal circuit 9 that operates in synchronization with a clock signal.

The fourth internal clock signal CLK7 is at the H level only when the third internal clock signal CLK6 is at the H level and the third power down signal PD3 is at the L level, and otherwise at the L level. . The first power-down signal PD3 is input to a delay circuit 10 including a plurality of even-numbered inverter elements. The delay circuit 10 delays the input third power-down signal PD3 for a predetermined time and outputs it. The delayed third power down signal PD3 and the undelayed third power down signal PD1
Is input to the third AND circuit 11, and only when both of these two input signals are at H level, the fourth
The power down signal PD4 is output, and in other cases, the L-level fourth power down signal PD4 is output. The fourth power-down signal PD4 inactivates the plurality of individual circuits 12 that can be stopped.

Here, the individual circuit is a circuit through which a direct current flows, such as an input first-stage circuit, a programmable impedance, and a sense amplifier as shown in the first embodiment. In this case, if the detection of the operation of the clock signal by the timer as to whether the clock signal is fixed is not an external clock signal but an internal clock signal having the same frequency as the internally divided internal cycle, the above-described second clock is considered. It can be considered exactly the same as in the first embodiment.

Therefore, even if the frequency of the external clock signal is twice, the circuit operation of the internal circuit is precharged and initialized as the inactive state in the latter half of the same cycle as normal, and then the power down of the individual circuit is performed. The same effect can be obtained. Further, even when the rising / falling edge of the echo clock signal does not coincide with the edge of the data output, and the edge coincides with the center of the data output, it is １ ／ of the external frequency output from the frequency dividing circuit. A stop clock signal is generated in accordance with the rising / falling edge of the internal clock signal having a period, so that current consumption can be reduced.

[0062]

According to the present invention, when the external clock signal is stopped to reduce the current consumption, the current consumption can be reduced regardless of whether the potential of the clock signal is at the H level or the L level. In addition, it is possible to provide a semiconductor integrated circuit that can return to normal operation without a special sequence when the clock is restarted.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a first timer detection circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram of an individual circuit according to the first embodiment of the present invention.

FIG. 4 is a timing chart of the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 5 is a configuration diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 6 is a configuration diagram of a frequency dividing circuit according to a second embodiment of the present invention.

FIG. 7 is a configuration diagram of a semiconductor integrated circuit in which current consumption is reduced using a conventional clock stop method.

FIG. 8 is a timing chart of a semiconductor integrated circuit in which current consumption is reduced using a conventional clock stop method.

FIG. 9 is a circuit diagram for reducing current consumption using a conventional clock stop method.

FIG. 10 is a timing chart of a semiconductor integrated circuit in which current consumption is reduced using a conventional clock stop method using a double data rate.

FIG. 11 is a timing chart for reducing current consumption by using a conventional clock stop method using a double data rate.

FIG. 12 is a circuit diagram for reducing current consumption using a conventional clock stop method using a double data rate.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Clock input circuit 2 1st timer detection circuit 3 2nd timer detection circuit 4 NOR circuit 5 1st AND circuit 6 OR circuit 7 Inverter 8 2nd AND circuit 9 Internal circuit 10 Delay circuit 11 3rd AND circuit 12 Individual circuit 13, 14, 15 First to third P-channel transistors 16, 17 First and second N-channel transistors 18 Inverter 19 Divider 30 First inverter 31 Second inverter 32, 33, 34, 35, 36, 37 First to eighth Inverters 38, 39, 40, 41, 42 First to fifth resistive elements 43, 44, 45 First to third N-channel transistors 46, 47 First and second P-channel transistors 48 Register 49 NOR circuit

Claims (10)

[Claims] A first clock signal input from the outside which is fixed to one of a first potential level and a second potential level, and the first clock signal is measured for a predetermined time or more; A timer circuit that outputs a first activation signal that becomes an activation level when it is detected that the input state of a signal is fixed at a first potential level or a second potential level, and otherwise becomes an inactivation level A potential level when the first clock signal is inputted as a second potential level when the first activation signal at the activation level is inputted, and And a control circuit that outputs a second clock signal that is the potential level of the first clock signal when the activation signal is input. 2. The method according to claim 1, wherein a period of time during which the input level of the first clock signal input from the outside is fixed to one of the first potential level and the second potential level is measured, and the first clock signal is supplied for a predetermined period or more. A timer circuit that outputs a first activation signal that becomes an activation level when it is detected that the input state of a signal is fixed at a first potential level or a second potential level, and otherwise becomes an inactivation level A potential level when the first clock signal is inputted as a second potential level when the first activation signal at the activation level is inputted, and And a control circuit for outputting a second clock signal which is the potential level of the first clock signal when the activation signal is inputted, and the first activation signal having an activation level is inputted. The case, becomes active level after a predetermined delay time, when the first activation signal of an inactive level is input, the first
Of the inactivation level simultaneously with the input of the activation signal of
And a delay circuit that outputs an activation signal. 3. The delay time from the input of the first activation signal at the activation level to the output of the second activation signal at the activation level is at least half the cycle time of the normal operation. 3. The semiconductor integrated circuit according to claim 2, wherein the time is set as: 4. A frequency divider for dividing a first clock signal input from the outside and outputting a second clock signal; and wherein the second clock signal has a first potential level or a second potential level.
When the time of a period in which the potential level is fixed to one state is measured and it is detected that the potential level of the second clock signal is fixed to the first potential level or the second potential level for a predetermined period or more. A timer circuit that outputs a first activation signal that is at an activation level and is otherwise at an inactivation level; and a second circuit when the first activation signal is at an activation level.
A control circuit for outputting a third clock signal having a potential level equal to the potential level of the second clock signal when the first activation signal is at a non-activation level. Characteristic semiconductor integrated circuit. 5. A frequency divider for dividing a first clock signal input from the outside and outputting a second clock signal; and wherein the second clock signal has a first potential level or a second potential.
When the time of a period in which the potential level is fixed to one state is measured and it is detected that the potential level of the second clock signal is fixed to the first potential level or the second potential level for a predetermined period or more. A timer circuit that outputs a first activation signal that is at an activation level and is otherwise at an inactivation level; and a second circuit when the first activation signal is at an activation level.
A control circuit for outputting a third clock signal having a potential level equal to that of the second clock signal when the first activation signal is at the inactivation level; After the first activation signal is input, the activation level goes to an activation level after a predetermined delay time, and when the first activation signal at an inactivation level is input, the first activation signal is input. A semiconductor integrated circuit, comprising: a delay circuit that outputs a second activation signal that becomes a deactivation level at the same time as the input of the signal. 6. The delay time between the input of the first activation signal at the activation level and the output of the second activation signal at the activation level is equal to the period of the third clock signal. 6. The semiconductor integrated circuit according to claim 5, wherein the time is set to at least half of the time. 7. An apparatus according to claim 1, further comprising an analog circuit for performing a current consumption reducing operation based on an input signal and said first activation signal when said first activation signal is at an activation level. Item 5. The semiconductor integrated circuit according to any one of Items 1 to 4. 8. The semiconductor device according to claim 1, further comprising an analog circuit for performing a current consumption reducing operation based on an input signal and said second activation signal when said second activation signal is at an activation level. Item 7. The semiconductor integrated circuit according to any one of Items 2, 3, 5, and 6. 9. The semiconductor integrated circuit according to claim 1, further comprising an internal circuit that operates synchronously based on an input signal and said second clock signal. . 10. The semiconductor integrated circuit according to claim 4, further comprising an internal circuit that operates synchronously based on an input signal and said third clock signal. circuit.