JP2002009670A - Synchronization capture circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of the conventional synchronization capture circuits, that have to carry out initial cell search in a state where a spread code frequency deviation takes place between a base station and a mobile station, because of poor frequency accuracy at application of power in the case of employing an inexpensive crystal oscillator, resulting in causing a serious problem onto an inter-base station asynchronous cellular system which would require long cell search time or a system at high-speed chip rate. SOLUTION: The synchronization capture circuit in a CDMA inter-base station asynchronous cellular system performing cell searching called a three- stage search adopts the 1st stage cell search, where using slot timing detection information eliminates spread code frequency deviation, the 2nd stage search where a code group is discriminated and frame timing is detected, and the 3rd stage search where scrambling code identification is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a synchronization acquisition circuit for a receiving station in a spread spectrum communication system, and more particularly to a synchronization acquisition circuit suitable for a cell search mounted on a mobile station in an asynchronous cellular system between CDMA base stations.

[0002]

2. Description of the Related Art In a spread spectrum communication system in digital mobile communication, it is necessary to acquire synchronization of spread codes used in a transmitting station and a receiving station. In an asynchronous cellular system between CDMA base stations representing a spread spectrum communication system, a mobile station performs a synchronization acquisition process called initial cell search in order to determine a cell in which a mobile station is located when power is turned on.

A typical initial cell search in an asynchronous cellular system between CDMA base stations is described in IEICE Technical Report RCS96-122, IEICE. The content of the description is to speed up the cell search by dividing it into three stages of processing.

[0004] In a CDMA cellular system, a downlink channel from a base station to a mobile station has a configuration in which a long-period scrambling code and a short-period channelization code are multiplexed. A different scrambling code is assigned to each. Therefore, at the time of cell search, it is necessary to detect the timing of the scrambling code and determine the code type. As the channelization code, an orthogonal code such as a Hadamard code is used, and a code group common to each base station is used.

[0005] Generally, the scrambling code is 512.
Since the number of types is prepared, the method of searching for correlation values for all scrambling codes involves a problem that the circuit scale becomes large or the search time becomes long. Therefore, the cell search process is performed in the following three stages to reduce the search time and the circuit size.

FIG. 7 shows a frame configuration of a downlink control channel. The first stage is 256 [chip] with a slot cycle (15 slots per frame) in a frame.
The slot timing is detected by searching for a primary synchronization code PSC (hereinafter, referred to as a first sync code) into which a common code having a long length is inserted.

The second stage is multiplexed at the same timing as the first sync code, and is different for each slot.
By searching for a secondary synchronization code SSC (hereinafter referred to as a second sync code) in which a code of 6 [chip] makes one cycle in one frame, a frame timing is detected and a scrambling code group is identified at the same time.

In the third step, correlation values are obtained for the scrambling codes (about 8 codes) belonging to the scrambling code group identified in the second step, and the scrambling code having the highest correlation is determined.

If the correlation value of the scrambling code having the highest correlation exceeds a predetermined threshold value, the scrambling code used by the base station in which the scrambling code is located is used. The cell search is determined to be a ring code, and the cell search ends. If the threshold has not been exceeded, the search is repeated again from the first stage. After the cell search is completed, communication with the base station is started and a location registration procedure is performed.

[0010]

By the way, when the power of the mobile station is turned on, since the AFC (Auto Frequency Control) process is not performed, the frequency accuracy of the crystal oscillator is poor, and the carrier wave between the base station and the mobile station is not provided. The initial cell search must be performed in a state where the frequency deviation and the spread code frequency deviation have occurred.

The carrier frequency deviation can be tolerated to some extent by converting the correlation value between the received signal and the spread code into power.
Since the phase of the received signal and the spread code are shifted during the search, if the phase detected at the start of the search is shifted by one or more chips during the search, the cell search cannot be performed correctly, resulting in a fatal injury. Becomes A mobile station cannot use a crystal oscillator with higher precision than a base station in terms of price. In the base station, the frequency stability of the crystal oscillator is ±
Use the one of about 0.1 ppm and the mobile station is ± 3.0p
It is common to use a material of about pm.

When the frequency deviation between the base station and the mobile station is obtained in the above example, the frequency of the spreading code is fc [MHz],
± 3.1 [ppm] × fc [MHz]. fc =
In the case of 3.84 MHz, the spread code frequency deviation Δfc
= 11.9 [Hz]. This means that the phases of the spreading codes of the base station and the mobile station are shifted by 11.9 [chip] per 1 [s]. Here, the cell search detection accuracy is ±
In the case of 0.5 [chip], the time ts allowed for the cell search is as shown in Expression 1.

[0013]

(Equation 1)

For example, using the above value, fc = 3.84.
When MHz and x = ± 3.0 ppm, the time ts allowed for the cell search is 43.4 [ms]. If it exceeds this, a correlation value may not be obtained correctly in the identification of the scrambling code, or the detected timing may be shifted, so that a problem such as not being able to shift to the demodulation operation correctly occurs. This is not a problem in a synchronous cellular system between CDMA base stations or a system with a low chip rate in which the time required for cell search is short, but an asynchronous cellular system between base stations in which a relatively long cell search time is required or in a system with a high chip rate. This is a significant problem for systems.

[0015]

SUMMARY OF THE INVENTION The present invention relates to a spread code synchronizing circuit in a spread spectrum communication system, which removes a spread code frequency deviation between a transmitting station and a receiving station by using a result of synchronizing a spread code. It has a function to perform.

In the above, the spread spectrum communication system is an asynchronous cellular system between CDMA base stations that performs a cell search called a three-stage search. The method is characterized in that the spread code frequency deviation is removed using the slot timing detection information, and thereafter, the code group determination and frame timing detection in the second stage search, and the scrambling code identification in the third stage search are performed.

In the synchronization acquisition circuit, the first stage search is repeatedly executed a predetermined number of trials N calculated from the search time required for the second stage search and the third stage search, and the first first stage search is performed. If the difference value Δsft between the slot timing detected in the search and the slot timing detected in the N-th first stage search exceeds a predetermined threshold value, the value of Δsft increases. The first-stage search is repeatedly executed while adjusting the oscillation frequency of the oscillator until the oscillation converges within the threshold value, and then the second-stage search is performed.
A stage search and a third stage search are performed.

In the asynchronous cellular system between base stations which performs the three-stage cell search, a cell search means for removing a spread code frequency deviation between the base station and the mobile station using slot timing detection information of the first stage search. When,
Means for storing the correction value of the spread code frequency deviation in the non-volatile memory after the end of the cell search, and means for starting the cell search with the correction value stored in the non-volatile memory as an initial value when performing the cell search again. The above problem is solved by a synchronization acquisition circuit having the above.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a configuration diagram of a mobile station receiving system circuit in an asynchronous cellular system between CDMA base stations employing a synchronization acquisition circuit according to the present invention. The receiving system circuit in the asynchronous cellular system between CDMA base stations includes a cell search unit 10, an antenna 20, an RF unit 30, an A / D converter 40, a demodulation unit 50, a RAKE combining unit 60, a sequencer 70, and a voltage control unit 80. , Voltage controlled crystal oscillator VCO (Vo
Stage Controlled Oscillator) 90.

The RF reception signal received from the antenna 20 is down-converted by the RF unit 30 and becomes a baseband reception signal separated into IQ components. The output of the RF unit 30 is input to the A / D converter 40 for each of the I component and the Q component, and is converted into a digital signal that has been oversampled and quantized (about 4 bits) at a frequency four times the spreading code frequency. The output of the A / D converter 40 is input to the demodulation unit 50 and the cell search unit 10, respectively.

When the power is turned on, the cell search unit 10 performs a cell search to identify the scrambling code used by the base station where the mobile station is located. After the cell search is completed, the scrambling code and the frame timing are reported to the demodulation unit 50 as a report signal 51, and the demodulation unit 50
Demodulates the downlink control channel from the base station for each finger based on the scrambling code and the frame timing reported from the cell search unit 10, and performs RAKE combining by the RAKE combining unit 60 on the demodulation result of each finger. Then, the received data 61 is obtained. The received data 61 is sent to a processing unit that performs deinterleaving, error correction, and the like, and starts a location registration procedure. Note that the location registration also requires transmission of an uplink control channel from the mobile station, but the description is omitted because it deviates from the applicable range of the present invention.

After the end of the initial cell search, the AKE (Auto Frequency Control) calculated from the carrier frequency deviation detected for each finger in the RAKE combining section 60 while demodulating the downlink control channel or the communication channel.
l) The oscillation frequency of the VCO 90 is controlled by the signal 62,
The carrier code frequency deviation is reduced and the spread code frequency deviation is reduced.

Next, the cell search unit 10 will be described in detail with reference to FIG. The cell search unit 10 includes a first search unit 101, a second search unit 102, and a third search unit 103. Further, the first search unit 101 includes first correlators 1011 and 1012 and a power adder 1013. Similarly, the second search unit 102 includes a second correlator 102
The third search unit 103 includes first and second correlators 1031 and 1032 and a power adder 1033. Further, the sequencer 70 controls the entire sequence in the cell search, and has a function of performing simple calculations such as peak detection. The sequencer 70 can be easily realized by installing software in the processor, but may be realized by hardware.

Hereinafter, in describing the embodiment of the present invention, it is assumed that the frame configuration of the downlink control channel is the same as that of FIG.

The first search section 101 controls slot timing detection. The slot timing is detected by searching for the first sync code inserted at the head of each slot with a code length of 256 chips. First, the correlation values with the first sync code are obtained independently by the first correlators 1011 and 1012 for each of the I component and the Q component. First
The output of the correlators 1011 and 1012 is the power adder 1013
, And the power value of the correlation value of the I component and the power value of the correlation value of the Q component are obtained, and then cumulative addition is performed over several slots.

The details of the power adder 1013 are shown in FIG.
The power adder 1013 includes a power calculator 1013a, an adder 1013b, and a RAM (Random Access Memory) 101.
3c. The RAM 1013c stores the power addition result for each phase. In the case of the frame configuration shown in FIG. 7, the RAM 1013c has 5120 phases (1 slot × 1 slot).
For 10 symbols × 256 chips × 2 times oversampling), a memory capacity capable of storing a power addition result of about 16 bits is required.

The first correlator 1 is provided in the power calculator 1013a.
The I-component correlation value of the output 011 and the Q-component correlation value of the output of the first correlator 1012 are input, and the power value of I ² + Q ² is obtained. The adder 1013b is a power calculator 1013
The power value of the output a and the output of the RAM 1013c are added. The current power value is added to the previous power addition result stored in the RAM 1013c, and the cumulative addition is performed over several slots. The RAM 1013
The initial state of c must be all cleared (zero).

Returning to the description of FIG. 2, the sequencer 70
The power addition value for each phase stored in M1013c is read. Next, the sequencer 70 detects the phase with the highest correlation from the power addition value read from the RAM 1013c, and determines that phase as the slot timing.

The second search unit 102 is responsible for identifying scrambling code groups and detecting frame timing. By searching for a second sync code multiplexed at the same timing as the first sync code and having a different 256-chip length code inserted for each slot, the identification of the scrambling code group and the frame timing are detected.

The sequencer 70 converts the slot timing detected by the first search section into second correlators 1021, 1022.
Is notified as a correlation start timing signal 1024,
The second correlator starts correlation processing according to the correlation start timing signal. The second sync code is a predetermined n
The 256 types of codes having a length of 256 chips constitute m types of comma-free codes in one frame period. Here, m means the number of scrambling code groups.

Hereinafter, the description will be made assuming that the number m of scrambling code groups is 64 and that eight scrambling codes belong to one group. Note that n
Is 16.

In the second correlators 1021 and 1022, n = 16 types of correlation values are obtained for each slot independently for each of the I component and the Q component, and the power adder 1023 calculates the correlation value of the I-axis component similarly to the first search unit. After calculating the power value of the correlation value between the and the Q-axis component, the power value is cumulatively added at the frame period. Power adder 1023 has the same configuration as power adder 1013. However, it is necessary that the RAM has a memory capacity of n × 15 slots = 240 words and about 16 bits per word.

The sequencer 70 reads the power addition results accumulated over several frames, correlates with m types of comma-free codes, identifies scrambling code groups, and detects frame timing.

The third search section 103 is responsible for identifying scrambling codes. Correlation values are obtained for eight types of scrambling codes belonging to the scrambling code group identified by the second search unit.

The sequencer 70 notifies the third correlator of the frame timing detected by the second search unit as a correlation start timing signal 1034, and starts correlation with eight types of scrambling codes according to the correlation start timing. The correlation between the I-axis component and the Q-axis component is obtained independently by the third correlators 1031 and 1032, and the power adder 103
After obtaining the power of the correlation value of the I-axis component and the power of the correlation value of the Q-axis component by 3, the power is cumulatively added at the symbol period.

The power adder 1033 is a power adder 1013
It has the same configuration as. However, a RAM having a memory capacity of 8 words and about 16 bits per word is required. The sequencer 70 reads the power addition result accumulated over several symbols for each of the eight types of scrambling codes, and determines a scrambling code having the highest correlation among them. If the correlation value of the scrambling code with the highest correlation exceeds a preset threshold value, it is determined that the scrambling code is used by the base station located in the area where the scrambling code is located. And terminate the cell search. If the threshold is not exceeded, the search is repeated from the first stage again.

FIG. 4 is a diagram showing the voltage control unit 80 in FIG. 2 in detail. The voltage control unit 80 includes a register 801,
807, a phase comparator 802, a low-pass filter 803,
Gain adjuster 804, adder 805, selector 806,
D / A converter 808, write enable switch 80
9. A non-volatile memory 810 (here, a flash memory is used).

The slot timing 71 obtained by the sequencer 70 based on the search result of the first search unit 101 is stored in the register 80 inside the voltage control unit 80 in FIG.
1 and the phase comparator 802. The slot timing 71 is input as phase information Tslot, and the value of Tslot is, for example, 1 to 5120 (1 slot × 10 symbols ×
256 chip × 2 times oversampling).

Here, assuming that the slot timing input at time n is Tslot [n], the previous slot timing Tslot [n-1] is stored in the register 801 and the phase comparator 802 stores the time n At the slot timing Tslot [n] at time n-1
[N-1] is input. The Tslot [n-1] at the time n-1 and the Tslo at the time n are calculated by the phase comparator 802.
A difference value from t [n] is obtained, and Tslot [n-1]
When the value of Tslot [n] is large (phase advance) as compared with Tslot [n−1], Tslo [n] is positive.
When the value of t [n] is small (phase advance), a negative value is obtained as an output. Note that the output E of the phase comparator 802 is
[N] has a configuration that the sequencer 70 can monitor.

The above Tslot [n-1] and Tslot
The difference value of [n] is transmitted to the low-pass filter 803,
After the loop gain has been adjusted by the gain adjuster 804, it is input to the adder 805 as a correction value C [n].

Here, the loop gain of the gain adjuster 804 is a negative gain in order to reverse the advance or delay of the phase detected by the phase comparator 802 in the reverse direction. In the adder 805, the digital input value D of the DA converter given to the VCO 90 at time n-1 and stored in the register 807
[N-1] and the correction value C [n] at time n are added. At this time, the selector 806 is connected to B.

The DA converter 808 has a function of converting a digital input value into a voltage, and the output of the DA converter 808 is a VC
The control voltage 81 applied to O90 is obtained. When the oscillation frequency at the control voltage V0 [V] is f0 [Hz], the VCO 90 changes from V0−ΔVmax [V] to V0 + ΔVmax.
F0-Δfmax with respect to the control voltage range up to [V]
This is a voltage controlled crystal oscillator in which the frequency from [Hz] to f0 + Δfmax [Hz] is in a variable range. Generally V
CO has a large variable range with respect to the frequency stability ± x [ppm].

FIG. 5 is a graph showing the oscillation frequency with respect to the control voltage of the VCO. The frequency stability of the VCO 90 is ± 3.
In the case of 0 ppm, V0−ΔVma as shown in FIG.
When changing from x [V] to V0 + ΔVmax [V], the frequency control range is about ± 4.0 ppm. A digital value necessary for generating V0 [V] is stored in the flash memory 810 in advance.

The configuration of the cell search has been described above. Next, the control flow of the cell search will be described with reference to FIG.
When the cell search is started, first, the cell search trial number i
Is not exceeded the maximum number of trials Ntry, and if it is not exceeded, the first stage search is started.

At the time of i = 1, that is, at the time of the first search, the selector 806 in FIG. 4 is connected to A and V0 stored in the flash memory 810 in advance.
The digital value that generates [V] is the D / A converter 808
And the control voltage is fixed at V0 [V].
When the control voltage of the VCO 90 is fixed at V0 [V], the first stage search is executed N1 times to obtain Δs
The value of ft is obtained, and it is determined whether the value of Δsft is greater than 1 [chip]. Δsft is obtained by Expression 2.

[0046]

(Equation 2)

The number of times N1 is obtained by Equation 3 where the search times required for the first-stage search, the second-stage search, and the third-stage search are Ts1, Ts2, and Ts3, respectively.

[0048]

(Equation 3)

Δ obtained by executing the first stage search N1 times
When the absolute value of sft is smaller than 0.5 [chip], the time required for the second-stage search and the third-stage search is such that the deviation of the spreading code between the base station and the mobile station is 0.5 [c].
[Hip], the process proceeds to the second-stage search and the third-stage search. If the absolute value of Δsft is larger than 0.5 [chip], the error of the crystal oscillator is large and the second-stage search and the third-stage search are considered not to be performed normally, and the first-stage search having the VCO correction function is performed. Start.

The first-stage search having the VCO correction function can be realized by switching the selector 806 of FIG. By switching the connection of the selector 806 to B, the phase comparison result E [n] detected by the phase comparator 802 can be reflected on the control voltage 81 applied to the VCO 90.

The spread code frequency deviation between the base station and the mobile station is detected by the phase comparator 802 as the phase comparison result E [n], where E [n] is the LPF 803 and the gain adjuster 8
04, and becomes a correction value C [n].
The value obtained by adding the digital input value D [n-1] to the A converter 808 is input to the D / A converter 808 as D [n]. Δsf obtained by executing the first stage search N1 times while monitoring the phase comparison result E [n] by the sequencer
The first-stage search is continued until the absolute value of t converges to 0.5 [chip] or less.

After the absolute value of Δsft converges to 0.5 [chip] or less, a scrambling code group and frame timing are detected in a second stage search, and eight types of scrambling codes are detected in a third stage search. Is identified.

In the third stage search, if the correlation value h with the scrambling code having the highest correlation exceeds a predetermined threshold Thr, the write enable switch 809 is enabled, and The final digital input value D to the D / A converter 808 is written into the flash memory, and the cell search ends. If the correlation value h does not exceed the threshold value Thr,
Assuming that the cell search was not performed normally, the number of trials i is incremented and the cell search is retried. If the correlation value h does not exceed Thr even after performing Ntry times, it is out of the service area.

After the end of the cell search, the demodulation section demodulates the control channel, registers the position with the base station, and thereafter the mobile station enters a standby state. At this time, the selector 806 is switched to connection C from the start of demodulation, and the VCO
It is entrusted to a demodulation unit having a function.

When the power is turned off, the VCO correction value is written in the flash memory. When the power is turned on again, the selector 806 is switched to connection A, and the cell search is started according to the control flow shown in FIG. As a result, the cell search time for the second and subsequent times can be significantly reduced unless a rapid temperature change or a mobile station moves at a high speed.

In the above description, in order to make the operation easy to understand, it is assumed that the slot timing is detected stably in the first stage search, but a plurality of base stations are received with substantially the same power. Alternatively, when the received power fluctuates due to fading, the slot timing is not always detected stably, and the slot timing detected at time n and the slot timing detected at time n + 1 are those of different base stations. there is a possibility.

When such a case is assumed, 2
By providing a detection window in the first and subsequent first-stage searches and restricting the search range so as not to detect other base stations, it becomes possible to detect slot timing stably.

[0058]

According to the present invention, a cell search can be performed normally even when the frequency stability of the crystal oscillator at the time of power-on is poor, so that a low-cost and low-precision crystal oscillator can be used. This leads to the effect of reducing the cost of the mobile station. After the cell search is completed and when the power is turned off, the VCO correction value is stored in the flash memory. When the cell search is performed again, the cell search is performed using the value stored in the flash memory as the VCO correction value. As a result, the cell search time can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a receiving circuit in a mobile station of an asynchronous cellular system between CDMA base stations according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a cell search unit 10 of FIG.

FIG. 3 is a block diagram showing details of a power adder 1013 in FIG. 2;

FIG. 4 is a block diagram showing details of a voltage control unit 80 in FIG. 1;

FIG. 5 is a graph showing a relationship between a control voltage of a VCO and an oscillation frequency.

FIG. 6 is a control flowchart of cell search according to one embodiment of the present invention.

FIG. 7 is an explanatory diagram showing an example of a frame configuration of a downlink control channel.

[Explanation of symbols]

10 cell search unit, 20 antenna, 30 RF unit,
40 A / D converter, 50 demodulation unit, 60 RAKE combining unit, 70 sequencer, 80 voltage control unit, 90 voltage controlled crystal oscillator VCO, 101 first search unit, 10
2 ... second search unit, 103 ... third search unit, 801, 8
07: register, 802: phase comparator, 803: low-pass filter, 804: gain adjuster, 805: adder,
806: selector, 808: D / A converter, 809: write enable switch, 810: nonvolatile memory (flash memory), 1011, 1012: first correlator, 1013: power adder, 1021, 1022: second
Correlator, 1023 ... power adder, 1031, 1032 ...
Third correlator, 1033 ... power adder.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5K022 EE01 EE36 5K047 AA02 AA16 BB01 BB05 CC01 DD01 DD02 GG27 GG44 HH02 HH15 HH45 JJ06 LL06 MM13 MM45

Claims (4)

[Claims] A spread code synchronization acquisition circuit in a spread spectrum communication system, characterized by having a function of removing a spread code frequency deviation between a transmission station and a reception station using a synchronization acquisition result of a spread code. Synchronization acquisition circuit. 2. The spread spectrum communication system according to claim 1, wherein the spread spectrum communication system is an asynchronous cellular system between CDMA base stations that performs a cell search called a three-stage search, wherein the spread-spectrum communication system uses slot timing detection information in the first-stage search of the cell search. A synchronous code acquisition circuit for removing a spread code frequency deviation, and then performing a code group determination and a frame timing detection in a second stage search and a scrambling code identification in a third stage search. 3. The method according to claim 2, wherein the first stage search is performed in the second stage.
The predetermined number of trials calculated from the search time required for the stage search and the third stage search is repeatedly executed N times, and the slot timing detected in the first first stage search and the Nth first stage search If the difference value Δsft from the detected slot timing exceeds a predetermined threshold, the first step is performed while adjusting the oscillation frequency of the oscillator until the value Δsft converges within the threshold value. A synchronization acquisition circuit that repeatedly executes a search, and thereafter performs a second-stage search and a third-stage search. 4. The synchronization acquisition circuit according to claim 3, further comprising a non-volatile memory, wherein a correction value of the spread code frequency deviation is stored in the non-volatile memory after the cell search is completed, and when the cell search is performed again, A synchronization acquisition circuit, wherein a first stage search of a cell search is started with a correction value stored in the nonvolatile memory as an initial value.