JP2002009600A - Switch circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switch circuit consisting of many MOSFETs connected in series that increases a noise margin in an off-state. SOLUTION: The switch circuit 10 is configured by connecting each drain of the MOSFETs Q1-Q40 to each source of an upper stage in series sequentially. When no on-signal is given between control terminals 3 and 4 and the Q1-Q40 are not conductive, all capacitors C40-C1 are charged through the path of R40 →C40 → the source of the Q40 → the gate of the Q40 → ...R1 → C1 to apply a reverse bias voltage to each MOSFET. In this case, Zener diodes D1, DD1-D40, DD40 that are connected in series in opposite polarity are respectively connected in parallel between each gate and each source of each of the Q1-Q40 to decide the reverse bias voltage to be a proper value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a switch circuit using a semiconductor, and more particularly to a switch circuit suitable for application to a high-voltage circuit configured by connecting a plurality of MOSFETs in series.

[0002]

2. Description of the Related Art A conventional switch circuit constituted by connecting a plurality of MOSFETs in series has a structure disclosed in, for example, JP-A-60-93820. That is, in a switch circuit composed of a MOSFET whose conduction is controlled by a control signal given to the gate and one or a plurality of MOSFETs which are sequentially connected in series to the drain side of the MOSFET and operate following the operation of the MOSFET. , The source of the MOSFET whose conduction is controlled by a control signal given to the gate, the gate of the MOSFET connected in series thereto, the source of each MOSFET connected in series and the gate of each MOSFET connected thereto, and M connected in series
Each MOSFET connected in series with a MOSFET whose conduction is controlled by a control signal given to the gate, wherein a series circuit consisting of a capacitor and a resistor is connected between the source and the drain of the MOSFET located last in the OSFET.
There is disclosed a switch circuit in which a Zener diode is connected between the source and the gate of the FET.

[0003]

When the circuit is operated with the conventional circuit configuration and the main current of the circuit increases, the MOSF
Noise may enter the gate via the capacitance between the drain and the gate of the ET, and if this phenomenon occurs when the gate signal is off, the MOSFET malfunctions. SUMMARY OF THE INVENTION It is an object of the present invention to maintain a large off-state noise margin in a DC high voltage electronic switch circuit.

[0004]

Means for Solving the Problems In order to solve this problem, the present invention proposes the following means.
That is, a switch circuit consisting of a MOSFET whose conduction is controlled by a control signal given to the gate and a plurality of MOSFETs which are sequentially connected in series to the drain side of the MOSFET and operate following the operation of the MOSFET. A source of a MOSFET whose conduction is controlled by a given control signal and an MO connected in series with the source
The gate of the SFET and each MOSF connected in series
A series circuit consisting of a capacitor and a resistor is connected between the source and drain of the MOSFET located at the end of the ET source and the gate of each MOSFET connected to the ET, and the MOSFET sequentially connected in series, and is given to the gate. In a switch circuit in which a first constant voltage diode is connected between a source and a gate of each MOSFET sequentially connected in series with a MOSFET whose conduction is controlled by a control signal, each MOSFET is connected in series with each of the first constant voltage diodes. A switch circuit characterized by connecting a second constant voltage diode with reverse polarity is proposed. Each second constant voltage diode is
Since a sufficient reverse bias voltage is maintained between the gate and the source of the OSFET, a sufficient margin for noise voltage can be obtained.

[0005]

FIG. 1 shows an example of an embodiment of a switch circuit according to the present invention, which is a switch circuit having a withstand voltage of 30 kilovolts. Terminal 1 of this switch circuit 10
And the terminal 2 are placed above a potential point charged with a DC high voltage, and a drive signal is transmitted to the charged potential by a two-insulation drive circuit shown in the following figure. Terminal 1
40 terminals of the MOSFETs Q1 to MOS
The source and drain of the MOSFET of the FET Q40 are connected in series with each other. Each MOSFE
Although the withstand voltage of TQ1 to MOSFET Q40 is 1 kilovolt, it is designed with more margin than the sum of the simple withstand voltages. A resistor group in which resistors RR1 to RR40 having relatively high resistance values are connected in series is connected between the terminal 1 and the terminal 2. These resistors are, for example, a resistor RR1 and a resistor RR2.
Is connected to the gate of MOSFET Q2,
Hereinafter, similarly, the interconnection points of the resistors are connected to the MOSFETs Q3 to
Connected to the gate of MOSFET Q40. The resistors RR1 to RR40 connected in series are connected to the MOSFET Q1.
When Q40 is off, the voltage sharing due to each leakage current and the like is made uniform. The gate of the MOSFET Q1;
Zener diodes D1 and DD1 connected in series in opposite directions are connected between the sources. Similarly, M
Zener diodes D2, DD2 to D40, DD40 connected in series in opposite directions to each other are also connected between the gate and source of the OSFETs Q2 to MOSFET Q40. A series circuit of a resistor R1 and a capacitor C1 is connected between the source of the MOSFET Q1 and the base of the MOSFET Q2.
Source of SFET Q39 and MOSFETs Q3 to MOSFET
It is respectively connected between the gate of ETQ40. Regarding the uppermost MOSFET Q40, a series circuit of the resistor R40 and the capacitor 40 is connected between the source of the MOSFET Q40 and the terminal 1. The bottom MOSFET
The gate of Q1 is connected to terminal 3 and the source of MOSFET Q1 is connected to terminal 4. The Zener diodes D1 to D40 and DD1 to DD40 are not limited to Zener diodes as long as they exhibit constant voltage characteristics, and other types and semiconductors can be used.

FIG. 2 shows an example of an insulation drive circuit in a switch circuit according to an embodiment of the present invention. The insulation drive circuit 100 is configured to insulate the insulation drive circuit 100 from the low-voltage high-frequency source 101 to the required withstand voltage via the primary winding and the secondary winding of the insulation transformer 120 and to connect the insulation drive circuit to the high-voltage circuit. 1
It supplies a relatively small amount of power required for 00.
That is, the relatively low voltage of the secondary winding of the insulating transformer 120 is rectified by the rectifier 121, smoothed by the capacitor 122, and supplied to the circuit of the transistor 110 and the optical receiver 107 as the common line COM and the internal power line VCC. Supply. The pulse signal from the pulse source 102 on the low voltage side is converted into an optical signal by the light emitting diode 103 and transmitted to the optical receiver 107 while being insulated by the optical fiber 106 so as to obtain a required withstand voltage. A resistor 108 is connected to the output terminal of the optical receiver 107 between the output terminal of the optical receiver 107 and the + side of the internal power supply, and a resistor 109 is connected between the output terminal and the − side of the internal power supply. The output terminal of the optical receiver 107 is connected to the base of the transistor 110. The emitter of the transistor 110 is connected to the negative side of the internal power supply and to the terminal 104, and the collector is connected to the internal power supply + side and to the terminal 103 via the resistor 111.

The pulse signal transmission operation of the insulated driving circuit 100 shown in FIG. 2 is performed during a short period in which the pulse signal of the low-voltage side pulse source 102 is at the H level.
3, an optical signal is generated, the optical receiver 107 is turned on via the optical fiber 106, the L signal is turned on, and the base of the transistor 110 is also turned L signal. Therefore, the transistor 110 is turned off, the collector potential becomes the H signal, and the terminal 103 is turned on. And an H signal is generated between. Conversely, when the pulse signal from the low-voltage side pulse source 102 is at L level, an L signal is generated between terminals 103 and 104. The signal between the terminals 103 and 104 is connected to the terminals 3 and 4 of the switch circuit 10 shown in FIG. 1, and is driven in an insulated state.

The operation of the switch circuit 10 is as follows. When a positive gate signal is not applied to the MOSFET Q1, the MOSFET Q1 is in an off state, and the MOSFETs Q2 to Q40 that operate accordingly are also in an off state, and the voltage E is applied between the terminals 1 and 2. Assuming that the capacitances of the capacitors C1 to C40 are substantially equal, and ignoring the voltage values of the Zener diodes D, DD, etc., the capacitors C1 to C40 share the voltage E almost equally, and the MOSFETs Q1 to Q40 , A voltage substantially equal to that of the capacitors C1 to C40 is applied with a polarity having the upper side of the figure as positive. Next, when a positive gate signal is applied to the MOSFET Q1, the MOSFET Q1 starts conducting. When the MOSFET Q1 starts conducting, the electric charge of the capacitor C1 starts discharging through the resistor R1, the gate and source of the MOSFET Q2 and the drain and source of the MOSFET Q1, and a sufficient voltage between the gate and the source of the MOSFET Q2 to operate the MOSFET Q2. The applied MOSFET Q2 starts conducting. The Zener diodes DD1 and D1 are for suppressing the voltage between the gate and the source of the MOSFET Q2 to a predetermined value or less. MOSFETs Q3 to Q40 are also MOSFE
Conduction starts sequentially in the same manner as in TQ2, and the switch circuit 1
0 is turned on. Since the positive gate signal continues to be applied during the ON period, the MOSFET Q1 maintains the ON state with a small ON resistance. Since there is no resistor connected between the gate and the source of the MOSFET Q2 to allow a current to flow, a voltage determined by the Zener diodes D2, DD2, etc. is continuously applied between the gate and the source.
In the same manner as described above, the ON state is maintained with a sufficiently small ON resistance. M
The OSFETs Q3 to Q40 maintain the ON state similarly to the MOSFET Q2. Therefore, even if a large number are connected in series, the on-resistance can be sufficiently reduced.

When the application of the gate signal of the MOSFET Q1 is stopped, the MOSFET Q1 is turned off and the MO
The drain current of the SFET Q1 becomes 0. Therefore, the current flowing through the switch circuit 10 flows through the source → gate → resistance R1 → capacitor C1 → terminal 2 of the MOSFET Q2, and cancels the charge between the gate and the source of the MOSFET Q2 when turned on. When charge between the gate and the source of MOSFET Q2 is erased, MOSFET Q2
Is turned off, and the current becomes zero. The current flowing through the switch circuit 10 flows through the source of the MOSFET Q3 → the gate → the resistor R2 → the capacitor C2.
3, the charge between the gate and the source is canceled and the MOS
FET Q3 is turned off. Similarly, the MOSFETs Q4, Q5,..., Q40 are turned off instantaneously, and the switch circuit 10 is turned off. Since the switching time of the MOSFET is as short as several tens of ns or less, there is almost no imbalance in the shared voltage due to the difference between the switching times in the above-described ON operation and OFF operation. Moreover, the rate of change of the load circuit current at the time of switch-off can be reduced by the capacitors C1 to C40, and application of an excessive voltage to the switch-off circuit can be prevented.

FIG. 3 is a circuit diagram of the switch circuit shown in FIG.
MO when pulse drive is performed by the insulation drive circuit shown in
7 shows a waveform of a gate-source voltage of the SFET Q2. When the pulse signal is at the H level, a positive bias of about +15 V is applied to the gate-source voltage at the peak A point in the figure, and when the pulse signal is at the L level, the gate-source voltage is at about the peak B point in the figure. A negative bias of -15 V is applied to provide a sufficient noise margin.

FIG. 4 shows a waveform of a gate-source voltage of a MOSFET when pulse driving is performed in a conventional switch circuit. When the pulse signal is at the H level, a positive bias of about +15 V is applied to the gate-source voltage at the peak C point in the figure, and when the pulse signal is at the L level, the gate-source voltage is about-at the point D in the figure. Only a slight negative bias of 0.5 V is applied.

[0012]

The present invention has the features as described above. In a switch circuit in which MOSFETs are connected in series, a sufficient negative bias can be applied at the time of off, and malfunction of the MOSFETs can be eliminated. . In addition, the circuit configuration is not complicated because only a constant voltage diode is added between the gate and the source of each stage MOSFET.

[Brief description of the drawings]

FIG. 1 shows an embodiment of a switch circuit according to the present invention.

FIG. 2 shows an example of an insulating drive circuit in a switch circuit according to an embodiment of the present invention.

FIG. 3 is a diagram showing a MOSFE in the switch circuit shown in FIG. 1;
3 shows a waveform of a voltage between a gate and a source of T.

FIG. 4 shows a waveform of a voltage between a gate and a source of a MOSFET in a conventional switch circuit.

[Explanation of symbols]

1, 2,... Terminals Q1, Q2. . . Q40: MOSFET R1, R2. . . R40... Resistors RR1, RR2. . . RR40 ... resistance C1, C2. . . C40: Capacitors D1, D2. . . D40: Zener diode DD1, DD2. . . DD40: Zener diode 10: Switch circuit 100: Insulation drive circuit 101: High frequency source 102
... Pulse source 103 ... Light-emitting diode 106 ... Optical fiber 107 ... Optical receiver 120 ... Insulation transformer

Claims (1)

[Claims] 1. A switch circuit comprising a MOSFET whose conduction is controlled by a control signal applied to a gate and a plurality of MOSFETs connected in series to the drain side of the MOSFET and operating in accordance with the operation of the MOSFET. , The source of a MOSFET whose conduction is controlled by a control signal applied to the gate, the gate of a MOSFET connected in series to the source, and each MO connected in series.
A series circuit consisting of a capacitor and a resistor is connected between the source and drain of the SFET source, the gate of each MOSFET connected thereto, and the last MOSFET among the serially connected MOSFETs, and is applied to the gate. MOSFE whose conduction is controlled by a control signal
In a switch circuit in which a first constant voltage diode is connected between the source and the gate of each MOSFET sequentially connected to T in series, a second constant voltage having a reverse polarity is connected in series with each of the first constant voltage diodes. A switch circuit comprising a diode connected.