JP2002009597A - Key input circuit - Google Patents

Key input circuit

Info

Publication number
JP2002009597A
JP2002009597A JP2000185860A JP2000185860A JP2002009597A JP 2002009597 A JP2002009597 A JP 2002009597A JP 2000185860 A JP2000185860 A JP 2000185860A JP 2000185860 A JP2000185860 A JP 2000185860A JP 2002009597 A JP2002009597 A JP 2002009597A
Authority
JP
Japan
Prior art keywords
switch
current
level
circuit
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000185860A
Other languages
Japanese (ja)
Inventor
Toshiaki Suzuki
敏明 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2000185860A priority Critical patent/JP2002009597A/en
Publication of JP2002009597A publication Critical patent/JP2002009597A/en
Pending legal-status Critical Current

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  • Electronic Switches (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a key input circuit that can reduce its current consumption and allows a circuit network to read the switching. SOLUTION: This invention provides a technological concept such that an external disturbance by a switch operation is given to the circuit network in a state of holding a digital signal through positive feedback so as to allow the circuit network to capture a switch level. The output of the circuit is fixed to an L or H level while the positive feedback is active. When the switch state does not match the state level of the circuit network, a current momentarily flows to the switch, but positive feedback becomes soon active to converge the voltage level to the same level. Thus, the switch level can be read without the need for supplying a steady-state current to the switch.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、消費電流を少なく
してキースイッチの入力を行う回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for inputting a key switch while reducing current consumption.

【0002】[0002]

【従来の技術】従来、スイッチの開閉状態を入力するた
めには、プルアップ抵抗などの電流を常時流す方法によ
り検出していた。たとえば、スイッチの片側をプルアッ
プ抵抗を介して、電源に接続しておき、スイッチの反対
側をグランド側にしておけば、スイッチの開閉により、
片側の電圧は電源とグランド間の電圧範囲でスイングす
る。
2. Description of the Related Art Conventionally, in order to input the open / closed state of a switch, a current such as a pull-up resistor is always detected by a method of flowing the current. For example, if one side of the switch is connected to the power supply via a pull-up resistor and the other side of the switch is grounded,
The voltage on one side swings in the voltage range between the power supply and ground.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、この様
な方法では、スイッチを閉じたときにプルアップ抵抗に
常時電流が流れ続けることになる。そこで、本発明は、
スイッチに流れる定常電流を無くする事により、消費電
流を少なくするという課題を解決するものである。
However, in such a method, current always flows through the pull-up resistor when the switch is closed. Therefore, the present invention
An object of the present invention is to solve the problem of reducing current consumption by eliminating a steady current flowing through a switch.

【0004】[0004]

【課題を解決するための手段】この課題を解決するため
に、正帰還をかけてデジタル信号を保持できる状態の回
路網に、スイッチ操作による外乱を与え、スイッチのレ
ベルを回路網に取り込もうという技術思想である。
In order to solve this problem, a disturbance is caused by a switch operation on a network capable of holding a digital signal by applying positive feedback, and the level of the switch is taken into the network. It is a technical idea.

【0005】スイッチの状態と、回路網の状態レベルが
一致していないときには、一瞬スイッチに電流が流れる
が、すぐに正帰還がかかり、同一電圧レベルに収束す
る。この事により、スイッチには定常電流が流れること
なくスイッチのレベルを読みとることが出来る。
When the state of the switch and the state level of the circuit network do not match, a current flows through the switch for a moment, but positive feedback is immediately applied and the voltage converges to the same voltage level. As a result, the level of the switch can be read without a steady current flowing through the switch.

【0006】[0006]

【発明の実施の形態】以下、本発明の実施の形態につい
て、図1から図3を用いて説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

【0007】図1は、本発明の基本的な構成図を示す。FIG. 1 shows a basic configuration diagram of the present invention.

【0008】図1において、スイッチ1は、1回路2接
点のメークスイッチであり、一方を電源に他方をグラン
ドに接続している。入力バッファーとしてのインバータ
2は、単純に信号を反転処理する。トランジスタ4,5
と電流制限抵抗3,6からは電流制限付きの出力ドライ
バーが構成されている。この出力ドライバーは、電流制
限されるところがポイントであり、通常のドライバーで
はなく、更にインバータ2の入力側に正帰還をかけてい
る。この事により、スイッチ1がオープン状態でもイン
バータ2の入力レベルはH/Lが決まる。正帰還をかけ
ているため、スイッチをどちらかに接続したままでも電
流は流れない。切り替えの過渡期にのみ電流が一瞬流れ
るだけである。
In FIG. 1, a switch 1 is a make switch having one contact and two contacts, one of which is connected to a power supply and the other is connected to ground. The inverter 2 as an input buffer simply inverts the signal. Transistors 4, 5
And the current limiting resistors 3 and 6 constitute an output driver with current limitation. The point of this output driver is that the current is limited, and the output driver is not a normal driver but also applies a positive feedback to the input side of the inverter 2. As a result, the input level of the inverter 2 is determined to be H / L even when the switch 1 is in the open state. Since positive feedback is applied, no current flows even if the switch is connected to either side. The current flows only momentarily only during the transitional period of switching.

【0009】電流制限の目処としては、この回路を実装
する基板のリーク電流が無視できる程度の大きさで、出
来るだけ、少ない方が好ましい。実施の形態としては、
50マイクロアンペア程度に制限している。
As a target of the current limitation, it is preferable that the leakage current of the substrate on which this circuit is mounted is negligible and is as small as possible. As an embodiment,
It is limited to about 50 microamps.

【0010】入力バッファーの出力を受ける単純なイン
バータは、スイッチの状態を読み出すための回路であ
り、出力負荷の影響を遮断するための回路である。
A simple inverter receiving the output of the input buffer is a circuit for reading out the state of the switch, and is a circuit for cutting off the influence of the output load.

【0011】図2は、リセット信号によりLの初期値に
設定する場合の図を示す。インバータの代わりに、NA
NDゲート8を用い、リセット信号がLレベル時に初期
値をLに設定する。
FIG. 2 shows a case where the reset signal sets the initial value of L. NA instead of inverter
Using the ND gate 8, the initial value is set to L when the reset signal is at L level.

【0012】図3は、リセット信号によりHの初期値に
設定する場合の図を示す。インバータの代わりに、NO
Rゲート9を用い、リセット信号がLレベル時に初期値
をHに設定する。
FIG. 3 shows a case where the initial value of H is set by a reset signal. NO instead of inverter
The initial value is set to H when the reset signal is at L level using the R gate 9.

【0013】以上のように本発明の実施の形態によれ
ば、抵抗に定常電流を流さずに、スイッチ1のレベルを
検出する事が出来る。
As described above, according to the embodiment of the present invention, the level of the switch 1 can be detected without passing a steady current through the resistor.

【0014】[0014]

【発明の効果】以上のように本発明に係るスイッチの入
力回路は、信号を入力するための入力バッファーと、前
記入力バッファー出力を増幅し、電流制限する電流制限
手段を備えた出力ドライバーと、前記出力ドライバーの
出力側を前記入力バッファーの入力側に正帰還をかける
手段を備えた事により、定常的に電流を流さなくてもス
イッチのレベルを検出することが出来る。
As described above, the input circuit of the switch according to the present invention comprises: an input buffer for inputting a signal; an output driver having current limiting means for amplifying the output of the input buffer and limiting the current; Since the output side of the output driver is provided with a means for applying a positive feedback to the input side of the input buffer, the level of the switch can be detected without constantly flowing a current.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の基本的な構成図FIG. 1 is a basic configuration diagram of the present invention.

【図2】初期値をLに設定する場合の図FIG. 2 is a diagram when an initial value is set to L;

【図3】初期値をHに設定する場合の図FIG. 3 is a diagram when an initial value is set to H;

【符号の説明】[Explanation of symbols]

1 スイッチ 2 入力バッファー 3 電流制限抵抗 4 トランジスタ 5 トランジスタ 6 電流制限抵抗 7 出力バッファー 8 NANDゲート 9 NORゲート DESCRIPTION OF SYMBOLS 1 Switch 2 Input buffer 3 Current limiting resistor 4 Transistor 5 Transistor 6 Current limiting resistor 7 Output buffer 8 NAND gate 9 NOR gate

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 信号を入力するための入力バッファー
と、前記入力バッファー出力を増幅し、入力信号源の電
流駆動能力に比べ、桁違いに少ない電流しか流せないよ
うに電流制限する電流制限手段を備えた出力ドライバー
と、前記出力ドライバーの出力側を前記入力バッファー
の入力側に正帰還をかける手段を備えた、キー入力回
路。
An input buffer for inputting a signal and current limiting means for amplifying the output of the input buffer and limiting the current so as to allow a current to flow by orders of magnitude less than the current driving capability of the input signal source. A key input circuit, comprising: an output driver provided with the output driver; and a means for applying a positive feedback from an output side of the output driver to an input side of the input buffer.
【請求項2】 請求項1記載の入力バッファーをNAN
DゲートもしくはNORゲート等で構成し、初期値を設
定するためのリセット信号を受理する手段を備えたキー
入力回路。
2. The input buffer according to claim 1, wherein the input buffer is NAN.
A key input circuit comprising a D gate or a NOR gate and having means for receiving a reset signal for setting an initial value.
JP2000185860A 2000-06-21 2000-06-21 Key input circuit Pending JP2002009597A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000185860A JP2002009597A (en) 2000-06-21 2000-06-21 Key input circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000185860A JP2002009597A (en) 2000-06-21 2000-06-21 Key input circuit

Publications (1)

Publication Number Publication Date
JP2002009597A true JP2002009597A (en) 2002-01-11

Family

ID=18686117

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000185860A Pending JP2002009597A (en) 2000-06-21 2000-06-21 Key input circuit

Country Status (1)

Country Link
JP (1) JP2002009597A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116455373A (en) * 2023-06-14 2023-07-18 芯迈微半导体(上海)有限公司 Reset trigger circuit of digital chip, digital chip and digital circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116455373A (en) * 2023-06-14 2023-07-18 芯迈微半导体(上海)有限公司 Reset trigger circuit of digital chip, digital chip and digital circuit
CN116455373B (en) * 2023-06-14 2023-09-05 芯迈微半导体(上海)有限公司 Reset trigger circuit of digital chip, digital chip and digital circuit

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