JP2002008373A - Potential generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a potential generating circuit having a circuit for charging electricity in a special case. SOLUTION: A potential generating circuit 16 forms a VBLH. The value of the VBLH is kept monitored at all times and is fed back by voltage dividing circuits R1 and R2 and a comparator circuit OP1 to the gate of a transistor MP1. The responsiveness of the feedback route of the potential generating circuit 16 is delayed in order to prevent the oscillation of the VBLH. At this time, the potential circuit 16 is in a stable state and the charging operation by the TR MP1 is not carried out in the special case, i.e., in the first operation period after the specified period when the non-operation period of a semiconductor circuit receiving the supply of the potential is a specified period or longer. The charging operation is forcedly carried out only in this special case.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a potential generating circuit, and more particularly, to a potential generating circuit for supplying a potential to a semiconductor circuit which is frequently activated, such as a sense amplifier or a buffer of a semiconductor memory.

[0002]

2. Description of the Related Art At present, various functions such as DRAM, SRAM, nonvolatile semiconductor memory, ASIC (including ASIC, ASIC with embedded memory), system LSI, microprocessor, etc. This can be realized by a combination of semiconductor circuits.

Here, each semiconductor circuit is driven by a power supply potential (including an external power supply potential and an internal power supply potential) or an intermediate potential (a potential between 0 V and the power supply potential). Preferably, it is stable at a constant value. However, it is known that the values (levels) of the power supply potential and the intermediate potential fluctuate due to various factors (load size, parasitic capacitance, etc.). In particular, the value of the intermediate potential generated by the potential generation circuit in the semiconductor chip easily varies depending on the driving force (charging ability) of the potential generation circuit, the size of the load, the parasitic capacitance, and the like.

Therefore, it is necessary to reduce the amount of change in the power supply potential or the intermediate potential and, if the value fluctuates, return it to its original value (constant value).

Hereinafter, as a specific example, an intermediate potential V supplied to a sense amplifier of a semiconductor memory (particularly, a DRAM) will be described.
A potential generation circuit for generating BLH (0 <VBLH <internal power supply potential) will be described below in detail.

FIG. 18 shows a conventional DRAM of the bank type.
The outline of the main part is shown.

[0007] Memory cell arrays (banks) 11A, 11
B is composed of a plurality of memory cells (dynamic memory cells) 12 arranged in an array. Word line W
L extends in the row direction on the memory cell arrays 11A and 11B, and one end thereof is connected to the row decoders 13A and 13B.
Connected to. The bit line pair BL, / BL extends in the column direction on the memory cell arrays 11A, 11B.

Peripheral circuits such as a sense amplifier (S / A) 14 and a column selection switch (SW) 15 are arranged between the memory cell arrays 11A and 11B. The sense amplifier 14 and the column selection switch 15 are shared by the memory cells of two adjacent memory cell arrays 11A and 11B.

The sense amplifier 14 is supplied with an intermediate potential VBLH generated by a VBLH generation circuit (step-down circuit) 16. This intermediate potential VBLH is applied to sense amplifier 1
4 is driven to the high level power supply potential (the low level side is ground potential). The sense amplifier 14 supplies not the internal power supply potential Vdd but the intermediate potential VBLH (0 <VBLH <V
One of the reasons for giving dd) is to reduce the power consumption required for charging and discharging the bit line because the charging and discharging of the bit line are repeated at a high frequency. However, the intermediate potential VBLH
Is too low, the sensing operation of the bit line potential cannot be performed sufficiently. Therefore, the value of the intermediate potential VBLH is set to a predetermined value capable of sufficiently performing the sensing operation and achieving low power consumption.

The bit line pair BL, / BL is connected to a data line pair (referred to as a DQ line pair) D via a column switch 15.
Q, / DQ. The DQ line pair DQ and / DQ
Write / read line pair 1 via Q buffer 17
8 is connected. The write / read line pair 18 is connected to an input / output buffer (I / O) 19.

FIG. 19 shows an example of a conventional VBLH generation circuit (step-down circuit).

Between the power supply Vdd terminal and the output node A,
P channel MOS transistor MP1 is connected. Resistors R1 and R2 are connected between the output node A and the power supply Vss terminal.
Are connected in series.

The connection point B between the resistors R1 and R2 is connected to the gate of the MOS transistor MP1 via a comparison circuit (current mirror type amplifier) OP1. Comparison circuit OP
Reference numeral 1 denotes a power supply Vdd similarly to the P-channel MOS transistor MP2 and the N-channel MOS transistor MN1 connected in series between the power supply Vdd terminal and the ground Vss terminal.
It comprises a P-channel MOS transistor MP3 and an N-channel MOS transistor MN2 connected in series between the terminal and the ground Vss terminal.

The gate and the drain of the MOS transistor MP2 are connected to each other, and the gate of the MOS transistor MN1 is connected to an input node (connection point of the resistors R1 and R2) B. Further, the gate of the MOS transistor MP3 is connected to the gate of the MOS transistor MP2,
The reference potential Vre is applied to the gate of the OS transistor MN2.
f is input. The connection point C between the MOS transistors MP3 and MN2 is connected to the gate of the MOS transistor MP1.

In the above-described VBLH generation circuit, an intermediate potential (potential at node B) is generated based on the output potential (VBLH) of output node A by resistance division. The potential of the node B is compared with the reference potential Vref. If the potential of the node B is lower than the reference potential Vref, the output potential (potential of the node C) becomes “L” and the potential of the node B becomes the reference potential Vref.
If it is higher than ref, the output potential (potential at node C) is
It becomes "H".

That is, when VBLH is a stable value, the potential of node B becomes higher than reference potential Vref.
MOS transistor MP1 maintains the off state, and charging of node A is prohibited. On the other hand, when VBLH is lower than the stable value, the potential of the node B becomes equal to the reference potential V
ref, the MOS transistor MP1
Is turned on, and the node A is charged.

The VBLH generation circuit shown in FIG. 19 is a so-called feedback type charging circuit having a function of constantly monitoring the value of VBLH and returning the value of VBLH to a stable value when the value of VBLH fluctuates (decreases). The feedback-type charging circuit has, for example, a structure in which the ground potential Vss is applied to the gate shown in FIG. 22 and a VBLH compared to a forced-charging-type charging circuit including only a P-channel MOS transistor connected between a power supply terminal and a charging node. Is very excellent in maintaining a constant value (stable value).

In the above description, for simplicity, the MO
Although the description is made digitally, such as turning on / off the S transistor (presence / absence of charging), the V transistor shown in FIG.
In the BLH generation circuit, the charging capability is changed in an analog manner by the gate potential (depending on the value of VBLH) of the MOS transistor MP1.

In the VBLH generation circuit of FIG. 19, the current value of VBLH is monitored, and based on this, the node A
Is provided with a feedback path for controlling the charging of the battery.
When the value of VBLH changes, VBLH enters an oscillation state. Therefore, in order to prevent the oscillation phenomenon of VBLH, the response of the feedback path is set to low speed in the VBLH generation circuit of FIG.

For this reason, in the VBLH generation circuit of FIG. 19, the time for feeding back the value of VBLH is delayed. For example, after the value of VBLH decreases, charging for returning the value of VBLH to a stable value is started. By a long time is needed.

By the way, in the DRAM of FIG.
At the time of reading or writing data, the access operation to the memory cells of the memory cell arrays 11A and 11B is performed continuously or intermittently. That is, the frequency of access to the memory cell arrays 11A and 11B is not constant, and may be high or low. Accordingly, the frequency of charging and discharging the bit line pair BL and / BL, that is, the frequency of activating the sense amplifier 14 is not constant.

Therefore, for example, in the access operation in the case where a plurality of access operations are continuously performed on the memory cells of the memory cell arrays 11A and 11B in FIG. 18, the sense amplifier 14 is frequently activated. , VB
Since the value of LH continues to be lower than the stable value, FIG.
VBLH generation circuit is always charging output node A. That is, in such a case, FIG.
Even if the response of the feedback path of the VBLH generation circuit is slow, no problem occurs in the charging operation.

However, for example, in a case where a plurality of access operations are performed intermittently with respect to the memory cells of the memory cell arrays 11A and 11B in FIG. Is maintained at a stable value, and the VBLH generation circuit in FIG. 19 is in a stable state (a state in which the output node A is not charged).
That is, in such a case, if the response of the feedback path of the VBLH generation circuit in FIG. 19 is slow, as shown in FIG. 20, when the first access operation is performed and the sense amplifier 14 is activated, Even though the value of VBLH drops sharply, charging is not performed, so that there is a problem that the value of VBLH drops significantly.

FIG. 20 is based on the premise that there are four circuits of FIG. 18, each of which is a block.
Each of the four blocks can perform an access operation independently and has its own sense amplifier. It is assumed that the word lines WL1 to WL4 exist in different blocks. However, the VBLH generation circuit is
It is common to the sense amplifiers of the four blocks.

By the way, there is a VBLH generation circuit 16 which can change the charging capability in a large range as shown in FIG. 21, although it does not solve the above problem. The VBLH generation circuit in FIG. 21 is obtained by adding a pulse circuit 20 and a P-channel MOS transistor MP4 for charging to the VBLH generation circuit in FIG.

However, the VBLH generation circuit shown in FIG. 21 uses the access frequency to the memory cells of the memory cell arrays 11A and 11B shown in FIG. 18, specifically, the first access after a continuous access operation or after a certain period of intermittent operation. Since the charging ability is not changed based on the operation, the above-mentioned problem cannot be solved.

[0027]

As described above, conventionally,
A semiconductor circuit whose frequency of activation (operation) changes,
For example, when applying an intermediate potential to the sense amplifier,
Since the potential generation circuit continues the charging operation in an intermediate operation period when the semiconductor circuit is continuously operating (including a case where the semiconductor circuit has a non-operation period shorter than a certain period), The value (level) of the intermediate potential does not decrease significantly.

However, in the case where the semiconductor circuit enters the operating state for the first time after maintaining the non-operating state for a certain period, the value of the intermediate potential given to the semiconductor circuit maintains the stable value. , Potential generation circuit is also in a stable state (non-charged state)
It has become. Therefore, in such a case, immediately after the semiconductor circuit enters the operating state for the first time, charging is not performed despite the rapid decrease in the value of the intermediate potential, so that the value of the intermediate potential is large. descend.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a potential generating circuit for applying an intermediate potential to a semiconductor circuit whose active state (operating state) changes in frequency. It detects whether the non-operating period of the semiconductor circuit is longer than or equal to a predetermined period, and if the period is longer than the predetermined period, the charging capability of the potential generating circuit in the first operating state after the non-operating period is increased (immediately. Charging is performed), and when the charging time is less than a predetermined period, normal feedback-type charging is performed as it is so that a stable intermediate potential can be always generated.

[0030]

According to the present invention, there is provided a potential generating circuit for generating an intermediate potential, applying the intermediate potential to a semiconductor circuit via an output node, and a non-operating period of the semiconductor circuit. And a second charging circuit for detecting whether or not the output node is longer than a predetermined period, and determining whether to forcibly charge the output node based on the detection result.

The first charging circuit is a feedback type charging circuit that changes the charging capability of the output node according to the value of the intermediate potential. The responsiveness of the feedback type charging circuit is set to such an extent that the value of the intermediate potential does not enter an oscillation state.

The second charging circuit forcibly charges the output node during a first operation period of the semiconductor circuit after the non-operation period when the non-operation period of the semiconductor circuit is equal to or longer than the predetermined period. .

The fixed period is a period from when the semiconductor circuit enters a non-operating state to when the intermediate potential becomes a stable value by the first charging circuit and charging by the first charging circuit is not performed. .

[0034] The potential generation circuit of the present invention further comprises a determination circuit for determining whether or not the value of the intermediate potential is higher than a stable value. Otherwise, charging of the output node during the first operation period is prohibited.

When the non-operation period of the semiconductor circuit is equal to or longer than the predetermined period, the first operation of the semiconductor circuit after the non-operation period is an initial operation, and the non-operation period of the semiconductor circuit is the predetermined period. If the period is less than the above, the operation when the non-operation period and the operation period of the semiconductor circuit are repeated is a continuous operation.

The second charging circuit includes a timer for determining the predetermined period, a logic circuit for determining whether a non-operation period of the semiconductor circuit is equal to or longer than the predetermined period, and a non-operation period of the semiconductor circuit. A pulse width adjustment circuit that generates a pulse signal for determining the degree of charging of the output node when the period is equal to or longer than the predetermined period, and a transistor that charges the output node based on the pulse signal.

The timer is a counter or a shift register that operates in synchronization with a clock signal. The timer includes at least one flip-flop circuit. The timer may include a ring oscillator and a circuit that counts an output of the ring oscillator.

The timer is initialized when the power is turned on. The timer is initialized when the semiconductor circuit enters an operating state.

The timer is constituted by an inverter delay circuit. The degree of charging of the output node is determined by at least one of a pulse width and a magnitude of the pulse signal as a control voltage of the transistor, or a channel width and a channel length of the transistor. The semiconductor circuit is a sense amplifier used for a semiconductor memory.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a potential generating circuit according to the present invention will be described in detail with reference to the drawings.

In the potential generation circuit of the present invention, the frequency of activation of the semiconductor circuit receiving the supply of the potential (for example, in the case of a sense amplifier, it is equal to the access frequency of the memory cell)
Is detected, and the ability to charge a node for supplying a potential to the semiconductor circuit is changed in accordance with the frequency of activation of the semiconductor circuit.

Specifically, it is detected whether the non-operation period (inactivation period) of the semiconductor circuit is longer than or equal to a predetermined period, and if the non-operation period is longer than the predetermined period, after the non-operation period, The charging capability of the potential generation circuit in the initial operation state is increased (so that charging is performed immediately), and when the non-operation period is less than a certain period (in the case of continuous operation), the normal operation by the potential generation circuit is performed. The charging is performed as it is.

The potential generation circuit according to the present invention has such features, and includes a DRAM, an SRAM, a non-volatile semiconductor memory, an ASIC (an ASIC incorporating a memory and an ASIC including a memory).
And the like), a system LSI, a microprocessor, and the like.

However, hereinafter, a case where a potential is supplied to a sense amplifier of a DRAM using the potential generation circuit of the present invention will be described as a typical example.

[First Embodiment] FIG. 1 schematically shows a main part of a bank type DRAM to which a potential generating circuit according to the present invention is applied.

Memory cell arrays (banks) 11A, 11
B is composed of a plurality of memory cells (dynamic memory cells) 12 arranged in an array. Word line W
L extends in the row direction on the memory cell arrays 11A and 11B, and one end thereof is connected to the row decoders 13A and 13B.
Connected to. The bit line pair BL, / BL extends in the column direction on the memory cell arrays 11A, 11B.

Peripheral circuits such as a sense amplifier (S / A) 14 and a column selection switch (SW) 15 are arranged between the memory cell arrays 11A and 11B. The sense amplifier 14 and the column selection switch 15 are shared by the memory cells of two adjacent memory cell arrays 11A and 11B.

The sense amplifier 14 is supplied with the intermediate potential VBLH generated by the VBLH generation circuit 16.
The intermediate potential VBLH is a high-level power supply potential for driving the sense amplifier 14 (the low-level side is a ground potential). The sense amplifier 14 is supplied with an intermediate potential VBLH (0 <VBLH <Vdd) instead of the internal power supply potential Vdd. The reason for this is, as described above, that the charging and discharging of the bit line is repeated at a high frequency, and thus the power consumption required for the charging and discharging of the bit line is reduced. However, if the intermediate potential VBLH is too low, the bit line potential sensing operation cannot be performed sufficiently.
Is set to a predetermined value capable of sufficiently performing the sensing operation and achieving low power consumption.

The bit line pair BL, / BL is connected via a column switch 15 to a data line pair (referred to as a DQ line pair) D
Q, / DQ. The DQ line pair DQ and / DQ
Write / read line pair 1 via Q buffer 17
8 is connected. The write / read line pair 18 is connected to an input / output buffer (I / O) 19.

FIG. 2 shows details of a peripheral circuit section surrounded by a broken line 22 in FIG. In this example, the bit line pair BL, /
The layout of the BL is of a folded type and a shared sense amplifier type.

For one sense amplifier 14, a plurality of bit line pairs (two bit line pairs in this example) BL, / B
L is connected. Bit line pairs BL and / BL have bit line isolation N-channel MOS transistors MN3L and MN
3R is connected. The control signal φ is input to the gate of the MOS transistor MN3L.
The control signal / φ is input to the gate of N3R. That is, only one bit line pair is electrically connected to the sense amplifier. Note that / φ is an inverted signal of φ.

A sense amplifier 14 is provided between the bit line isolation N-channel MOS transistors MN3L and MN3R.
The column switch 15 and the equalizing circuit 23 are arranged. The sense amplifier 14 includes a flip-flop connected CMOS inverter.

The column switch 15 is an N-channel MOS
It comprises transistors MN5 and MN6, and is connected to a data line pair (DQ line pair) DQ and / DQ. The gates of the MOS transistors MN5 and MN6 forming the column switch 15 are connected to a column select line CSLi. The equalizing circuit 23 includes an N-channel MOS transistor M
When the control signal EQ is at "H", the potentials of the bit line pair BL and / BL are made equal to each other.

FIG. 3 shows a VBLH generation circuit (step-down circuit) according to the present invention.

The VBLH generation circuit of this embodiment constantly monitors the level of VBLH supplied to the sense amplifier,
When the level of VBLH decreases, VBLH
Of the so-called feedback-type potential generating circuit for returning the level of the signal to a stable value.

Between the power supply Vdd terminal and the output node A,
P channel MOS transistor MP1 is connected. Resistors R1 and R2 are connected between the output node A and the power supply Vss terminal.
Is connected. Resistance R1, R2
Is composed of a resistance element, for example, an element utilizing the channel resistance of a MOS transistor.

The connection point B between the resistors R1 and R2 is connected to the gate of the MOS transistor MP1 via a comparison circuit (current mirror type amplifier) OP1. Comparison circuit OP
Reference numeral 1 denotes a power supply Vdd similarly to the P-channel MOS transistor MP2 and the N-channel MOS transistor MN1 connected in series between the power supply Vdd terminal and the ground Vss terminal.
It comprises a P-channel MOS transistor MP3 and an N-channel MOS transistor MN2 connected in series between the terminal and the ground Vss terminal.

The gate and drain of MOS transistor MP2 are connected to each other, and the gate of MOS transistor MN1 is connected to an input node (connection point of resistors R1 and R2) B. Further, the gate of the MOS transistor MP3 is connected to the gate of the MOS transistor MP2,
The reference potential Vre is applied to the gate of the OS transistor MN2.
f is input. The connection point C between the MOS transistors MP3 and MN2 is connected to the gate of the MOS transistor MP1.

Further, in the VBLH generation circuit of this embodiment, the auxiliary charging circuit 21 is connected to the output node A. The charging circuit 21 does not normally perform the charging operation, and performs the charging operation only in special cases.

More specifically, the charging circuit 21 detects whether the non-operation period (inactivation period) of the sense amplifier is longer than or equal to a predetermined period, and determines whether the non-operation period of the sense amplifier is longer than a predetermined period. After the non-operation period, the output node A is forcibly charged during the first operation period of the sense amplifier. on the other hand,
When the non-operating period of the sense amplifier is shorter than the fixed period (in the case of continuous operation), the charging circuit 21 does not perform the charging operation, and performs only the normal charging operation by the feedback-type potential generation circuit.

FIG. 4 shows a specific example of the charging circuit 21 of FIG. The main part of the charging circuit of this example is a counter (or shift register) 24 for determining a fixed period, and a NAN for determining whether or not the non-operating period of the sense amplifier is longer than a fixed period.
When the non-operating period of the D circuit NA1 and the sense amplifier is equal to or longer than a predetermined period, the pulse width adjusting circuit 25 that generates a pulse signal that determines the degree of charging of the output node A, and the output node A
And a P-channel MOS transistor MP4 for executing the charging of.

There are a plurality of counters 24 (in this example, 2
) D (delay) type flip-flop circuit FF
1 and FF2. In this example, a certain period (non-operating period of the sense amplifier) serving as a criterion for determining whether to perform forced charging can be determined based on the number of flip-flop circuits FF1 and FF2 connected in series.

It is to be noted that the certain period as a criterion for determining whether or not to perform forced charging can be naturally determined by means other than the value of the counter or the number of flip-flop circuits.

For example, the fixed period may be determined using a ring oscillator and a circuit for counting its output. In other words, a timer that can take a time in a broad sense can easily determine a certain period as a criterion for determining whether to perform forced charging.

The control signal SAac is supplied to the NOR circuit NR1.
t and PowerOn are input. Control signal Power
On is, for example, a signal which goes to “H” level when the power of the system is turned on and an external power supply potential is applied to the memory chip. The control signal SAact is used when, for example, a memory cell is accessed and the sense amplifier is turned on. Is an "H" level signal when is activated.

After the output signal of the NOR circuit NR1 passes through the inverters I1 and I2, its level is inverted.
The signal is input to the reset terminal R of the flip-flop circuit FF1. The output signal of the NOR circuit NR1 is input to the NOR circuit NR2 via the inverters I1, I2, and I3. The clock signal CLOCK is input to the NOR circuit NR2 via the inverter I4.

The output signal of the NOR circuit NR2 is input to the clock terminal CP of the flip-flop circuit FF1 via the inverter I5. Flip-flop circuit FF
The output signal Q1 is output from one output terminal Q.

The clock signal CLOCK is output from the inverter I
After that, the signal is input to the clock terminal CP of the flip-flop circuit FF2. The control signal PowerOn is
After passing through the inverter I7, its level is inverted and input to the reset terminal R of the flip-flop circuit FF2. Output signal Q1 of flip-flop circuit FF1
Is input to the input terminal D of the flip-flop circuit FF2. An output signal Q2 is output from an output terminal Q of the flip-flop circuit FF2.

The control signal SAa is supplied to the NAND circuit NA1.
ct and the output signal Q2 of the flip-flop circuit FF2 are input. That is, when the control signal SAact is at the “H” level, an inverted signal of the output signal Q2 is input to the pulse width adjustment circuit 25.

The pulse width adjusting circuit 25 includes a NAND circuit N
A pulse signal CP having a predetermined width (the period of “L” is a predetermined width) is generated based on the output signal of A1.
Is applied to the gate of P-channel MOS transistor MP4 for charging.

The pulse width adjusting circuit 25 can be composed of, for example, a circuit as shown in FIG. In this circuit, when the level of the input signal (output signal of the NAND circuit NA1) a changes from “L” to “H”, the pulse signal (CP) having a pulse width corresponding to the delay time determined by the odd number of inverters 26 d is generated. The degree of forced charging can be adjusted by the pulse width of the pulse signal (CP) d,
The pulse width can be determined by the number of inverters 26. The operation waveform of the circuit of FIG. 5 is as shown in FIG.

While the pulse signal CP generated by the pulse width adjusting circuit 25 is being input to the gate of the P-channel MOS transistor MP4, that is, while the gate of the MOS transistor MP4 is at the "L" level, VB
The output node A of the LH generation circuit is forcibly charged.

As described above, V is used to supply a potential to the sense amplifier of the DRAM as shown in FIGS.
The BLH generation circuit includes a new charging circuit for forced charging that performs a charging operation only at a specific time, in addition to a normal feedback-type charging circuit. That is, the charging circuit includes a timer (in this example, a counter or a flip-flop circuit) for detecting whether the non-operation period (inactivation period) of the sense amplifier is longer than or equal to a predetermined period,
It is determined whether the current operation of the sense amplifier is an initial operation or a continuous operation.

In the initial operation, the feedback type charging circuit is in a stable state (non-charging state), and the charging operation by the feedback type charging circuit set so that the response is slow is insufficient. Forced charging by the forced charging circuit according to the present invention is performed, and VB
It prevents an extreme drop in the level of LH. In the case of continuous operation, since the feedback-type charging circuit continues to perform the charging operation, the forced charging by the forced charging circuit according to the present invention is unnecessary, and the forced charging is not performed.

Accordingly, for example, as shown in FIGS. 8 and 9, the frequency at which the sense amplifier is activated (access frequency)
Irrespective of the potential VBLH supplied to the sense amplifier
Can be maintained at a value close to the stable value.
M can contribute to the stable operation.

Note that the initial operation refers to the operation of the sense amplifier that is performed first after the non-operation period when the non-operation period (non-access period to the memory cell) of the sense amplifier is longer than a certain period. The continuous operation means that the non-operating period and the operating period are repeated when the non-operating period of the sense amplifier (the non-access period to the memory cell) is shorter than a certain period (always when the sense amplifier is in the operating state). Including some cases).

Here, the certain period is a period in which the value (level) of VBLH is settled to a stable value after the sense amplifier is deactivated (inactive), and the VBLH generation circuit is in a stable state (non-charged state). The period until it becomes.

Next, the operation of the VBLH generation circuit according to the present invention will be described.

FIG. 6 shows operation waveforms of the charging circuit 21 shown in FIGS.

Non-Continuous Access Operation (FIG. 6A) As a precondition, a case where the non-operation period of the sense amplifier is equal to or longer than one clock (a certain period) is referred to as a non-continuous access operation.

First, the control signal PowerOn goes high in synchronization with the clock signal CLOCK, and the flip-flop circuits FF1 and FF2 are initialized. Thereafter, control signal SAac for activating the sense amplifier
t becomes "H" level. The control signal PowerO
The first access operation A (when the control signal SAact is at the “H” level) after n becomes the “H” level is treated as a continuous operation in principle.

The reason is that after the power is turned on (Pow
This is because the access operation is generally performed immediately after erOn becomes “H”), and at this time, the charging operation is being performed by the feedback-type charging circuit. However, after a predetermined period has elapsed since the power was turned on, V
Even if the BLH generation circuit is in a stable state, if the first access operation is not yet performed, the first access operation is treated as an initial operation, and the forced charging according to the present invention is performed.

After the first access operation is performed, a non-access period (a non-operation period of the sense amplifier) for a certain period is set. In this example, the non-access period is equal to or longer than one clock, and is a time sufficient for the VBLH generation circuit to be in a stable state (non-charged state).

Here, the clock signal CLOCK becomes "H".
After the first access operation (period A) is performed and the clock signal CLOCK goes to the “H” level (period B), the control signal SAact becomes:
This is the “L” level. At this time, the output signal of the NOR circuit NR1 becomes “H” level, and the two input signals of the NOR circuit NR2 both become “L” level.

Therefore, the level of the input terminal CP of the flip-flop circuit FF1 becomes "L", and the output signal Q1 of the flip-flop circuit FF1 changes from "L" level to "H" level. After this, the clock signal CLOC
At the negative edge of K, the output signal Q1 of the flip-flop FF1 at that time is
It is transmitted to F2. That is, when the clock signal CLOCK changes from “H” level to “L” level, the output signal Q2 of the flip-flop circuit FF2 changes from “L” level to “H” level.

Then, after that, the clock signal CLOCK
When the control signal SAact goes to the “H” level in synchronism with “1”, both of the two input signals of the NAND circuit NA1 become “H”.
Therefore, the output signal of the NAND circuit NA1 (the input signal of the pulse width adjusting circuit 25) changes from “H” level to “L” level.
Change to a level. That is, this access operation is determined by the charging circuit to be an initial operation.

By the way, at the time point when the control signal SAact becomes “H” level, the flip-flop circuit FF1
Initialized, the output signal Q1 goes to "L" level. After this, the control clock (clock signal CLO)
At the negative edge of (CK), the output signal Q1 of the flip-flop FF1 at that time is transmitted to the flip-flop circuit FF2.

That is, when the clock signal CLOCK changes from "H" level to "L" level, the output signal Q2 of the flip-flop circuit FF2 changes from "H" level to "L" level.
Change to a level. Then, the output signal of NAND circuit NA1 (the input signal of pulse width adjustment circuit 25) changes from "L" level to "H" level.

The input signal of the pulse width adjustment circuit 25 is "L"
When the level changes from the “H” level to the “H” level, as shown in FIGS. 5 and 7, the pulse width adjustment circuit 25 outputs a pulse signal CP (charge p) having a predetermined width (the “L” period is a predetermined width).
ulse) is output.

This pulse signal CP is input to the gate of P-channel MOS transistor MP4 in FIG.
In the access operation (initial operation) during the period C in which the clock signal CLOCK is at the “H” level, the sense amplifier is activated and the node A that supplies VBLH to the sense amplifier is forcibly charged.

The degree of forced charging of node A is controlled by the pulse width and magnitude of pulse signal CP. When the control signal SAact becomes “H”, the counter 24, that is, the flip-flop circuit is initialized, and prepares for the next operation (detection of a non-operation period).

When the control signal SAact is at the "L" level during the period C in which the clock signal CLOCK is at the "H" level, the pulse signal CP (charge pulse)
e) is not output (CP always
"H"), since the non-operation period of the sense amplifier is continued, the output signal Q of the flip-flop circuit FF1 is again output.
1 becomes "H" level.

Continuous Access Operation (FIG. 6B) As a prerequisite, continuous access is performed when the access operation is performed every clock, that is, when the non-operating period of the sense amplifier is less than one clock (constant period). Let's call it action.

First, the control signal PowerOn goes high in synchronization with the clock signal CLOCK, and the flip-flop circuits FF1 and FF2 are initialized. Thereafter, control signal SAac for activating the sense amplifier
t becomes "H" level. Here, the control signal SAact
Goes high at each clock in synchronization with the clock signal CLOCK.

In this case, when the clock signal CLOCK is at the “H” level, the control signal SAact does not go to the “L” level, so that the output signal of the NOR circuit NR2 does not go to the “H” level.

Therefore, the flip-flop circuits FF1, F
The output signals Q1 and Q2 of F2 are always at the “L” level, and the pulse signal CP is not output from the pulse width adjustment circuit 25. That is, in the continuous access operation, the forced charging is not performed.

In the above-described operation example, forcible charging is performed when the interval for sensing the level of the bit line pair, that is, when the non-operating period of the sense amplifier is one clock cycle or more. Flip-flop circuits FF1, F
By increasing or decreasing the number of F2, it is possible to adjust a certain period as a criterion for determining whether to perform forced charging.

For example, in the charging circuit shown in FIG. 4, if the number of flip-flop circuits is set to three, the interval for sensing the potential (level) of the bit line pair, that is, the non-operating period of the sense amplifier is two clock cycles or more. In this case, forced charging is performed (see FIGS. 16 and 23).

FIGS. 8 and 9 show the effect when the potential generation circuit (VBLH generation circuit) according to the present invention is used.

For example, the memory cell array 11A of FIG.
In the first access operation after a non-access for a certain period when the non-continuous access operation is performed on the memory cell of 11B, the value of VBLH maintains a stable value, and VBH of FIG.
The LH generation circuit is in a stable state (a state in which the output node A is not charged). Further, as described above, FIG.
Is set such that the response of the feedback path is slow.

Here, conventionally, as shown in FIG. 8 and FIG. 9, when the first access operation is performed after the non-access for a certain period and the sense amplifier 14 is activated, the VBL
Despite the rapid decrease in the value of H, no charging is performed, so the value of VBLH drops significantly.

On the other hand, in the present invention, as shown in FIGS. 8 and 9, the first access operation is performed after a certain period of non-access and the sense amplifier 14 is activated.
Since the forced charging circuit ("21" in FIG. 3) immediately starts the charging operation, the value of VBLH does not extremely decrease even if the response of the feedback path of the VBLH generation circuit is slow.

FIG. 9 is based on the premise that there are four circuits of FIG. 1, each of which is a block.
Each of the four blocks can perform an access operation independently and has its own sense amplifier. It is assumed that the word lines WL1 to WL4 exist in different blocks. However, the VBLH generation circuit is
It is common to the sense amplifiers of the four blocks.

As described above, according to the potential generation circuit according to the first embodiment of the present invention, it is detected whether the non-operating period of the semiconductor circuit is equal to or longer than a predetermined period, and the non-operating period of the semiconductor circuit is determined. When the operation period is longer than a certain period, after the non-operation period, the charging capacity of the potential generation circuit when the operation is first performed is increased (so that charging is performed immediately), and the non-operation period of the semiconductor circuit is constant. If the period is less than the period, normal charging is performed as it is, so that a stable intermediate potential can always be generated.

[Second Embodiment] Next, a potential generation circuit according to a second embodiment of the present invention will be described. The potential generating circuit according to this embodiment is characterized by a specific configuration of a forced charging circuit. The configuration of the potential generation circuit is, for example, a feedback type as shown in FIG.

FIG. 10 shows a specific example of a charging circuit according to the present invention. This charging circuit uses the control signal SA without using the clock signal (basic clock) CLOCK.
Only by act, for example, it is detected whether or not the non-operation period of the sense amplifier is longer than or equal to a predetermined period, and it is determined whether or not to perform forced charging based on the detection result.

The charging circuit of this embodiment includes an inverter delay circuit 27 for determining a fixed period and a logic circuit (NAND) for determining whether the non-operating period of the sense amplifier is longer than a fixed period.
Circuit NA2). Specifically, the control signal SAact includes four inverters I8, I9, I10,
After passing through I11, it is input to the NOR circuit NR3, and after passing through two inverters I8 and I9, NO
The signal is input to the R circuit NR3. The output signal a of the NOR circuit NR3 and the control signal SAact (= b)
The signal is input to the ND circuit NA2.

The output signal c of the NAND circuit NA2 is input to the pulse width adjustment circuit 25,
Generates a pulse signal CP (= d) based on the output signal c. Note that the pulse width adjustment circuit 25 is, for example, as shown in FIG.
And operates according to operation waveforms as shown in FIG.

The output signal CP of the pulse width adjusting circuit 25 (=
d) is input to the gate of the P-channel MOS transistor MP4. The pulse signal ("L" level) is MOS
While the signal is being input to the gate of the transistor MP4, the charging circuit performs forcible charging on the output node A.

FIG. 11 shows a specific example of the inverter of FIG. This inverter includes a P-channel MOS transistor MP5 and an N-channel MOS transistor MN
7, a resistor R and a capacitor C. The RC circuit composed of the resistor R and the capacitor C has a time constant and is provided for the purpose of adjusting the timing of the inverter delay circuit 27.

Next, referring to the operation waveforms of FIG.
The operation of the charging circuit of FIG. 10 will be described.

While the control signal SAact is "H", the sense amplifier is in the operating state, and while the control signal SAact is "L", the sense amplifier is in the non-operating state.

First, it is assumed that the non-operation period of the sense amplifier is P1, and this period P1 is shorter than a fixed period X determined by the inverters I8, I9, I10, I11 in the charging circuit 21 shown in FIG. I do. In this case, even if the control signal SAact changes from “H” → “L” → “H”,
This change does not change the output signal a of the NOR circuit NR3. That is, if the period of SAact = “L” is shorter than the fixed period X, the inverters I8 and I8 in FIG.
9, I10, I11, the NOR circuit NR
Therefore, the output signal a of the NOR circuit NR3 maintains the "L" level because both of the two input signals No. 3 and "3" do not go to the "L" level.

Therefore, when the control signal SAact changes from "L" level to "H" level, the signal "a" becomes "L" level.
Level, the output signal c of the NAND circuit NA2
Remain at the “H” level. That is, since the input signal c of the pulse width adjustment circuit 25 remains at the “H” level, the pulse signal (CP) d is not output from the pulse width adjustment circuit 25, and the forced charging is not performed.

Next, if the non-operating period of the sense amplifier is P2, and this period P2 is longer than a fixed period X determined by the inverters I8, I9, I10 and I11 in the charging circuit 21 shown in FIG. Assume. In this case, when the control signal SAact changes from “H” → “L” → “H”,
After the control signal SAact changes from “H” level to “L” level, when a certain period X has elapsed, the output signal “a” of the NOR circuit NR3 changes from “L” level to “H” level.

Then, the output signal a of the NOR circuit NR3
Maintains the "H" level after the control signal SAact changes from the "L" level to the "H" level until the delay time Y determined by the inverters I8 and I9 in FIG. 10 elapses. After the lapse of Y, the level changes from “H” level to “L” level.

Here, in the period Y, the control signal SA
act (= b) and the output signal a of the NOR circuit NR3 are
Both are at “H” level.

Therefore, in period Y, output signal c of NAND circuit NA2 is at "L" level. That is,
The pulse width adjustment circuit (for example, see FIG. 5) 25
A change in the output signal c of the D circuit NA2 from “L” to “H” is detected, and a pulse signal (CP) d having a predetermined pulse width is output.

Then, while the pulse signal (CP) d is at the "L" level, the P-channel MOS transistor MP4 is turned on, so that forced charging is performed.

As described above, according to the potential generation circuit according to the second embodiment of the present invention, like the potential generation circuit according to the first embodiment, the non-operation period of the semiconductor circuit is a fixed period. If the non-operating period of the semiconductor circuit is equal to or longer than a predetermined period, the charging capability of the potential generating circuit when the semiconductor circuit is first operated after the non-operating period is increased (immediately after the non-operating period). And when the non-operating period of the semiconductor circuit is less than a certain period, normal charging is performed as it is, so that a stable intermediate potential can be always generated.

[Third Embodiment] Next, a potential generating circuit according to a third embodiment of the present invention will be described. The potential generation circuit according to this embodiment is an improved example of the potential generation circuits according to the above-described first and second embodiments.

That is, in the present embodiment, the charging circuits shown in FIG. 4 (first embodiment) and FIG.
A determination circuit for detecting the potential of VBLH and determining whether to perform forced charging based on the detection result is newly added. This determination circuit allows forcible charging by the charging circuit when the potential of VBLH is lower than the stable value. However, when the potential of VBLH is higher than the stable value, Prohibit forced charging.

Therefore, the condition under which the forced charging is performed in the third embodiment is the first operating period of the semiconductor circuit after the non-operating period of the semiconductor circuit supplied with the potential has continued for a certain period or more, and That is, the level of the potential supplied to the semiconductor circuit is lower than the stable value.

FIG. 13 shows an example in which the charging circuit of FIG. 4 is improved. The difference between the charging circuit of this example and the charging circuit of FIG.
The input of the NAND circuit NA1 is increased by one, and a total of 3
And the increased input terminal is provided with a judgment signal J
Is entered.

When the potential of VBLH is lower than the stable value, judgment signal J is at "H" level (charge allowed).
, The operation of the charging circuit of the present example is shown in FIG.
(See FIG. 6 and the description thereof). On the other hand, when the potential of VBLH is higher than the stable value, judgment signal J is set to the “L” level (charging prohibited), so that forced charging is not performed.

FIG. 14 shows an example in which the charging circuit of FIG. 10 is improved. The difference between the charging circuit of the present embodiment and the charging circuit of FIG. 10 is that the input of the NAND circuit NA2 is increased by one to a total of three, and the determination signal J is input to the increased one input terminal. It is in the point.

When the potential of VBLH is lower than the stable value, the determination signal J is at the “H” level (charge allowed).
, The operation of the charging circuit of this example is as shown in FIG.
The operation is exactly the same as the operation of the charging circuit of 0 (see FIG. 12 and its description). On the other hand, when the potential of VBLH is higher than the stable value, judgment signal J is set to the “L” level (charging prohibited), so that forced charging is not performed.

FIG. 15 shows a specific example of the judgment circuit for generating the judgment signal J. The configuration of this determination circuit is substantially the same as, for example, the configuration of the feedback potential generation circuit shown in FIG. That is, in the potential generation circuit of FIG. 3, the charge circuit 21 and the P-channel MOS transistor MP1 are deleted, and a signal obtained by inverting the output signal of the comparison circuit (current mirror amplifier) OP1 by an inverter is referred to as a determination signal J. Fifteen determination circuits can be obtained.

However, the response of the determination circuit is, of course,
It is set to be faster than the response of the feedback path in FIG. That is, the determination circuit detects the potential (level) of VBLH, and the detection result (determination signal J)
Is required to be immediately transmitted to the forced charging circuit 21.

The operation of FIG. 15 will be briefly described.
If H is higher than the stable value, the voltage dividing circuit (resistors R1 ′, R
2 ′) (the input signal of the comparison circuit OP2) is higher than the reference potential Vref. Therefore, the output signal of the comparison circuit OP2 becomes “H” level, and the determination signal J becomes “L” level.

On the other hand, when VBLH is lower than the stable value,
The potential (input signal of the comparison circuit OP2) obtained by the voltage dividing circuit (resistors R1 ′, R2 ′) becomes lower than the reference potential Vref. Therefore, the output signal of the comparison circuit OP2 is
The signal becomes “L” level, and the determination signal J becomes “H” level.

As described above, since the forced charging circuits shown in FIGS. 4 and 10 do not feed back the potential of VBLH, the non-operating period of the semiconductor circuit is longer than a certain period regardless of the potential (level) of VBLH. In an operation period of the first semiconductor circuit in a certain case, the output node of the VBLH generation circuit is forcibly charged.

This is because, as a rule of thumb, it has been clarified that the potential of VBLH is liable to extremely decrease during the first operation period of the semiconductor circuit when the non-operation period of the semiconductor circuit is longer than a certain period. (See the description of the prior art).

However, if the potential of VBLH is larger than the stable value during the first operation period of the semiconductor circuit when the non-operation period of the semiconductor circuit is longer than a certain period for some reason, Such forced charging is not required at all.

According to the VBLH generation circuit according to this embodiment, if the potential of VBLH is rising, the operation of the first semiconductor circuit when the non-operation period of the semiconductor circuit is longer than a certain period Even during the period, since the forced charging is not performed, such unnecessary forced charging can be prohibited.

The configuration of the potential generation circuit is, for example, a feedback type as shown in FIG.

[Fourth Embodiment] Next, a potential generation circuit according to a fourth embodiment will be described. The potential generation circuit according to the present embodiment is obtained by changing the length of a certain period serving as a criterion for determining whether to perform forced charging in the potential generation circuits according to the first and second embodiments.

FIG. 16 shows a modification of the charging circuit shown in FIG. 4, in which the number of flip-flop circuits is different. In this example, since there are three flip-flop circuits, a certain period serving as a criterion for determining whether to perform forced charging is two cycles of the control clock (clock signal CLOCK). Therefore, when the non-operating period of the sense amplifier is only one clock cycle (in the case of a continuous access operation), forcibly charging the output node A during the first operating period of the sense amplifier after this non-operating period Not performed. At this time, in order to prepare for the next operation (detection of a non-operation period), the counter 24, that is, the flip-flop circuit is initialized. The operation waveform of the charging circuit in FIG. 16 is as shown in FIG.

FIG. 17 shows a modification of the charging circuit shown in FIG. 10, in which the number of inverters is different. As described above, the certain period of time as a criterion for determining whether or not to perform forced charging is based on, for example, the performance of a normal feedback-type potential generation circuit, the magnitude of the load on the semiconductor circuit to which the potential is supplied, and the like. , Can be easily changed.

[Others] In the above embodiment, an example in which the hood-back type potential generating circuit (FIG. 19) is improved has been described. However, the basic potential generating circuit is limited to the feedback type potential generating circuit of FIG. Not done. For example, a charging circuit according to the present invention may be combined with a forced charging circuit as shown in FIG.

Further, the degree of the forced charging by the charging circuit according to the present invention is controlled by the pulse width and the magnitude of the pulse signal input to the gate of the P-channel MOS transistor, but instead or together with this. For example, P
The control may be performed by changing the size (channel width, channel length) of the channel MOS transistor.

In the above-described embodiment, the VBLH generation circuit for supplying a potential to a sense amplifier has been described by taking a DRAM as an example. However, the potential generation circuit of the present invention can be applied to various semiconductor circuits. . For example, FIG.
Taking a DRAM as an example, the present invention is applied to a potential generating circuit for supplying a potential to a DQ buffer 17 for driving a DQ line pair DQ and / DQ, a potential generating circuit for supplying a potential to an I / O buffer 19, and the like. Can be applied.

The present invention is naturally applicable to memories other than DRAMs and integrated circuits other than memories.

[0144]

As described above, according to the present invention, a non-operating period of a semiconductor circuit is constant with respect to a potential generating circuit which applies an intermediate potential to a semiconductor circuit whose active state (operating state) changes in frequency. Detecting whether it is longer than or less than the period, if it is more than a certain period, after the non-operation period, raise the charging capability of the potential generation circuit when it is first in the operating state (so that charging is performed immediately), If the period is less than the predetermined period, normal feedback-type charging is performed as it is, so that a stable intermediate potential can be always generated.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing a DRAM to which a potential generation circuit of the present invention is applied.

FIG. 2 is a diagram showing details of a peripheral circuit portion of the DRAM of FIG. 1;

FIG. 3 is a diagram showing a VBLH generation circuit according to the present invention.

FIG. 4 is a diagram showing a charging circuit according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a specific example of the pulse width adjustment circuit of FIG. 4;

FIG. 6 is a diagram showing operation waveforms of the charging circuit of FIG. 4;

FIG. 7 is a diagram showing operation waveforms of the pulse width adjustment circuit in FIG. 5;

FIG. 8 shows VB when the VBLH generation circuit of the present invention is used.
The figure which shows the change of LH.

FIG. 9 shows VB when the VBLH generation circuit of the present invention is used.
The figure which shows the change of LH.

FIG. 10 is a diagram showing a charging circuit according to a second embodiment of the present invention.

FIG. 11 is a diagram showing a specific example of the inverter in FIG. 10;

FIG. 12 is a diagram showing operation waveforms of the charging circuit of FIG.

FIG. 13 is a diagram showing a charging circuit according to a third embodiment of the present invention.

FIG. 14 is a diagram showing a charging circuit according to a third embodiment of the present invention.

FIG. 15 is a diagram illustrating a specific example of a determination circuit that generates a determination signal J in FIGS. 13 and 14;

FIG. 16 is a diagram showing a charging circuit according to a fourth embodiment of the present invention.

FIG. 17 is a diagram showing a charging circuit according to a fourth embodiment of the present invention.

FIG. 18 is a view schematically showing a general DRAM.

FIG. 19 is a diagram showing a conventional VBLH generation circuit.

20 is a diagram showing V when the VBLH generation circuit shown in FIG. 19 is used;
The figure which shows the change of BLH.

FIG. 21 is a diagram showing a conventional VBLH generation circuit.

FIG. 22 is a diagram showing a conventional VBLH generation circuit.

FIG. 23 is a diagram showing operation waveforms of the charging circuit of FIG.

[Description of References] 11A, 11B: Memory cell array (bank), 12: Memory cell, 13A, 13B: Row decoder, 14: Sense amplifier, 15: Column switch, 16: VBLH generation circuit, 17: DQ buffer, 18: Write / read line pair, 19: I / O buffer, 20: pulse circuit, 21: charging circuit (forcible charging circuit), 22: peripheral circuit section, 23: equalizing circuit, 24: counter, 25: pulse width adjusting circuit, 26: Inverter train, 27: Inverter delay circuit, MP1 to MP5: P-channel MOS transistor, MN1 to MN7: N-channel MOS transistor, R1, R2: Resistive element, I1 to I12: Inverter, NR1 to NR3: NOR circuit, NA1 , NA2: NAND circuit, FF1, FF2: Flip-flop circuit, OP1, OP2: comparing circuit (current mirror type amplifier).

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Masaaki Kuwagata 1st address, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa F-term in Toshiba Microelectronics Center Co., Ltd. 5B015 JJ15 KB62 QQ10 5B024 AA03 AA15 BA09 BA27 CA07 5F038 BB04 BB08 DF01 DF05 DF06 EZ20

Claims (16)

[Claims] A first charging circuit for generating an intermediate potential and applying the intermediate potential to a semiconductor circuit via an output node;
A second charging circuit that detects whether the non-operating period of the semiconductor circuit is equal to or longer than a predetermined period, and determines whether to forcibly charge the output node based on the detection result. Potential generation circuit. 2. The potential generating circuit according to claim 1, wherein the first charging circuit is a feedback type charging circuit that changes a charging capability of the output node according to the value of the intermediate potential. 3. The potential generation circuit according to claim 2, wherein the responsiveness of the feedback type charging circuit is set to such an extent that the value of the intermediate potential does not enter an oscillation state. 4. The semiconductor device according to claim 2, wherein the second charging circuit forcibly forces the output node during an initial operation period of the semiconductor circuit after the non-operation period, when the non-operation period of the semiconductor circuit is the predetermined period or more. The battery is charged.
The potential generation circuit according to any one of the preceding claims. 5. The fixed period is a period from when the semiconductor circuit enters a non-operating state to when the intermediate potential becomes a stable value by the first charging circuit and charging by the first charging circuit is not performed. 5. The method according to claim 4, wherein
The potential generation circuit according to any one of the preceding claims. 6. The semiconductor device according to claim 1, further comprising a determination circuit configured to determine whether a value of the intermediate potential is higher than a stable value, wherein the second charging circuit determines whether the value of the intermediate potential is higher than the stable value. 5. The potential generation circuit according to claim 4, wherein charging of said output node during said first operation period is prohibited. 7. When the non-operation period of the semiconductor circuit is equal to or longer than the predetermined period, the first operation of the semiconductor circuit after the non-operation period is an initial operation, and the non-operation period of the semiconductor circuit is the When less than a certain period, the operation of the semiconductor circuit when the non-operation period and the operation period are repeated,
2. The potential generation circuit according to claim 1, wherein the operation is a continuous operation. 8. The second charging circuit includes: a timer for determining the predetermined period; a logic circuit for determining whether a non-operation period of the semiconductor circuit is equal to or longer than the predetermined period; A pulse width adjustment circuit that generates a pulse signal that determines a degree of charging of the output node when the operation period is equal to or longer than the predetermined period; and a transistor that charges the output node based on the pulse signal. The potential generation circuit according to claim 1, wherein: 9. The potential generation circuit according to claim 8, wherein the timer is a counter or a shift register that operates in synchronization with a clock signal. 10. The potential generation circuit according to claim 8, wherein said timer comprises at least one flip-flop circuit. 11. The timer comprises: a ring oscillator;
9. The potential generation circuit according to claim 8, further comprising a circuit for counting an output of said ring oscillator. 12. The potential generation circuit according to claim 9, wherein the timer is initialized when power is turned on. 13. The potential generation circuit according to claim 9, wherein the timer is initialized when the semiconductor circuit enters an operation state. 14. The potential generation circuit according to claim 8, wherein said timer is constituted by an inverter delay circuit. 15. The degree of charging of the output node is determined by at least one of a pulse width and a magnitude of the pulse signal as a control voltage of the transistor, or a channel width and a channel length of the transistor. 9. The potential generation circuit according to claim 8, wherein: 16. The semiconductor circuit according to claim 1, wherein said semiconductor circuit is a sense amplifier used in a semiconductor memory.
The potential generation circuit according to any one of the preceding claims.