JP2002007202A - Semiconductor storage device and adjusting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device and its adjusting method which can adjust differences in output time among pieces of data outputted from input/output terminals to be less than a reference value. SOLUTION: A phase comparing circuit 9 is connected to equal loads by pads 11 and 12 and wires 17 and 18, and the phase of the data outputted to the pad 11 is compared with the phase of the data outputted to the pad 12. Then the comparison result is outputted to a delay signal generating circuit 10. The delay signal generating circuit 10 outputs a delay signal SDL to a delay circuit 8, until the output signal of the phase comparing circuit 9 is switched from level L to level H and the delay circuit 8 delays the data according to the delay signal SDL. The delay signal generating circuit 10 outputs a delay fixation signal SDLC to the delay circuit 8 once the output signal of the phase comparing circuit 9 is switched from level L to level H, and the delay circuit 8 fixes the delay quantity according to the delay fixation signal SDLC.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device for adjusting an output time difference between data output from a plurality of input / output terminals to a reference value and a method of adjusting the same.

[0002]

2. Description of the Related Art A semiconductor memory device has a clock generator and a synchronous DRA for inputting and outputting data in synchronization with a reference clock generated in the clock generator.
There is M. A DDR (Dou) that inputs and outputs data at both the rising and falling timings of the reference clock.
ble Data Rate) -DRAM and Rambus D
There is a RAM.

In a DDR-DRAM, 100 MH
Data is exchanged with a device outside the DRAM at a frequency of about z.

A Rambus DRAM exchanges data with a memory chip including a plurality of memory cells and a peripheral circuit such as an input / output interface circuit for inputting / outputting data to / from the plurality of memory cells, and a device outside the DRAM. Are manufactured separately from the interface circuit that performs the operation. Then, between the memory chip and the interface circuit, 5
Data is input and output at a frequency of about 00 MHz, and DRA
800 MH between the device outside M and the interface circuit
Data is exchanged at a high frequency of 1 GHz from z.

[0005]

However, DDR-DR
In an AM or Rambus DRAM, an output control clock circuit that controls data output timing based on a reference clock is not always connected equidistant from two adjacent input / output terminals.
There is a problem that data output from each input / output terminal of a DRAM or a Rambus DRAM has an output time difference.

Particularly, in a Rambus DRAM, data exchange between an interface circuit and a device outside the DRAM is performed at a high frequency of 800 MHz to 1 GHz, so that a deviation in data output timing between input and output terminals is a serious problem.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor device capable of adjusting an output time difference between data output from a plurality of input / output terminals to be within a reference value. An object of the present invention is to provide a storage device and a method of adjusting the storage device.

[0008]

A semiconductor memory device according to the present invention comprises a plurality of input / output terminals, an interface circuit for outputting data read from a memory cell array to the input / output terminals based on a reference clock, and an interface circuit. A test mode recognizing circuit for activating a test mode signal in response to an entry of a test mode via the first and second input / output terminals arbitrarily selected from a plurality of input / output terminals in response to activation of the test mode signal And an adjustment circuit for adjusting an output time difference between first and second data output from the first and second input / output terminals, respectively, wherein the adjustment circuit comprises a first and a second input / output terminal.
, An output time difference of the first data with respect to the second data is detected from the input / output terminals under the same load condition, and based on the detected output time difference, the output time difference of the first data with respect to the second data is set as a reference. Delay the first data to be within the value.

In the semiconductor memory device according to the present invention, at the time of testing, adjacent first and second input / output terminals arbitrarily selected from a plurality of input / output terminals are output from the second input / output terminal. An output time difference of the first data output from the first input / output terminal for the second data is detected under the same load condition as the first and second input / output terminals. Then, the first data is delayed based on the detected output time difference, and the first data is adjusted so that the output time difference of the first data with respect to the second data is within the reference value. The interface circuit is an input / output interface circuit in the case of a DDR-DRAM, and an interface logic circuit in the case of a Rambus DRAM.

Therefore, a semiconductor memory device which outputs data from a plurality of input / output terminals at almost the same timing can be manufactured.

Further, since an output time difference between two data is detected from two adjacent input / output terminals under an equal load condition, an accurate output time difference can be detected. As a result, the output timing of data from the plurality of input / output terminals in the semiconductor memory device can be accurately adjusted.

Preferably, the adjustment circuit comprises a first and a second
A phase comparison circuit that is connected to the input / output terminal and the equal load and compares the phase of the first data with the phase of the second data; and that the comparison result from the phase comparison circuit is changed from the first logic to the second logic. And a delay circuit for delaying the first data until switching.

In the adjusting circuit, the phase of the first data is compared with the phase of the second data, and the first data is delayed until the comparison result switches from the first logic to the second logic. Is adjusted so that the output time difference between the first data and the second data is within the reference value. That is, of the two data output from the two adjacent input / output terminals, the data whose phase is advanced is delayed until the phase relation is switched with respect to the data whose phase is delayed, and the output time difference between the two data is delayed. Is adjusted to be within the reference value.

Therefore, the output time difference can be easily adjusted to be within the reference value by detecting a change in the phase difference between two data output from two adjacent input / output terminals.

Preferably, the adjustment circuit further includes a delay signal generation circuit for generating a delay signal or a delay fixed signal based on a comparison result of the phase comparison circuit, wherein the delay signal generation circuit determines that the comparison result is from the first logic to the first logic. A delay signal is generated until the logic is switched to the second logic, and when the comparison result switches from the first logic to the second logic, a delay fixed signal is generated, and the delay circuit delays the first data based on the delay signal. Then, the delay amount of the first data is fixed based on the delay fixing signal.

In the adjustment circuit, a delay signal is generated until the comparison result of comparing the phase of the first data with the phase of the second data switches from the first logic to the second logic, Is delayed. Then, when the comparison result switches from the first logic to the second logic, a delay fixed signal is generated, and the delay amount of the first data is fixed.

Therefore, by delaying the first data until the comparison result in the phase comparison circuit switches from the first logic to the second logic, the first data for the second data is delayed.
Can be adjusted so that the output time difference of the data is within the reference value.

Preferably, the delay circuit includes a plurality of delay elements for delaying the first data, and a plurality of fuses for selectively activating the plurality of delay elements, and the plurality of fuses are trimmed by the plurality of fuses. Are selectively activated to fix the delay amount of the first data.

In the delay circuit, when a delay fixed signal is input, a part of the plurality of fuses is turned off, and the remaining fuses are turned on to selectively activate the plurality of delay elements. Then, the delay amount of the first data is fixed.

Therefore, the delay amount of the first data can be reliably fixed by turning off some of the plurality of fuses.

Preferably, the phase comparison circuit of the adjustment circuit is provided in the dicing section. The phase comparison circuit is provided in the dicing unit and compares a phase difference between two data output from two adjacent input / output terminals of the plurality of input / output terminals. Then, the output time difference between the two data is adjusted to be within the reference value.

Therefore, the dicing may be cut after the adjustment is completed, and a compact semiconductor memory device not including the adjustment phase comparison circuit can be manufactured.

Further, the semiconductor memory device according to the present invention
A semiconductor memory device including a real chip and a dicing unit, wherein the real chip includes a plurality of input / output terminals, an interface circuit that outputs data read from a memory cell array to the plurality of input / output terminals, and a plurality of input / output terminals. A delay circuit provided corresponding to the first input / output terminal in the adjacent first and second input / output terminals arbitrarily selected from the output terminal; A third input / output terminal provided opposite to the second input / output terminal, a fourth input / output terminal provided opposite to the second input / output terminal,
And a fifth input / output terminal connected to the equal load, and the delay circuit outputs the first data output from the first input / output terminal in response to the activation of the test mode signal to the third input / output terminal. And a fifth input / output terminal to input to the phase comparison circuit,
Inputting the second data output from the second input / output terminal to the phase comparison circuit through the fourth and fifth input / output terminals;
The first data is delayed until the result of comparing the phase of the first data with the phase of the second data compared by the phase comparison circuit switches from the first logic to the second logic.

In the semiconductor memory device according to the present invention, a dicing section different from an actual chip including a plurality of input / output terminals and a memory cell array outputs two output signals from two adjacent input / output terminals of the plurality of input / output terminals. A plurality of terminals for detecting an output time difference between the two data are provided.

Then, two adjacent input / output terminals of the actual chip are connected to the input / output terminal of the dicing unit using the probe, and a phase difference between the two adjacent input / output terminals is detected. Then, based on the detected phase difference, the output time difference between the two data is adjusted to be within the reference value. The interface circuit is DD
In the case of an R-DRAM, it is an input / output interface circuit, and in the case of a Rambus DRAM, it is an interface logic circuit.

Therefore, the output time difference between the two data can be adjusted without manufacturing the phase comparison circuit in the semiconductor memory device.

Further, after the adjustment is completed, the semiconductor device can be made compact by cutting the dicing portion.

An adjusting method according to the present invention is an adjusting method for adjusting an output time difference between data output from a semiconductor memory device. The adjusting method according to the present invention includes a plurality of input / output terminals adjacent to each other when a test mode signal is activated. First and second
Detecting an output time difference between the first data output from the first input / output terminal and the second data output from the second input / output terminal under the condition of equal load from the input / output terminal of the first input / output terminal
And a second step of delaying the second data based on the output time difference such that the output time difference of the second data with respect to the first data is within a reference value.

In the adjusting method according to the present invention, when the test mode is entered, two adjacent input / output terminals arbitrarily selected from a plurality of input / output terminals are used.
An output time difference between data output from the two input / output terminals is detected. Then, the output time difference is adjusted so as to be within the reference value by delaying the data output from one of the input / output terminals.

Therefore, a semiconductor memory device capable of outputting data from a plurality of input / output terminals at almost the same timing can be manufactured.

Since the output time difference between two data is detected from two adjacent input / output terminals under the condition of equal load, an accurate output time difference can be detected. As a result, the output timing of data from the plurality of input / output terminals in the semiconductor memory device can be accurately adjusted.

Preferably, in the first step, the phase of the second data is compared with the phase of the first data by a phase comparison circuit connected to the first and second input / output terminals and the equal load. In the second step, the second data is delayed until the comparison result of the phase comparison circuit switches from the first logic to the second logic.

The phase of the second data is compared with the phase of the first data by the phase comparison circuit, and the comparison result is the first data.
The second data is delayed by the delay circuit until the logic is switched from the logic to the second logic, and the output time difference between the data output from two adjacent input / output terminals is adjusted to be within the reference value. That is, of the two data output from the two adjacent input / output terminals, the data whose phase is advanced is delayed until the phase relation is switched with respect to the data whose phase is delayed, and the output time difference between the two data is delayed. Is adjusted to be within the reference value.

Therefore, by detecting a change in the phase difference between two data output from two adjacent input / output terminals, the output time difference can be easily adjusted to be within the reference value.

Preferably, the phase comparison circuit is provided in the dicing section, and further includes a third step of cutting the dicing section after the second step is completed.

The phase difference between data output from two adjacent input / output terminals is detected by the phase comparison circuit,
After the output time difference between the two data is adjusted, the dicing unit provided with the phase comparison circuit is cut off.

Therefore, a compact semiconductor memory device capable of outputting data from a plurality of input / output terminals at almost the same timing can be manufactured.

Preferably, the first input / output terminal and the third input / output terminal provided opposite to the first input / output terminal are connected to the first probe in accordance with activation of the test mode signal. The second input / output terminal is connected to the fourth input / output terminal provided opposite to the second input / output terminal by a second probe, and the third input / output terminal and the fourth input / output terminal are connected to each other.
Connecting the phase comparison circuit to the fifth input / output terminal connected to the equal load with the fifth input / output terminal by a third probe before the first and second steps.

Of the plurality of input / output terminals provided on the actual chip, another two input / output terminals are provided in the dicing section so as to face two adjacent input / output terminals. Then, two input / output terminals of the real chip and two input / output terminals of the dicing unit are connected by a probe, and a phase difference between two adjacent input / output terminals is detected. Then,
Based on the detected phase difference, the output time difference between the two data is adjusted to be within the reference value.

Therefore, the output time difference between two data can be adjusted without manufacturing a phase comparison circuit in a semiconductor memory device.

Preferably, after the second step is completed, a third step of cutting the dicing portion is further included.

After the data output time difference between two adjacent input / output terminals is adjusted to be within the reference value,
Dicing is cut.

Therefore, a compact semiconductor memory device having almost the same output timing can be manufactured.

[0044]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.

[First Embodiment] Referring to FIG. 1, a semiconductor memory device 20 according to the present invention has an input / output interface circuit 1, a row decoder 2, a memory cell array 3, and an I / O interface circuit.
O control circuit 4, column decoder 5, test mode recognition circuit 6, input / output terminals DQ1 to DQn, adjustment circuit TC1
To DQn-1.

The input / output interface circuit 1 receives an address signal and outputs the address signal to the row decoder 2 and the column decoder 5. The input / output interface circuit 1 inputs data read from the memory cell array 3 via the I / O control circuit 4 and outputs the data to the adjustment circuits TC1 to TCn-1. The input / output interface circuit 1 receives a row address strobe signal / RAS = L (logic low) level, a column address strobe signal / CAS = L level, and a mode entry signal ME = L level, and inputs an address signal of a specific pattern. When input, the test mode entry signal TME is output to the test mode recognition circuit 6.

Row decoder 2 decodes a row address from input / output interface circuit 1, and activates a word line pair (not shown) in memory cell array 3 corresponding to the row address. Memory cell array 3 includes a plurality of memory cells, stores data written in the memory cells based on a row address specified by row decoder 2 and a column address specified by column decoder 5, and stores the row address. And outputs the data of the memory cell specified by the column address. The I / O control circuit 4 controls writing / reading of data to / from a memory cell in the memory cell array 3. Column decoder 5 decodes a column address from input / output interface circuit 1, and a bit line pair (not shown) in memory cell array 3 corresponding to the column address.
Activate.

When receiving test mode entry signal TME from input / output interface circuit 1, test mode recognition circuit 6 outputs an activated test mode signal TE to each of adjustment circuits TC1 to TCn-1. Adjustment circuit T
When each of C1 to TCn-1 receives the activated test mode signal TE, two adjacent input / output terminals DQ1, DQ1,. , DQn−1, n so that the output time difference between the data output from DQn−1, n is within the reference value.

Referring to FIG. 2, adjustment circuits TC1 to TCn
Each of −1 includes a delay circuit 8, a phase comparison circuit 9, and a delay signal generation circuit 10. The pads 11 and 12 correspond to two adjacent input / output terminals arbitrarily selected from the plurality of input / output terminals DQ1 to DQn. That is, when the adjustment circuit TC1 is configured by the delay circuit 8, the phase comparison circuit 9, and the delay signal generation circuit 10, the pad 11 corresponds to the input / output terminal DQ1, and the pad 12 corresponds to the input / output terminal DQ.
It corresponds to Q2. Then, by the delay circuit 8, the phase comparison circuit 9, and the delay signal generation circuit 10,
When each of the adjustment circuits TC2 to TCn-1 is configured,
The pad 11 corresponds to each of the input / output terminals DQ2 to DQn-1, and the pad 12 corresponds to each of the input / output terminals DQ3
To DQn.

The output control clock circuit 7 controls the output timing of data output from the pads 11 and 12 based on a reference clock. The output control clock circuit 7 is connected to the delay circuit 8 via a wiring 14A. They are connected via a wiring 14B. Delay circuit 8 is pad 1
The delay circuit 13 is connected to the pad 12 via a wiring 16. In addition, wiring 1
5 and the wiring 16 have the same resistance value and length. The phase comparison circuit 9 is connected to the pad 11 via a wiring 17, and is connected to the pad 12 via a wiring 18. The wiring 17 and the wiring 18 have the same resistance value and length. That is, the phase comparison circuit 9 is connected to the pads 11 and the pads 12 at the same load. Therefore, the phase comparison circuit 9 compares the phase of the data output from the pad 11 with the phase of the data output from the pad 12 under the condition that the pads 11 and 12 are connected to the same load, and compares the comparison result. Output to the delay signal generation circuit 10. As a result, the phase comparison circuit 9 can accurately detect the phase difference between the data output from the pad 12 and the data output from the pad 11.

The delay signal generation circuit 10 generates the delay signal SDL until the comparison result from the phase comparison circuit 9 switches from the L level to the H level as described later, and outputs the delay signal SDL to the delay circuit 8. . When the comparison result from the phase comparison circuit 9 switches from the L level to the H level, a delay fixed signal SDLC is generated, and the delay fixed signal SDLC is generated.
LC is output to the delay circuit 8.

The delay circuit 8 delays the data output from the pad 11 based on the delay signal SDL by a method described later, and delays the data output from the pad 11 based on the delay fixed signal SDLC.
The delay amount of the data output from is fixed.

Therefore, the adjusting circuits TC1 to TCn-1
Of the wirings 14A and 14B, the output control clock circuit 7 controls the output timing of the data output from the pad 11 and the data output from the pad 12 based on the reference clock. This is an adjustment circuit that adjusts an output time difference between two data generated due to the difference to be within a reference value. Note that the delay signal generation circuit 10 does not output the delay signal SDL and the delay fixed signal SDLC to the delay circuit 13. Adjustment circuit TC
Each of 1 to Tcn-1 detects a phase difference between one of two data output from pads 11 and 12, which are two adjacent input / output terminals, based on the phase of the other data. This is because the output time difference between the two data is adjusted within the reference value based on the detected phase difference.

Referring to FIG. 3, a phase comparison circuit 9 includes a switch 91, NANDs 92 to 97, and inverters 98 to 97.
101. NAND 92 and NAND 93, NA
ND94 and NAND95, and NAND96 and NAN
D97 functions as a flip-flop.

When the phase of the signal REF is compared with the phase of the signal RTN, the phase comparison circuit 9
, And a signal RTN from the terminal 104. The switch 91 inputs a signal ZUPF which is an output signal of the NAND 94.

Referring to FIG. 4, when phase comparison circuit 9 inputs signal (a) from terminals 102 and 103 and signal (b) from terminal 104, switch 91 outputs signal (c).
Enter Then, the UP terminal outputs the signal (d). That is, when the signal (b) corresponding to the signal RTN is at the H level at the rising of the signal (a) corresponding to the signal REF, the UP terminal outputs the H level signal slightly behind the rising timing of the signal (a). Is output.

Referring to FIG. 5, when phase comparator 9 receives signal (a) from terminals 102 and 103 and signal (b) from terminal 104, switch 91 receives signal (c). I do. Then, the UP terminal outputs the signal (d). That is, when signal (b) corresponding to signal RTN is at L level at the rise of signal (a) corresponding to signal REF, UP terminal outputs a signal at L level.

Therefore, when the phase of the signal REF to be compared is behind the phase of the signal RTN as the reference signal (see FIG. 4), the phase comparison circuit 9 outputs an H level signal from the UP terminal. , The phase of the signal REF is the signal RT
When the phase is advanced with respect to the N phase (see FIG. 5), the phase comparison circuit 9 outputs an L level signal from the UP terminal. As a result, it is possible to determine from the signal output from the UP terminal whether the phase of the signal REF to be compared is delayed or advanced with respect to the phase of the signal RTN as the reference signal.

The input / output terminals DQ1, DQ1,
When detecting a time difference between data output from DQ2 and DQ2, the phase comparison circuit 9 inputs data output from the input / output terminal DQ1 from terminals 102 and 103, and
Data output from Q2 is input from terminal 104.
The same applies to the case where the time difference of data output from other input / output terminals is detected.

Referring to FIG. 6, a method of adjusting the time difference between data output from two adjacent input / output terminals using the comparison result in phase comparison circuit 9 will be described.
Signal REF for the phase of signal RTN (shown by the dotted line)
When the phase is changed (shown by a solid line) (see FIG. 6A), the phase comparison circuit 9 outputs the L level from the UP terminal based on the phase difference between the signal REF and the signal RTN as described above. Alternatively, an H-level signal is output (see FIG. 6B). In the area where the time is 0 to 2.5 nsec,
The phase of the signal REF is significantly ahead of the phase of the signal RTN, and the phase comparison circuit 9 outputs an L-level signal from the UP terminal. The phase of the signal REF is delayed,
When the phase of the signal REF matches the phase of the signal RTN at nsec, the phase comparison circuit 9 outputs an H-level signal from the UP terminal. In the time period of 4 nsec or more, the phase of the signal REF is further delayed and the signal REF is
Is greatly delayed with respect to the phase of the signal RTN. When the time reaches 16 nsec, the phase of the signal REF changes to the signal RTN.
Of the phase comparison circuit 9
Outputs an L-level signal from the UP terminal.

Therefore, when the phase of the signal REF is changed with respect to the phase of the signal RTN, which is the reference signal, the phase comparison circuit 9 changes from the L level only when the phase of the signal REF matches the phase of the signal RTN. A signal that switches to the H level is output. That is, at the timing T1, the signal REF
Is in phase with the signal RTN, the output from the UP terminal of the phase comparison circuit 9 switches from the L level to the H level at timing T2. Then, the phase comparison circuit 9
T at which the output of L switches from L level to H level
2 is detected until the phase of the signal REF is delayed by delaying the phase of the signal REF to be compared.
Can be matched. As shown in FIG. 6A, by detecting the phase difference of the signal REF with respect to the phase of the signal RTN, the signal REF with respect to the signal RTN is detected.
Output time difference can be detected.

In the present invention, two data output from two adjacent input / output terminals DQ1 and DQ2 are input to the phase comparison circuit 9, and the output signal from the phase comparison circuit 9 is switched from L level to H level. Input / output terminal DQ1
When the timing of switching the output signal from the phase comparison circuit 9 from the L level to the H level is detected, the phase of the data output from the input / output terminal DQ1 is fixed. Therefore, when the output signal from phase comparison circuit 9 is at L level or H level, delay signal generation circuit 10 shown in FIG.
DL is generated and output to the delay circuit 8, and when the output signal from the phase comparison circuit 9 switches from L level to H level, a delay fixed signal SDLC is generated and output to the delay circuit 8. In this case, the delay signal generation circuit 10 does not output the delay signal SDL and the delay fixed signal SDLC to the delay circuit 13. This is because the data output from the pad 12 is a signal serving as a reference for performing a phase comparison.

Referring to FIG. 7, delay circuits 8 and 13 include switch 131, terminals 132 and 133, and delay section 134.
And The switch 131 is connected to a terminal 133 when data serving as a reference for phase comparison is input to the delay circuits 8 and 13.
, And the data is output to the pad 12 without delay. When data to be subjected to phase comparison is input to the delay circuits 8 and 13, the switch 131 is connected to the terminal 132.
, And the data is output to the pad 11 after being delayed by the delay unit 134. The switch 131 is initially connected to the terminal 13
3 and is connected to the terminal 132 when the delay signal SDL or the delay fixed signal SDLC is input from the delay signal generation circuit 10.

Referring to FIG. 8, delay units 134 of delay circuits 8 and 13 include resistors 135-139 and capacitors 140
To 144, fuses 145, 147, and N-channel M
OS transistors 146 and 148 and terminals 170 and 17
And 1. The resistors 135 to 139 have the same resistance value R, and the capacitors 140 to 144 have the same capacitance C. Resistance 135 and capacitor 140, resistance 136 and capacitor 141, resistance 137 and capacitor 142, resistance 1
38 and the capacitor 143, and the resistor 139 and the capacitor 144 each constitute a delay stage for delaying the phase of the input signal by a fixed amount. Fuse 145 is N-channel M
The fuse 145 and the N-channel MOS transistor 146 connected in series with the OS transistor 146 are connected in parallel with the resistor 136. Fuse 147 is connected in series with N-channel MOS transistor 148, and fuse 147 and N-channel MOS transistor 14 connected in series are connected.
8 is connected in parallel with the resistor 138.

N-channel MOS transistor 146 has
Activated / inactivated by signal / TM0, N-channel MOS transistor 148 is activated / inactivated by signal / TM1. Signal / TM0, signal / TM1
Constitutes the delay signal SDL or the delay fixed signal SDLC. When delay signal SDL including signal / TM0 = L level and signal / TM1 = H level is input to delay section 134, N-channel MOS transistor 146 is inactivated and N-channel MOS transistor 148 is activated. Then, the delay unit 134 converts the signal input from the terminal 170 into the resistor 135, the capacitor 140, and the resistor 13
6, the capacitor 141, the resistor 137 and the capacitor 14
2, and four delay stages including a resistor 139 and a capacitor 144. Also, the signal / TM0 = H level,
When delay signal SDL having signal / TM1 = H level is input to delay section 134, N-channel MOS transistors 146 and 148 are activated. Then, the delay unit 134 converts the signal input from the terminal 170 into the resistor 135.
And the capacitor 140, the resistor 137 and the capacitor 142,
And a delay of three delay stages including a resistor 139 and a capacitor 144. Further, when delay signal SDL including signal / TM0 = L level and signal / TM1 = L level is input to delay section 134, N-channel MOS transistors 146 and 148 are inactivated. Then, the delay unit 134 converts the signal input from the terminal 170 into the resistor 135.
And the capacitor 140, the resistor 136 and the capacitor 141,
Delay is performed by five delay stages including a resistor 137 and a capacitor 142, a resistor 138 and a capacitor 143, and a resistor 139 and a capacitor 144. Therefore, the delay unit 134
In the above, the number of delay stages can be changed within a range of 3 to 5 stages depending on the type of the input delay signal SDL.

Then, the delay section 134 outputs the delay fixed signal S
When the DLC is input, the fuses 145 and 147 are trimmed to fix the delay amount. For example, when a signal having a signal / TM0 = L level and a signal / TM1 = H level is input as the delay fixed signal SDLC, the delay unit 134 removes the fuse 145 and removes the N-channel MOS transistor 14
6 is inactivated, fuse 147 is short-circuited, and N-channel MOS transistor 148 is activated. Then,
The delay unit 134 delays the input signal by a fixed number of four delay stages and outputs the delayed signal from the terminal 171.

The delay section 134 is not limited to the configuration shown in FIG. 8, but may have the configuration shown in FIG. Referring to FIG.
Delay unit 134 includes inverters 149 to 157, fuses 158 to 160, and N-channel MOS transistor 1
61 to 163, and terminals 164 and 165. The inverter 149 and the inverter 150, the inverter 152 and the inverter 153, and the inverter 155 and the inverter 156 are connected in parallel. Fuse 158 and N-channel MOS transistor 161 are inserted in series between the output terminal of inverter 149 and the output terminal of inverter 150. A fuse 159 and an N-channel MOS transistor 162 are inserted in series between the output terminal of the inverter 152 and the output terminal of the inverter 153. Further, between the output terminal of inverter 155 and the output terminal of inverter 156, fuse 160 and N-channel MOS transistor 163 are inserted in series.

Inverters 149 to 157 each include an N-channel MOS transistor and a P-channel MOS transistor having the same channel width. N channel M
OS transistor 161 is activated / deactivated by signal / TM0. N channel MOS transistor 1
62 is activated / inactivated by the signal / TM1. N-channel MOS transistor 163 receives signal / T
Activated / inactivated by M2. And the signal /
TM0, / TM1, and / TM2 constitute the delay signal SDL or the delay fixed signal SDLC.

Since inverter 149 and inverter 150, inverter 152 and inverter 153, and inverter 155 and inverter 156 are connected in parallel,
It can be considered as one inverter having a wide channel width between the N-channel MOS transistor and the P-channel MOS transistor forming the inverter. Then, when N-channel MOS transistors 161 to 163 are activated, inverters 149 and 150, inverter 152 and inverter 153, and inverter 155
And inverter 156 are connected to inverters 151 and 15 respectively.
The input signal is delayed by a delay amount larger than the delay amount in 4,157. The delay unit 134 delays the signal input from the terminal 164 most when all of the N-channel MOS transistors 161 to 163 are activated. When all of the N-channel MOS transistors 161 to 163 are inactivated, The signal input from the terminal 164 is delayed the least. Then, the delay unit 134 outputs the delay fixed signal S
When the DLC is input, the fuses 158 to 160 are trimmed by the above-described method to fix the delay amount.

Referring to FIG. 2 again, when the activated test mode signal TE is input from test mode recognition circuit 6, phase comparison circuit 9 connects to pad 11 from delay circuit 8 via line 15 to pad 11. The output data and the delay circuit 13
And the data output to the pad 12 via the wiring 16 from the pad 11 via the wirings 17 and 18 of equal load.
Is compared with the phase of the data output to the pad 12. Then, the phase comparison circuit 9 outputs an L level or H level signal to the delay signal generation circuit 10 according to the comparison result. The delay signal generation circuit 10
When the output signal from phase comparison circuit 9 is at L level or H level, signals / TM0, / TM1 (or signal / T
M0, / TM1, / TM2) to the delay circuit 8. Then, the delay unit 134 of the delay circuit 8 delays the phase of the input data by the delay amount determined by the delay signal SDL according to the method described above and outputs the delayed data to the pad 11.

The delay signal generation circuit 10 includes a phase comparison circuit 9
When a signal that switches from L level to H level is input, signals / TM0 and / TM1 (or signals / TM0 and / TM0) are input.
(TM1, / TM2) is output to the delay circuit 8. The delay circuit 8 includes a delay fixed signal SD
The fuses 145 and 147 (or the fuses 158 to 160) are trimmed based on the LC to fix the delay amount of input data. As a result, the time difference between the data output from the pad 11 and the data output from the pad 12 is suppressed to several tens of picoseconds (psec).

The semiconductor memory device according to the present invention may be the semiconductor memory device 100 shown in FIG. The semiconductor memory device 100 includes a memory chip 30, an interface logic circuit 40, adjustment circuits TC1 to TCn-1, and input / output terminals DQ1 to DQn. The memory chip 30
I / O interface circuit 1, row decoder 2, memory cell array 3, I / O control circuit 4, column decoder 5
And a test mode recognition circuit 6. I / O interface circuit 1, row decoder 2, memory cell array 3,
The description of the I / O control circuit 4, the column decoder 5, and the test mode recognition circuit 6 is as described above. Interface logic circuit 40 outputs data read from memory chip 30 to input / output terminals DQ1 to DQn, and inputs data input from input / output terminals DQ1 to DQn to memory chip 30. Adjustment circuits TC1 to DQn-1
Are two adjacent input / output terminals DQ1, DQ2,
Are arranged between DQ2, DQ3,..., DQn-2 and DQn-1, and have the same configuration as the configuration shown in FIG.

Semiconductor memory device 100 is, for example, a Rambus DRAM. Data is input / output between memory chip 30 and interface logic circuit 40 at a frequency of about 500 MHz, and input / output terminals DQ1-DQn are connected to external device. (Not shown) between 800 MHz and 1 GH
Data is exchanged at the frequency of z. Therefore, in the case of a Rambus DRAM, the input / output terminals DQ1 to DQ1
Time difference between data output from DQn is several tens of psec
It is extremely important to adjust the degree.

Row address strobe signal / RAS = L level, column address strobe signal / CAS = L level,
When the mode entry signal ME = L level is input and an address signal of a specific pattern is input from the interface logic circuit 40 to the input / output interface circuit 1 of the memory chip 30, the input / output interface circuit 1 tests the test mode entry signal TME. Output to the mode recognition circuit 6. Then, the test mode recognition circuit 6 outputs the activated test mode signal TE to each of the adjustment circuits TC1 to TCn-1. Then, the adjustment circuits TC1 to TCn
Each -1 adjusts the time difference between data output from two adjacent input / output terminals by the above-described method to about several tens of psec. Thereby, the time difference between the data output from the input / output terminals of the semiconductor memory device 100 is adjusted to be within a certain value.

Referring to FIG. 11, semiconductor memory devices 20,
An adjustment method for adjusting the time difference between the data output from two adjacent input / output terminals in 100 will be described. When the adjustment operation starts, a phase difference between two data output from two adjacent input / output terminals is detected by the phase comparison circuit 9 under an equal load condition (step S1). It is determined whether or not the output signal from the phase comparison circuit 9 has switched from the L level to the H level (step S2). If the output signal from the phase comparison circuit 9 has not switched from the L level to the H level, The delay signal generation circuit 10 outputs the delay signal SDL, and delays the phase of one data by a delay amount determined by the type of the delay signal SDL (step S3). Then, the loop of steps S1 to S3 is repeated until the output signal of the phase comparison circuit 9 switches from the L level to the H level. Step S2
If the output signal from the phase comparison circuit 9 has been switched from L level to H level, the delay signal generation circuit 10 outputs the delay fixing signal SDLC, and the delay amount is fixed by trimming (step S4). Thus, the operation of adjusting the time difference between the data output from the two adjacent input / output terminals is completed.

According to the first embodiment, semiconductor memory device 2
0 and 100 detect the phase difference between two data output from two adjacent input / output terminals under the condition of equal load, delay one of the data according to the detection result, and output the two data. Since the adjusting circuit for adjusting the time difference within a certain value is provided, the output timing of data from the input / output terminals DQ1 to DQn can be adjusted within the reference value.

[Second Embodiment] Referring to FIG. 12, a semiconductor memory device 200 according to a second embodiment
And dicing 60. The real chip 50 includes an output control clock circuit 7, delay circuits 8 and 13, wirings 14A, 14B, 15, and 16, and pads 11 and 12. The real chip 50 includes the input / output interface circuit 1, the row decoder 2, the memory cell 3,
It also includes an I / O control circuit 4, a column decoder 5, and a test mode recognition circuit 6.

The dicing section 60 includes a phase comparison circuit 9
Wirings 17 and 18 are provided. I / O interface circuit 1, row decoder 2, memory cell 3, I / O control circuit 4,
The column decoder 5, the test mode recognition circuit 6, the output control clock circuit 7, the delay circuits 8, 13, the phase comparison circuit 9, the wirings 14A, 14B, 15, 16 to 18, and the pads 11, 12 are as described above. is there. The method of adjusting the output time difference between data output from two adjacent input / output terminals in the semiconductor memory device 200 is also as described above.

The semiconductor memory device 200 is manufactured with the real chip 50 and the dicing unit 60 connected. Then, after the adjustment of the output time difference between the data output from the two adjacent input / output terminals is completed by the above-described method, the dicing unit 60 is disconnected from the actual chip 50.
By cutting the dicing section 60 and manufacturing a semiconductor memory device using only the actual chip 50, a compact semiconductor memory device can be manufactured.

Referring to FIG. 13, semiconductor memory device 200
The method for adjusting the output time difference in the above will be described. The method of adjusting the output time difference in the semiconductor memory device 200 is obtained by adding step S5 to the flowchart of FIG. That is, after the output time difference between the data output from the two adjacent input / output terminals is adjusted to about several tens of psec, the dicing unit is cut off (step S5). Thus, the adjustment of the output time difference between the data output from the two adjacent input / output terminals in the semiconductor memory device 200 ends.

According to the second embodiment, semiconductor memory device 2
00 detects a phase difference between two data output from two adjacent input / output terminals under an equal load condition, delays one data according to the detection result, and determines an output time difference between the two data. Since the adjustment circuit is provided for adjusting the data to be within a certain value, the output timing of the data from the input / output terminals DQ1 to DQn can be adjusted to be within the reference value.

Further, the semiconductor memory device 200 includes a phase comparison circuit 9 in the dicing section 60 for detecting a phase difference between two data output from two adjacent input / output terminals under an equal load condition. After the output time difference between the two data is adjusted, the dicing unit is cut off, so that compactness can be achieved.

[Third Embodiment] Referring to FIG. 14, a semiconductor memory device 300 according to a third embodiment
And a dicing unit 80. The real chip 70 includes an output control clock circuit 7, delay circuits 8 and 13,
Wirings 14A, 14B, 15, 16 and pads 11, 12
And The real chip 70 also includes the input / output interface circuit 1, row decoder 2, memory cell 3, I / O control circuit 4, column decoder 5, and test mode recognition circuit 6 shown in FIG.

An input / output interface circuit 1, a row decoder 2, a memory cell 3, an I / O control circuit 4, a column decoder 5,
Test mode recognition circuit 6, output control clock circuit 7, delay circuits 8, 13, phase comparison circuit 9, wiring 14
A, 14B, 15, 16 to 18, and pads 11, 1
2 is as described above. On the other hand, the dicing 80 includes pads 81 to 83 and wirings 84 and 85. The pad 81 is formed to face the pad 11 of the real chip 70, and the pad 83 is formed to face the pad 12 of the real chip 70. The pad 82 is connected to the pad 81 by a wiring 84, and is connected to the pad 83 by a wiring 85. The wiring 84 and the wiring 85 have the same load and the same length. That is, the pad 82
Are connected to the pads 81, 83 and the same load by wirings 84, 85.

In the semiconductor memory device 300, when an output time difference between two data output from two adjacent input / output terminals is adjusted, the pad 11 of the real chip 70 and the pad 81 of the dicing unit 80 are connected to the probe 86. The pad 12 of the real chip 70 and the pad 83 of the dicing unit 80 are connected by the probe 87. The probes 86 and 87 have the same load. The pad 82 is connected to the phase comparison circuit 9 by a probe 88. Phase comparison circuit 9 and delay signal generation circuit 10 are arranged outside semiconductor memory device 300.

Row address strobe signal / RAS = L level, column address strobe signal / CAS = L level,
When the mode entry signal ME = L level is input, an address signal of a specific pattern is input from the input / output interface circuit 1, and the input / output interface circuit 1 outputs the test mode entry signal TME, the test mode recognition circuit 6 is activated. The test mode signal TE is output. Then, the data output from the delay circuit 8 to the pad 11 via the wiring 15 is transmitted to the probe 86 and the pad 8.
1, the wiring 84, the pad 82, and the probe 88 are input to the phase comparison circuit 9. The data output from the delay circuit 13 to the pad 12 via the wiring 16 is
The signal is input to the phase comparison circuit 9 via the probe 87, the pad 83, the wiring 85, the pad 82, and the probe 88.

The phase comparison circuit 9 compares the phase of one data with the phase of the other data, and outputs a signal corresponding to the comparison result to the delay signal generation circuit 10. Delay signal generation circuit 10 outputs delay signal SDL to delay circuit 8 until the signal from phase comparison circuit 9 switches from L level to H level, and switches the signal from phase comparison circuit 9 from L level to H level. After that, the delay fixed signal SDLC is output to the delay circuit 8. The delay of the data and the fixing of the delay amount in the delay circuit 8 are the same as those described in the first embodiment.

When the output time difference between two data output from two adjacent input / output terminals is adjusted, the dicing unit 80 is cut off.

Referring to FIG. 15, semiconductor memory device 300
The method of adjusting the output time difference between two data output from two adjacent input / output terminals will be described. The flowchart shown in FIG. 15 is the same as FIG. 13 except that step S0 is inserted in the flowchart shown in FIG.

When the adjustment operation starts, step S0
In this case, the probes 86 and 83 are respectively connected so that the pads 11 and 81 and the pads 12 and 83 of the dicing unit 80 facing the real chip 70 are connected under the same load condition.
87 is brought into contact. Subsequent operations are the same as those described with reference to FIG. The adjustment operation shown in FIG. 15 is performed between two adjacent input / output terminals.

According to the third embodiment, semiconductor memory device 3
00 is provided with a dicing unit having a pad for detecting a phase difference between two data output from two adjacent input / output terminals under the condition of equal load, so that a phase comparison circuit is connected to a pad of the dicing unit by a probe. Then, the output time difference between the two data can be adjusted within a certain value.

Since the semiconductor memory device 300 has a pad for detecting the phase difference between two data output from two adjacent input / output terminals under the condition of equal load, the output time difference is reduced. The adjusted dicing portion can be cut, and the size can be reduced.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description of the embodiments, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0094]

According to the semiconductor integrated circuit of the present invention, the adjusting circuit detects the output time difference of the first data from the second data under the condition of equal load from the first and second input / output terminals, and detects the difference. Based on the output time difference, the first data is delayed so that the output time difference of the first data with respect to the second data falls within the reference value, so that the data is output from the plurality of input / output terminals at almost the same timing. A semiconductor memory device can be manufactured.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a semiconductor memory device according to a first embodiment.

FIG. 2 is a schematic block diagram of an adjustment circuit.

FIG. 3 is a circuit diagram of a phase comparison circuit.

FIG. 4 is a diagram showing signals in a phase comparison circuit.

FIG. 5 is a diagram showing signals in a phase comparison circuit.

FIG. 6 is a diagram illustrating signals in a phase comparison circuit.

FIG. 7 is a configuration diagram of a delay circuit.

FIG. 8 is a circuit diagram of a delay unit of FIG. 7;

FIG. 9 is another circuit diagram of the delay unit of FIG. 7;

FIG. 10 is another schematic block diagram of the semiconductor memory device according to the first embodiment;

FIG. 11 is a flowchart showing a method for adjusting an output time difference according to the first embodiment.

FIG. 12 is a schematic block diagram of a semiconductor memory device according to a second embodiment.

FIG. 13 is a flowchart showing a method for adjusting an output time difference according to the second embodiment.

FIG. 14 is a schematic block diagram of a semiconductor memory device according to a third embodiment.

FIG. 15 is a flowchart showing a method for adjusting an output time difference according to the third embodiment.

[Explanation of symbols]

1 I / O interface circuit, 2 row decoder, 3
Memory cell array, 4 I / O control circuit, 5 column decoder, 6 test mode recognition circuit, 7 output control clock circuit, 8 and 13 delay circuit, 9 phase comparison circuit, 10 delay signal generation circuit, 11 and 12 pads, 1
4A, 14B, 15 to 18, 84, 85 wiring, 20, 1
00, 200, 300 semiconductor memory device, 30 memory chip, 40 interface logic circuit, 50, 70
Real chip, 60,80 dicing part, 81-83 pad, 86-88 probe, 91,131 switch, 92-97 NAND, 98-101, 149-1
57 inverters, 102 to 104, 132, 133,
164, 165, 170, 171 terminals, 134 delay unit, 135 to 139 resistor, 140 to 144 capacitor, 145, 147, 158 to 160 fuse, 14
6,148,161 to 163 N-channel MOS transistors.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B024 AA03 BA23 BA29 CA07 CA27 EA01 EA04 5B060 CC01 CC03 5L106 AA01 DD11 EE03 GG03

Claims (11)

[Claims] A plurality of input / output terminals, an interface circuit for outputting data read from a memory cell array to the input / output terminals based on a reference clock, and a test mode entry via the interface circuit. A test mode recognition circuit for activating a test mode signal; and an adjacent first and second input / output terminal arbitrarily selected from the plurality of input / output terminals in accordance with the activation of the test mode signal. An adjustment circuit that adjusts an output time difference between first and second data output from the first and second input / output terminals, respectively, wherein the adjustment circuit is configured to control the output time difference from the first and second input / output terminals. Detecting an output time difference of the first data with respect to the second data under a load condition, and, based on the detected output time difference, Output time difference between the first data to the second data delaying the first data to be in the reference value, the semiconductor memory device. 2. The adjustment circuit is connected to the first and second input / output terminals and an equal load,
A phase comparison circuit for comparing the phase of the first data with the phase of the second data;
2. The semiconductor memory device according to claim 1, further comprising: a delay circuit that delays the first data until the logic is switched to the first logic. 3. The adjustment circuit further includes a delay signal generation circuit that generates a delay signal or a delay fixed signal based on the comparison result, wherein the delay signal generation circuit determines that the comparison result is from a first logic to a first logic. And generating the delay signal until the comparison result switches from the first logic to the second logic. The delay circuit generates the delay fixed signal based on the delay signal. The first data is delayed, and the first data is delayed based on the delay fixed signal.
3. The semiconductor memory device according to claim 2, wherein the data delay amount is fixed. 4. The delay circuit includes: a plurality of delay elements for delaying the first data; and a plurality of fuses for selectively activating the plurality of delay elements, and trims the plurality of fuses. 4. The semiconductor memory device according to claim 3, wherein said plurality of delay elements are selectively activated to fix a delay amount of said first data. 5. The semiconductor memory device according to claim 2, wherein said phase comparison circuit is provided in a dicing unit. 6. A semiconductor memory device including a real chip and a dicing unit, wherein the real chip outputs a plurality of input / output terminals and data read from a memory cell array to the plurality of input / output terminals. An interface circuit, and a delay circuit provided corresponding to the first input / output terminal at adjacent first and second input / output terminals arbitrarily selected from the plurality of input / output terminals, A dicing unit, a third input / output terminal provided to face the first input / output terminal, a fourth input / output terminal provided to face the second input / output terminal, A third input / output terminal connected to an equal load and a fifth input / output terminal, wherein the delay circuit is output from the first input / output terminal when the test mode signal is activated. The first data is stored in the third And the second data output from the second input / output terminal to the phase comparison circuit via the fourth and fifth input / output terminals. And delaying the first data until the result of comparison of the phase of the first data with the phase of the second data compared by the phase comparison circuit switches from the first logic to the second logic. Semiconductor storage device. 7. An adjusting method for adjusting an output time difference between data output from a semiconductor memory device, wherein, when a test mode signal is activated, adjacent first and second input / output terminals are selected from a plurality of input / output terminals. Detecting an output time difference between the first data output from the first input / output terminal and the second data output from the second input / output terminal under the condition of equal load from the input / output terminal Adjusting, based on the output time difference, a second step of delaying the second data such that an output time difference of the second data with respect to the first data is within a reference value. Method. 8. The method according to claim 1, wherein in the first step, the first
And comparing the phase of the second data with the phase of the first data by a phase comparison circuit connected to a second input / output terminal and an equal load. In the second step, comparing the phase of the phase comparison circuit The adjustment method according to claim 7, wherein the second data is delayed until a result switches from the first logic to the second logic. 9. The phase comparing circuit is provided in a dicing unit, and further includes a third step of cutting the dicing unit after the completion of the second step.
Adjustment method described in 1. 10. A first probe, comprising: a first probe connected to the first input / output terminal and a third input / output terminal provided opposite to the first input / output terminal in response to activation of the test mode signal. The second input / output terminal is connected to a fourth input / output terminal provided opposite to the second input / output terminal by a second probe. The third input / output terminal And a step of connecting a phase comparison circuit to a fifth input / output terminal connected to the fourth input / output terminal and the equal load by a third probe, before the first and second steps. Item 8. The adjustment method according to Item 7. 11. The adjusting method according to claim 10, further comprising a third step of cutting the dicing unit after the second step is completed.