JP2002007179A - Information processor and file system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a file system API whose mounting scale is small and which has the possibility capable of dealing with various storage means. SOLUTION: This system is provided with respective indivisual libraries being respective file systems API for each storage means and a common library being a common file system API for each storage means. The respective individual libraries substitute the function of the common library for their own functions at the time of operating the corresponding storage means, thereby functioning the respective individual libraries by using the common library.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an information processing apparatus and a file system.

[0002]

2. Description of the Related Art A personal computer or a PDA (Pers
2. Description of the Related Art In an information processing device such as an onal Digital Assistants (portable information device), recording / reproducing of a file or the like on various recording media such as an HDD (Hard Disc Drive), an optical disk, a magneto-optical disk, a magnetic disk, and a memory card is performed. .

[0003]

The storage media accessed from the information processing apparatus include different types having the same file system. For example, as for media in a category called a memory card, each maker manufactures a variety of different types of card media, and all of these various memory cards employ the FAT file system. There is. Floppy (registered trademark) disks and hard disks also employ FAT.

[0004] Here, in a certain information processing apparatus, in consideration of selection of a medium that can be mounted and expansion in the future, an FAT corresponding to each medium is required. Therefore, it is conceivable to construct a file system so as to correspond to all media considered as a general-purpose FAT. In other words, a general-purpose file system API (Application Prog
ramming Interface) is required. In this case, general purpose FA
Regarding T, since each medium has its own FAT method, it is necessary to prepare a portion corresponding to each medium as an API, which is large in terms of mounting. I will. For example, in a PDA device or the like, it is inappropriate to mount a large-scale file system. On the other hand, FA for each individual media
Implementing the T file system API lacks extensibility.

[0005]

SUMMARY OF THE INVENTION In view of such circumstances, an object of the present invention is to realize a file system in which the mounting scale is not increased and the media expandability is not impaired.

Therefore, the information processing apparatus of the present invention has, as its file system, each individual library which is an individual file system API for each storage unit, and a common file system API which is a common file system API for each storage unit. Each of the individual libraries has a function of replacing the function of the common library with its own function when operating the corresponding storage means.
Make it work using a common library. That is, when a plurality of different types of storage means having the same file system can be accessed, each individual library uses the common library as an API to realize A
It is assumed that the PI scale can be reduced and that it can support various types of storage means.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in the following order. As an embodiment, a PDA device will be described as an information processing apparatus of the present invention. 1. 1. Appearance example of information processing device 2. Configuration of information processing device 3. OS structure and database structure Memory Card 4-1 Appearance 4-2 Terminals and Internal Structure of Memory Card 4-3 File System Processing Hierarchy 4-4 Physical Data Structure 4-5 Concept of Physical Address and Logical Address 4-6 Logical-Physical Address Conversion Table 4 -7 directory structure FAT structure 6. Interface between memory card and information processing device File system API

[0008] 1. Example of Appearance of Information Processing Apparatus FIG. 1 shows an example of the appearance of an information processing apparatus of this example. The information processing device 1 is a small and lightweight device suitable for being carried as a so-called PDA device. Also, it is assumed that a memory card 70 described later can be mounted as a recording medium to perform recording and reproduction. Note that the present invention is not limited to a portable information processing apparatus, but can be applied to any type of information processing apparatus including a personal computer, and the recording medium on which the apparatus performs recording is not limited to a memory card. Other types of recording media such as an HDD, an optical disk, a magneto-optical disk, or a RAM or a flash memory fixedly arranged in the apparatus may be used.

FIGS. 1A, 1B, 1C, and 1D are a plan view, a right side view, a left side view, and an outer appearance example of the information processing apparatus 1, respectively.
FIG. As shown in FIG. 1D, a memory slot 7 in which a memory card 70 to be described later can be inserted is formed on the upper surface side of the device. Various data (computer data, music data, audio data, moving image data, still image data, control data, and the like) can be recorded and reproduced. In the example of FIG. 1, since two memory slots 7 are formed,
One memory card 70 can be inserted at a time. Of course, the number of memory slots 7 to be formed is 1
Or three or more.

In this information processing apparatus 1, a display unit 2 formed of, for example, a liquid crystal panel is formed on a flat surface, and images and characters as data, data and images to be reproduced, and audio and music to be reproduced upon activation of application software and various processes. , An operation guide message, a menu screen for reproduction and editing operations, and the like are displayed.

On the information processing apparatus 1, various operators for user operation are provided. For example, operation key 3
a, a jog dial 3b, a push dial 3c, etc. are formed at required portions, respectively. These controls allow the user to perform, for example, a power supply operation, a menu operation, a selection operation, an input operation of characters and the like, and various other necessary operations. These controls are of course only examples. That is, the number, types, and positions of the deployed operators can be variously considered.

Further, a speaker 4, a microphone 5, and an imaging unit 6 are also formed on the information processing apparatus 1, so that audio output, input, image capturing by imaging, and the like can be executed.

Various terminals are formed for connection with various devices. For example, as shown in FIG. 1B, a headphone terminal 10, a line output terminal 12, a line input terminal 11, and the like are formed, and as shown in FIG.
Four terminals 8, USB (universal serial bus) terminals 9, and the like are formed. It should be noted that other examples are also conceivable for the types, numbers, and arrangement positions of these terminals. For example, a digital input / output terminal corresponding to an optical cable is provided, or
A CSI connector, a serial port, an RS232C connector, or the like may be formed.

2. FIG. 2 shows an internal configuration of the information processing apparatus 1. As shown in the figure, in the information processing device 1, first, as a core portion,
System controller 21, CPU 22, Flash R
An OM 23 and a D-RAM 24 are provided. Operation unit 3 as a part for basic user interface
5, a display control unit 27 and a display unit 2 are formed.

The system controller 21 inputs operation information from the operation unit 35 and interrupts the CPU 22 accordingly. The operation unit 35 corresponds to the various operators 3a, 3b, and 3c shown in FIG. Although not described in FIG. 1, a touch panel operator may be formed by displaying operation keys and icons on the display unit 2 and providing a touch detection mechanism on the display unit 2. The touch panel operator is also included in the operation unit 35 shown in FIG.

The CPU 22 is a basic software (OS: Operatin)
g System) and application programs. The CPU 22 executes a required process according to the operation information supplied via the system controller 21. The flash ROM 23 is an area for storing a basic operation program, various processing constants, setting information, and the like. D
A RAM 24 for storing information necessary for various processes, buffering data, expanding a work area of the CPU 22,
In addition, it is used variously according to the processing of the CPU 22.
The D-RAM 24 is provided with a storage area (non-volatile area).
And application software are installed. Then, the application software installed in the D-RAM 24 is started in response to an operation from the user, and is executed by the CPU 22. Also, the application software has a user interface screen, and based on the state transition by the user's instruction,
-Drawing is performed in the frame buffer secured in the RAM 24. The drawn image data is sent to the display control unit 27 and displayed on the display unit 2.

As described above, the memory slot 7 for the memory card 70 is formed, and the memory card 70 can be inserted. However, the CPU 22 writes or reads the memory card 70 via the memory card interface 28. Can be accessed. The interface operation between the memory card interface 28 and the memory card 70 will be described later. CPU2
2 can use the inserted memory card 70 as an expanded memory area. If an application program is recorded on the memory card 70, the application program can be installed in the D-RAM 24, or the application or data can be directly stored in the D-RAM 24.
24 to execute required processing. In addition, the CPU 22 can record, on the memory card 70, document data, image data, audio data, spreadsheet data, and the like created by the CPU 22 based on a certain application. By detecting that the memory card 70 is inserted into the memory slot 7, the operation for the memory card 70 can be performed for recording and reproduction, or the application or data recorded on the memory card 70 is automatically A so-called hot plug-in operation such as being developed in the D-RAM 24 is also possible. The memory card interface 28 is also capable of performing encryption processing on data recorded on the memory card 70 and decryption processing of read data.

The image pickup section 6 is formed by, for example, a CCD image pickup device and an image pickup circuit system. The captured image data captured by the imaging unit 6 is transmitted to the imaging data interface 34.
Can be taken into the D-RAM 24 via
The PU 22 edits captured image data and operates the memory card 70 by operating based on a predetermined application program.
Can be executed.

The audio interface 29 includes the above-described speaker 4, microphone 5, and headphone terminal 1.
0, an interface part for audio data input / output from the line output terminal 12 and the line input terminal 11. For example, an analog audio signal input from the microphone 5 or the line input terminal 11 is subjected to predetermined amplification processing and filtering in the input audio processing unit 32, and is converted into digital audio data in the A / D converter 33, and is converted into an audio interface 29. Supplied to The audio interface 29 performs processing and output on the input digital audio data based on the control of the CPU 22. For example, after performing required compression encoding processing, the data can be supplied to the memory card interface 28 and recorded on the memory card 70. The audio interface 29 performs a predetermined decoding process on the digital audio data supplied by being read from the memory card 70, for example, and supplies the digital audio data to the D / A converter 30. The D / A converter 30 converts digital audio data into an analog audio signal. The output audio processing unit 31 performs predetermined amplification processing, impedance adjustment, and the like according to the output destination on the supplied analog audio signal, and outputs the analog audio signal to the speaker 4, the headphone terminal 10, and the line output terminal 12.

The USB interface 25 is a communication interface with an external device connected to the USB connector 9. CPU 22 is USB interface 2
5, data communication can be performed with an external personal computer or a peripheral device. For example, transmission and reception of control data, computer data, image data, audio data, and the like handled by the information processing device 1 are executed. Similarly, the IEEE 1394 interface 26 is a communication interface with an external device connected to the IEEE 1394 terminal 8. The CPU 22 can perform various data communications with external information devices via the IEEE1394 interface 26.

The configuration of the information processing apparatus 1 shown in FIG. 2 is merely an example, and the present invention is not limited to this. That is, addition of various constituent parts generally used in personal computers and PDA devices or deletion of unnecessary parts as actual products is determined by design convenience.

3. OS Structure and Database Structure Subsequently, in FIG. 3, the OS installed in the information processing apparatus 1 of the present example
The structure will be described. As shown in FIG. 3, the OS includes a manager layer including a kernel as a central part of the basic software, a hardware layer such as a standard library, and a hardware layer such as a control IC.
r). The application software operates on the basic operation based on the OS structure. For the HAL, a layer is added as one or a plurality of device drivers, and actual hardware (HW) is added.
Is driven.

Here, in particular, in the case of the information processing apparatus 1 of the present embodiment, since the memory card 70 can be driven and the data of the memory card 70 is managed by the FAT as described later, the FAT library is added to the OS. Further, a library (MS library) for handling the memory card is added. The memory drive is configured to drive the memory card 70 based on the FAT library and the MS library.

In the information processing apparatus 1 of the present example having such an OS structure, a concept of "database" is further introduced as a concept equivalent to a "file" in a usual manner. The “database” here is not simply a storage of data as in a normal database, but is formatted as a structure that allows the database itself to manage data. In this sense, “database” corresponds to “file”.

FIG. 4 shows the database structure. That is, in the database, an area including a database name (DTB Name) and other information is formed as a header (DTB header), and a pointer table is arranged.
The actual data recorded in the data area is in a state where positional management is performed based on the point information recorded in the pointer table.

As a database having such a structure,
There are two types. For example, generally, one application software is composed of a plurality of files, among which are an execution file (***. Exe) and a data file (***. Data). .Exe), there is a "resource database (***. Prc)", and as a data file (***. Data), there is a "database database (***. Dtb)". .

The information processing apparatus 1 of the present embodiment handles data based on such a concept of "database". Therefore, files recorded and reproduced in the memory card 70 (files handled by FAT) also have the form of the database. In this specification, the term "file" is used according to a general concept, and in this embodiment, "file" means a database having the above structure. Becomes

4. Memory Card 4-1 Appearance Next, the memory card 70 will be described. First, FIG.
Shows the outer shape of the memory card 70. Memory card 7
No. 0 includes, for example, a memory element having a predetermined capacity inside a plate-shaped casing as shown in FIG. 5, for example. In this example, a flash memory is used as the memory element. The casing shown as a plan view, a front view, a side view, and a bottom view in FIG. 5 is formed by, for example, a plastic mold.
mm, W12 = 20 mm, and W13 = 2.8 mm.

A terminal portion 72 having, for example, ten electrodes is formed from the lower front side to the bottom side of the housing. From this terminal portion 72, a read or write operation to an internal memory element is performed. The upper left part in the plane direction of the housing is a cutout 7
It is set to 3. The notch 73 is provided in the memory card 70
For example, when inserting the disk drive into the mounting / dismounting mechanism of the drive device main body, the insertion direction is prevented from being erroneously inserted. Also, from the top surface to the bottom surface of the housing, the label attaching surface 7
4 is formed so that the user can attach a label with the stored contents. Further, a slide switch 75 for preventing erroneous erasure of recorded contents is formed on the bottom side.

In such a memory card 70,
As the flash memory capacity, 4 MB (megabyte), 8 MB, 16 MB, 32 MB, 64 MB, 128
It is defined as one of the MBs. A so-called FAT (File Allocation Table) system is used as a file system for recording / reproducing data.

The writing speed is from 1500 KByte / sec.
330KByte / sec, read speed 2.45MBy
te / sec, the write unit is 512 bytes, and the erase block size is 8 KB or 16 KB. The power supply voltage Vcc is 2.7 to 3.6 V and the serial clock SC
LK is set to a maximum of 20 MHz.

4-2 Terminals and Internal Structure of Memory Card FIG. 6 shows an electrode structure of the terminal 72. As shown in FIG. 5, the terminal portion 72 has a structure in which ten planar electrodes are arranged in one row. As shown in FIG. 6, each of the electrodes (terminals T1 to T1)
0) is as follows.

The terminals T1 and T10 are used as detection voltage Vss terminals. The terminal T2 is an input terminal for the serial protocol bus state signal BS. Terminals T3 and T9 are power supply voltage Vcc terminals. The terminal T4 is a data terminal, that is, an input / output terminal for a serial protocol data signal. Terminals T5 and T7 are reserved. The terminal T6 is a detection terminal, and is used by the drive device (memory card interface of the information processing device 1) to detect the attachment of the memory card. The terminal T8 is connected to the serial clock S
CLK input terminal.

FIG. 6 also shows the internal configuration of the memory card 70. Inside the memory card 70, a control IC 80 and a flash memory 81 are provided.
The control IC 80 is a part for executing a write / read operation on the flash memory 81. As can be seen from the figure, the control IC 80 receives the serial protocol bus state signal BS from the terminal T2 and the terminal T8.
From the serial clock SCLK. During a write operation, the control IC 80 controls the serial protocol bus state signal BS and the serial clock S
In accordance with CLK, data supplied from terminal T4 is written to flash memory 81. At the time of reading, data is read from the flash memory 81 according to the serial protocol bus state signal BS and the serial clock SCLK, and is output from the terminal T4 to the drive device side.

The detection voltage Vss is supplied to the detection terminal T6. On the drive device side, the terminal voltage of the detection terminal T6 is detected by a resistor R as shown in FIG. It can be detected whether or not it is connected to the memory slot 7).

4-3 File System Processing Hierarchy Next, a format in a system using the memory card 70 as a recording medium will be described. FIG. 7 shows a file system processing hierarchy of a system using the memory card 70 as a recording medium. As shown in this figure, as a file system processing layer, a file management processing layer, a logical address layer, a physical address layer, and a flash memory access are sequentially arranged below the application processing layer. In this hierarchy, the file management processing layer is a so-called FAT (File Allocation Table). Also,
As can be seen from the figure, the concept of a logical address and a physical address is introduced in the file system of this example, which will be described later.

4-4 Physical Data Structure FIG. 8 shows a physical data structure of the flash memory 81 which is a storage element in the memory card 70.
The storage area of the flash memory 81 is based on fixed-length data units called segments. This segment has a size defined as 4 MB (megabyte) or 8 MB per segment, and the number of segments in one flash memory 81 varies depending on the capacity of the flash memory 81.

Then, as shown in FIG. 8A, this one segment is divided into 8 KB (kilobytes) or 16 KB as a fixed-length data unit called a block. In principle, one segment is divided into 512 blocks, so that n = 511 for the block n shown in FIG. 8A. However, in the flash memory 81, the number of blocks as a defect area, which is a damaged area that is not writable, is permitted within a predetermined number range. The above n is smaller than 511.

Of the blocks 0 to n formed as shown in FIG. 8A, the first two blocks 0 and 1 are called boot blocks. However, actually, the first two blocks of the effective block are defined as boot blocks, and there is no guarantee that the boot blocks are blocks 0 and 1. Then, the remaining blocks are user blocks in which user data is stored.

One block is divided into pages 0 to m as shown in FIG. As shown in FIG. 8E, the capacity of one page is 528 (= 512), which is composed of a data area of 512 bytes and a redundant portion of 16 bytes.
+16) fixed length of bytes. The structure of the redundant section will be described later with reference to FIG. The number of pages in one block is 16 pages when the capacity of one block is 8 KB, and 32 pages when the capacity of one block is 16 KB.

The page structure in the blocks shown in FIGS. 8D and 8E is common to the boot block and the user block. Also, the flash memory 8
In 1, the data reading and writing are performed in page units, and the data erasing is performed in block units. The data writing is performed only on the erased page. Therefore, actual rewriting or writing of data is performed for each block.

In the first boot block, as shown in FIG. 8B, a header is stored for page 0, and page 1 stores information indicating the position (address) of the initial failure data. Further, page 2 stores information called CIS / IDS. As shown in FIG. 8C, the second boot block is an area for backup as a boot block.

The redundant part (16 bytes) shown in FIG. 8E has the structure shown in FIG. In the redundant portion, as shown in the figure, the first three bytes from the 0th byte to the 2nd byte are an overwrite area which can be rewritten according to the update of the data content of the data area. In the overwrite area, the 0th byte stores the block status, and the 1st byte stores the data status (Block Flag Data). Also, a conversion table flag (Page Data
Status1) is stored.

In principle, the third to fifteenth bytes are
The content is fixed according to the data content of the current page,
This is an area where information that cannot be rewritten is stored.
The third byte stores a management flag (Block Info) indicating access permission, copy prohibition designation, and the like. A 2-byte area consisting of the fourth and fifth bytes contains a logical address described later.
(LogicAddress) is stored. 6th to 10th byte 5
The byte area is used as the format reserve area.
The subsequent two bytes of the eleventh and twelfth bytes are shared information E for performing error correction on the format reserve.
This is an area for storing the CC. In the remaining thirteenth to fifteenth bytes, data ECC for performing error correction on data in the data area shown in FIG. 8E is stored.

The management flag stored in the third byte of the redundant part shown in FIG.
The content of each bit from bit 7 to bit 0 is defined. Bits 7 and 6 and bits 1 and 0 are reserved (undefined) areas. Bit 5 is "valid"('1'; Free) of access permission for the current block /
A flag indicating "invalid"('0'; Read Protected) is stored. Bit 4 stores a flag for the copy prohibition designation ('1'; OK / '0'; NG) for the current block.

Bit 3 is used as a conversion table flag.
This conversion table flag is an identifier indicating whether or not the current block is a logical-physical address conversion table described later. If the value of bit 3 is set to '0',
The current block is identified as a logical-physical address conversion table, and if it is '0', it is invalid. That is, it is identified that the current block is not a logical-physical address conversion table.

Bit 2 stores a system flag.
If "1", it indicates that the current block is a user block, and if "0", it indicates that it is a boot block.

Here, the relationship between the segments and blocks and the flash memory capacity will be described with reference to FIG. 13 (see the left three columns). The flash memory capacity of the memory card 70 is 4 MB, 8 MB, 16 MB, 32 M
B, 64 MB, or 128 MB. In the case of 4 MB having the smallest capacity, one block is defined as 8 KB, and the number of blocks is 512. That is, 4MB
Has exactly one segment capacity.
Then, if the capacity is 4 MB, 1 block = 8 similarly
After KB capacity is defined, 2 segments = 1024
It becomes a block. As described above, 1 block =
If it is 8 KB, the number of pages in one block is 16 pages. However, with a capacity of 16 MB, it is permitted that both 8 KB and 16 KB exist as a capacity per block. For this reason, there are two types, that is, 2048 blocks = 4 segments (1 block = 8 KB) and 1024 blocks = 2 segments (1 block = 16 KB). When one block is 16 KB, the number of pages in one block is 32 pages.

In the case of capacities of 32 MB, 64 MB and 128 MB, the capacity per block is defined as being only 16 KB. Therefore, 2048 blocks = 4 segments for 32 MB, 4096 blocks = 8 segments for 64 MB, and 8192 for 128 MB.
Block = 16 segments.

4-5 Concept of Physical Address and Logical Address Next, based on the physical data structure of the flash memory as described above, the physical address in the file system of this embodiment is changed according to the data rewriting operation shown in FIG. And the concept of a logical address will be described.

FIG. 10A schematically shows four blocks extracted from a certain segment. A physical address is assigned to each block. The physical address is determined according to the physical arrangement order of the blocks in the memory, and the relationship between a certain block and the physical address associated with the block remains unchanged. Here, for the four blocks shown in FIG. 10A, values of 105, 106, 107,
108 is attached. The actual physical address is 2
Expressed in bytes.

Here, as shown in FIG. 10A, blocks indicated by physical addresses 105 and 106 are used blocks in which data is stored, and physical addresses 107 and 106 are used.
Assume that the block indicated by 108 is an unused block in which data has been erased (that is, an unrecorded area).

The logical address is an address that is allocated so as to accompany the data written to the block. This logical address is an address used by a FAT file system described later. FIG. 10A shows a state in which 102, 103, 104, and 105 are assigned as logical address values in order from the top to four blocks. Incidentally, the logical address is actually represented by 2 bytes.

Here, it is assumed that, from the state shown in FIG. 10A, rewriting or partial erasing is performed, for example, as updating data stored in the physical address 105. In such a case, in the file system of the flash memory, the updated data is not written again to the same block, but the updated data is written to an unused block. That is, for example, as shown in FIG.
Is erased, and the updated data is written to the block indicated by the physical address 107, which has been an unused block (processing).

Then, as shown in the processing, before the data update (FIG. 10A), the physical address 105
Is changed so that the logical address 102 corresponding to the logical address 102 corresponds to the physical address 107 of the block in which the updated data has been written. Accordingly, before the data update, the physical address 10
The logical address 104 corresponding to 7 has been changed to correspond to the physical address 105.

In other words, the physical address is an address uniquely assigned to a block, and the logical address is unique to write data in block units, which follows data once written to the block. Address.

By performing such block swap processing, a certain same storage area (block) is not repeatedly and intensively accessed, and the life of a flash memory having an upper limit of the number of rewrites can be reduced. It can be extended. At this time, by treating the logical address as in the above processing, even if the block written in the data before and after the update is moved by the block swap processing, the same address is obtained from the FAT. The address becomes visible, and subsequent access can be executed properly. Note that, for the purpose of simplifying management for updating on a logical-physical address conversion table, which will be described later, the swap processing of blocks is defined as being completed within one segment. Conversely, block swap processing is not performed across segments.

4-6 Logical-physical address conversion table As can be understood from the description with reference to FIG. 10, the correspondence between the physical address and the logical address changes by performing the block swap processing. Therefore, in order to realize access for writing and reading data to and from the flash memory, a logical-physical address conversion table indicating the correspondence between physical addresses and logical addresses is required. That is, the logical-physical address conversion table is
, A physical address corresponding to the logical address specified by the FAT is specified, and a block indicated by the specified physical address can be accessed. Conversely, if there is no logical-physical address conversion table, it is impossible to access the flash memory by the FAT.

Conventionally, for example, when the memory card 70 is inserted into the set main body, the microprocessor of the set main body checks the storage contents of the memory card 70, so that the set main body performs logical-physical address conversion. A table is constructed, and the constructed logical-physical address conversion table is stored in the RAM of the set body. That is, in the memory card 70,
The information of the logical-physical address conversion table was not stored. On the other hand, in the present example, the logical-physical address conversion table is stored in the memory card 70 as described below.

FIG. 11 conceptually shows a construction form of the logical-physical address conversion table stored in the memory card 70 of the present embodiment. That is, in the present example, for example, according to the ascending order of the logical addresses, table information for storing the corresponding 2-byte physical address is constructed as a logical-physical address conversion table. As described above, both the physical address and the logical address are represented by 2 bytes. This is 12
819 for flash memory with a maximum capacity of 8 MB
Since there are two blocks, at most this 8192
This is based on the requirement that the number of bits be large enough to cover the number of blocks. For this reason, the physical address and the logical address illustrated in FIG. 11 are also expressed in two bytes according to the actual situation. However, here, these two bytes are represented by hexadecimal numbers. That is,
“0x” indicates that the value that follows is in hexadecimal notation. It should be noted that the notation that represents a hexadecimal number by using “0x” is also used in the following description when a hexadecimal number is described. (However, in some drawings, "0x" is omitted in order to prevent the notation from being complicated.)

FIG. 12 shows an example of the structure of a logical-physical address conversion table based on the concept shown in FIG. The logical-physical address conversion table is stored for a certain block in the last segment of the flash memory as shown in FIG. First, as shown in FIG. 12A, of the pages into which the block is divided, pages 0, 1
Are allocated as a logical-physical address conversion table for segment 0. For example,
As described with reference to FIG.
If the capacity is only one segment, the area of only pages 0 and 1 becomes the area of the logical-physical address conversion table. Also, for example, if the flash memory is 8
Since the capacity of the MB has two segments, in addition to pages 0 and 1 assigned as a logical-physical address conversion table for segment 0, pages 2 and
3 pages are allocated as the logical-physical address conversion table for the segment 1.

Thereafter, in accordance with the increase in the capacity of the flash memory, the allocation area of the logical-physical address conversion table for each segment is set for each of the following two pages. Then, in the case of the maximum capacity of 128 MB, there are 16 segments, so the pages up to the segment 15 are allocated as the area of the logical-physical address conversion table at the maximum. Therefore, in a flash memory having a maximum capacity of 128 MB, 30 pages are used.
As the page N shown in (a), N = 29 at the maximum. As can be seen from the above description, the logical-physical address conversion table is managed for each segment.

FIG. 12B shows the structure of a logical-to-physical address conversion table for one segment, in which a data area for two pages is extracted and shown. That is, since the data area of one page is 512 bytes (see FIG. 8E), FIG. 12B shows a state where 1024 (= 512 × 2) bytes are developed. .

As shown in FIG. 12B, the data area for 1024 bytes, which is a data area for two pages, is divided into two bytes, and the area for each two bytes is sequentially allocated from the top to the logical address 0 and the logical address. For one ...
Finally, the 2-byte area of the 991th and 992th bytes from the beginning is assigned to the logical address 4
It is stipulated that the area should be allocated as an area for 95. A physical address corresponding to each logical address is written in these two-byte areas. Therefore, in the logical-physical address conversion table of this example, when the correspondence between the physical address and the logical address is changed by the swap processing of the block by the actual data update or the like, the storage state of the physical address is based on the logical address. Is updated, and the table information is rewritten.

Also, from the remaining 993 bytes to the last 10 bytes,
An area of a total of 32 bytes up to the 24th byte is allocated as an area for storing a physical address of a surplus block. That is, the physical addresses of the 16 surplus blocks can be managed. The surplus block referred to here is, for example, a so-called work block set as an area for temporarily saving data to be rewritten when updating data in block units.

In the table structure shown in FIG. 12, the number of blocks that can be managed is from logical address 0 to logical address 0, although one segment is divided into 512 blocks. There are 496 blocks for the address 495. This is because, in practice, the above-mentioned surplus address is set, and as described above, a defect (unusable area) of a certain number of blocks is permitted in the flash memory. Therefore, in reality, it depends on the existence of a considerable number of defect blocks. Accordingly, in practice, it is sufficient to manage 496 blocks in order to manage blocks for which writing / erasing is effective.

For the block in which the logical-physical address conversion table is stored in this manner, the management flag (FIG. 9) in the redundant portion of each page forming the block is used.
Bit) of the management flag
Is set to '0'. This indicates that the block is a block in which the logical-physical address conversion table is stored.

In the block storing the logical-physical address conversion table, if the contents of the logical-physical address conversion table are rewritten, the block shown in FIG.
The swap processing described in (1) is performed. Therefore, logic-
The block in which the physical address conversion table is recorded is undefined, and it cannot be defined that the logical-physical address conversion table is stored in a specific block. Therefore, the FAT accesses the flash memory and searches for a block in which bit 3 of the management flag is set to “0” so as to identify the block in which the logical-physical address conversion table is stored. Is done. However, considering that the FAT can easily search for the block storing the logical-physical address conversion table, the block storing the logical-physical address conversion table is stored in the flash memory. In the present example, it is specified that the last numbered segment is in the segment with the number. As a result, the FAT can search the logical-physical address conversion table only by searching for the block of the segment to which the last number is assigned. That is, it is not necessary to search all the segments of the flash memory to search the logical-physical address conversion table. The logical-physical address conversion table shown in FIG. 12 is stored when the memory card 70 is manufactured, for example.

Here, the relationship between the flash memory capacity and the size of the logical-physical address conversion table will be described with reference to FIG. 13 again. As described with reference to FIG. 11, the size of the logical-physical address conversion table for managing one segment is 1024 bytes for two pages, that is, 1 KB. Therefore, as shown in the rightmost column of FIG. 13, when the flash memory has a capacity of 4 MB (one segment), the logical-physical address conversion table has a size of 1 KB. When the capacity of the flash memory is 8 MB (2 segments), the logical-physical address conversion table is 2 KB (4 pages). When the capacity of the flash memory is 16 MB, 2048 blocks =
The logical-physical address conversion table is 4 KB (8 pages) for the 4-segment type, and the logical-physical address conversion table is 2 K for the 1024-block = 2 segment type.
B (4 pages). When the capacity of the flash memory is 32 MB (4 segments), the logical-physical address conversion table is 4 KB (8 pages). When the capacity of the flash memory is 64 MB (8 segments), the logical-physical address conversion table is 8 KB (16 pages). When the capacity of the flash memory is 128 MB (16 segments), the logical-physical address conversion table is 16 KB.
(Page 32).

4-7 Directory Structure An example of a directory structure recorded on the memory card 70 is shown in FIG. The main data that can be handled by the memory card 70 includes computer data, moving image data, still image data, message data, audio data, control data, and the like. "VOICE" (message directory), "DCIM" (still image directory), "MOxxxxnn" (moving image directory), "CONTROL" (control directory),
"HIFI" (directory for audio), "PM"
(Directory for information processing device).

Although not shown, sub-directories, files (the above-mentioned database), folders, and the like are arranged under each directory, and have a so-called tree structure. Note that such a directory structure is of course only an example, and a directory structure is actually formed according to the recording status of the information processing apparatus 1 or the like, the type of file to be recorded, and the like.

5. FAT Structure As described in the file system hierarchy of FIG. 7, the file management processing is performed by the FAT. That is, in order to realize the recording / reproducing (data writing / reading) with respect to the memory card 70 by the information processing apparatus 1 having the configuration shown in FIG. 2, the file storage position management by the FAT is referred to in response to the request in the application processing. Then, the above-described logical-physical address conversion is performed, and the actual access is performed. Here, the structure of the FAT will be described.

FIG. 15 shows an outline of a management structure based on the FAT. In this example, the FAT and the logical-physical address conversion table are stored in the memory card 70, but the FAT structure shown in FIG.
This is a management structure within 0.

As shown, the FAT management structure includes a partition table, a free area, a boot sector, a FAT,
It consists of a FAT copy, a root directory, and a data area. In the data area, cluster 2, cluster 3,...
The unit data is shown as, but this cluster is
This is one data unit handled by the FAT serving as a management unit. Generally, in FAT, the cluster size is 4 Kbytes as standard, but this cluster size can be a power of 2 between 512 bytes and 32 Kbytes. In the memory card 70 of this example, as described above, one block is set to 8 Kbytes or 16 Kbytes. However, in the case of the memory card 70 where one block is set to 8 Kbytes,
The cluster handled by the FAT is 8 Kbytes. In the case of the memory card 70 in which one block is 16 Kbytes, the cluster handled by the FAT is 16 Kbytes. That is, 8 Kbytes or 16 Kbytes is a data unit in FAT management, and is one data unit as a block in the memory card 70. From the viewpoint of the memory card, the cluster size handled by the FAT =
This is the block size of the memory card. For this reason,
In the following description of this example, it is assumed that blocks = clusters for simplification.

Then, on the left side of FIG. 15, x... (X + m-1), (x + m) (x + m + 1) as block numbers
(X + m + 2)..., For example, various data for constructing the FAT structure in each block as described above are stored. Actually, each information is not necessarily stored in each physically continuous block.

In the FAT structure, first, the start and end addresses of the FAT partition (up to 2 Gbytes) are described in the partition table. In the boot area, so-called 12-bit FAT, 16-bit FA
The type of T and the FAT structure (size, cluster size, size of each area, etc.) are described.

As will be described later, the FAT is a table indicating the link structure of the clusters constituting each file. For the FAT, a copy is described in a subsequent area. In the root directory, a file name, a leading cluster number, and various attributes are described. These descriptions use 32 bytes per file.

In the FAT, the entries of the FAT correspond to the clusters on a one-to-one basis, and the entry of each cluster describes the link destination, that is, the number of the subsequent cluster. In other words, for a certain file formed by a plurality of clusters (= blocks), the first cluster number is indicated by the directory, and the entry of the first cluster in the FAT indicates the next cluster number. In the next cluster number entry,
Further, the next cluster number is indicated. Thus, the link of the cluster is described in the FAT.

FIG. 16 schematically shows the concept of such a link (the numerical value is a hexadecimal value). For example, assuming that two files “MAIN.C” and “FUNC.C” exist, the leading cluster numbers of these two files are described in the directory as “002” and “004”, for example. For the file “MAIN.C”, the entry of the cluster number “002” is added to the next cluster number “003”.
Is described, and the next cluster number “006” is described in the entry of the cluster number “003”. Further, assuming that the cluster number 006 is the last cluster of the file “MAIN.C”, the cluster number “006”
The entry of “F” indicating the last cluster
FF ”is described. As a result, the file “MAIN.
C ”are stored in the order of cluster“ 002 ”→“ 003 ”→“ 006 ”. That is, assuming that the cluster number matches the block number in the memory card 70, the file “MAIN.C” is stored in the blocks “002”, “003”, and “006” in the memory card 70. Is expressed. (However, the cluster handled by the FAT is handled by the logical address as described above, and therefore does not directly match the physical address of the block)

Similarly, for the file “FUNC.C”, the cluster “004” → “00” is obtained by FAT.
5 "is stored.

The entry of a cluster corresponding to an unused block is "000".

In the directory of each file stored in the area of the root directory, not only the leading cluster number shown in FIG. 16 but also various data are described as shown in FIG. 17, for example. That is, the file name, extension, attribute, change time information, change date information, head cluster number, and file size are each described by the number of bytes shown.

The sub-directory below a certain directory is stored in the data area, not in the area of the root directory in FIG. That is, the subdirectory is treated as a file having a directory structure. In the case of a subdirectory, the size is unlimited, and an entry for itself and an entry for the parent directory are required.

In FIG. 18, there is a file "DIR1" (attribute = directory: sub-directory) in a certain root directory.
An example of the structure in a case where there is an “R2” (attribute = directory: that is, a subdirectory) and a file “FILE” further exists therein. That is, in the root directory area, the head cluster number as the file “DIR1” which is a subdirectory is indicated, and the clusters X, Y, and Z are linked by the above-described FAT. As can be seen from this figure, the subdirectories "DIR1" and "DIR2" are treated as files and incorporated into the FAT link.

6. Interface between Memory Card and Information Processing Apparatus A serial interface system configuration between the memory card 70 and the memory card interface 28 of the information processing apparatus 1 will be described with reference to FIG. Memory card 70
The control IC 80 includes a flash memory controller 80a, a register 80b, a page buffer 80c, a serial interface 80d as shown in FIG.
As each block.

The flash memory controller 80a
Data transfer is performed between the flash memory 81 and the page buffer 80c based on the parameters set in the register 80b. The data buffered in the page buffer 80c is stored in the serial interface 80d.
The data transferred to the memory card interface 28 of the information processing apparatus 1 via the data interface 1, and the data transferred from the memory card interface 28 of the information processing apparatus 1 are buffered to the page buffer 10c via the serial interface 80d.

The memory card interface 28 has a file manager 60, a transfer protocol interface 61, and a serial interface 62 as an interface structure for the memory card 70. The file manager 60 manages files in the memory card 70. For example, in the system of this example, a management file for managing the main data file is stored in the memory card 70, but the information processing apparatus 1 reads the management file from the loaded memory card 70 and
The PU 22 will form the file manager 60. Access to the memory card 70 is executed according to the file manager 60. The transfer protocol interface 61 includes a register 80b, a page buffer 80c.
Perform access to. Serial interface 6
2 is three signal lines to the memory card 70, that is, S
CLK (serial clock), BS (bus state),
In SDIO (serial data input / output), a protocol for performing arbitrary data transfer is defined.

The read / write access to the memory card 70 (flash memory 81) by the information processing device 1 is performed by the operation of each unit in the above configuration.

7. File System API In the above description, an example of the memory card 1 is given as a medium loaded in the information processing apparatus 1, and its configuration and FA
T has been described. However, in practice, for example, a memory card equipped with a flash memory is provided by a variety of different products from respective manufacturers, and many employ a FAT file system. Here, various memory cards, that is, FAT
Although the system is adopted, media provided as separate products having different structures and shapes and file system APIs are also unique are temporarily assumed to be media # 1,
# 2... For example, products called “Memory Stick”, “SmartMedia”, “Compact Flash (registered trademark)”, “SD card”, etc. correspond to media # 1, # 2,. I do.

In order to cope with such various media, in the information processing apparatus 1 of the present embodiment, the FAT file system API is configured as shown in FIG.
That is, each of the media # 1, # 2,... Has a library as a unique file system API and a common library as a common file system API. Each library corresponding to each of the media # 1, # 2,... Is not an API as an entity, but a function as an API is included in the common library.

As a function, the common library performs, for example, for opening, closing, reading, and writing a file, for example, “General File Open”, “General File Cl
ose "," General File Read "," General File Write ", etc. Each individual library also has a function for each corresponding media. For example, media # 1FA
In T library, "# 1 File Open""# 1 File Cl
ose ","# 1 File Read ","# 1 File Write ", etc. . However, in actual operation, each individual library replaces the function of the common library with its own function, and then causes the common library to function as a file system API. Specifically, media # 1
To open a file for
The FAT library uses the function "Ge
neral File Open ”and own function“ # 1 File Open ”
By replacing the common library with media # 1F
It will be used as an AT library. The same applies to other individual libraries. In other words, it can be said that each individual library functions by hacking the common library. From the user's point of view (assuming that the function can be confirmed on the display), all media are similarly opened with a function as “File Open”, but the substance of “File Open” is , According to each media.

Such a FAT file system API
In, first, the table initialization shown in FIG. 21A is performed as an initial operation. In this case, the device used in the information processing apparatus 1 is recognized in step F101. For example, it is assumed that memory cards # 1 and # 3 are set as devices to be used. Next, in step F102, a function table used for file opening or the like in each device is prepared. For example, "# 1 FileOpen", "# 1 File Close", "# 1
"File Read", "# 1 File Write", "# 3 File Open", "# 3 File Clos" for media # 3
A function table having information such as “e”, “# 3 File Read”, and “# 3 File Write” is prepared.

The processing when media #n is loaded is as shown in FIG. 21B. When loading of media #n is recognized in step F201, the function table of the common library is stored in step F202. #NF
The AT library performs a process of replacing the function table with its own function table. As a result, the common library has media #n
Is a FAT file system API corresponding to. According to the configuration of FIG. 3, in this state, the common library is the memory card 70 corresponding to the medium #n.
And a device, that is, a memory drive is controlled and accessed via the MS library.

[0094] Such a FAT file system API
According to the structure, the actual API is only the common library, and in order to correspond to each medium, each individual library only needs to replace the function table.
The I-scale does not become large-scale, and can be adapted to various media, while maintaining expandability.

Although the embodiment has been described above, the API structure is not limited to the above example, and can be applied even if it is not necessarily a FAT system. The devices to which the present invention can be applied are not only portable information processing devices but also various types.

[0096]

As will be understood from the above description, according to the present invention, each individual library which is an individual file system API for each storage means, and a common file system API for each storage means are provided. And a common library. Then, each individual library replaces the function of the common library with its own function when operating the corresponding storage means, thereby forming a file system that functions using the common library. In this way, since each individual library uses the common library as an actual API,
File system API scale can be reduced, for example PD
There is an effect that it can be suitable for mounting on the A-device or the like, and can be compatible with various types of storage means.

[Brief description of the drawings]

FIG. 1 is a plan view of an information processing apparatus according to an embodiment of the present invention;
It is a right side view, a left side view, and a top view.

FIG. 2 is a block diagram of the information processing apparatus according to the embodiment;

FIG. 3 is an explanatory diagram of an OS structure of the information processing apparatus according to the embodiment;

FIG. 4 is an explanatory diagram of a database structure handled by the information processing apparatus according to the embodiment;

FIG. 5 is a plan view, a front view, a side view, and a bottom view showing the external shape of the memory card according to the embodiment;

FIG. 6 is an explanatory diagram of an internal structure of the memory card according to the embodiment;

FIG. 7 is an explanatory diagram of a file system processing hierarchy according to the embodiment;

FIG. 8 is an explanatory diagram of a physical data structure of the memory card according to the embodiment;

FIG. 9 is an explanatory diagram of a management flag of the memory card according to the embodiment.

FIG. 10 is an explanatory diagram of the concept of a data update process and a physical address and a logical address in the memory card of the embodiment.

FIG. 11 is an explanatory diagram of a management form of a logical-physical address conversion table according to the embodiment;

FIG. 12 is an explanatory diagram of a structure of a logical-physical address conversion table according to the embodiment;

FIG. 13 is an explanatory diagram showing the relationship between the flash memory capacity of the memory card / the number of blocks / the capacity of one block / the capacity of one page / the size of the logical-physical address conversion table.

FIG. 14 is an explanatory diagram of a directory structure of the memory card according to the embodiment;

FIG. 15 is an explanatory diagram of a FAT structure.

FIG. 16 is an explanatory diagram of a cluster management mode using FAT.

FIG. 17 is an explanatory diagram of the contents of a directory.

FIG. 18 is an explanatory diagram of a storage mode of a subdirectory and a file.

FIG. 19 is an explanatory diagram of an interface configuration between the information processing device and the memory card according to the embodiment;

FIG. 20 is a FAT file system API according to the embodiment;
FIG.

FIG. 21 is a FAT file system API according to the embodiment;
3 is a flowchart of the process in FIG.

[Explanation of symbols]

Reference Signs List 1 information processing device, 2 display unit, 3a, 3b, 3c operator, 4 speakers, 5 microphone, 6 imaging unit,
7 memory slots, 8 IEEE1394 terminals, 9
USB terminal, 10 headphone terminal, 11 line input terminal, 12 line output terminal, 21 system controller, 22 CPU, 23 flash ROM, 24
D-RAM, 25 USB interface, 26 I
EEE1394 interface, 27 display control unit,
28 memory card interface, 29 audio interface, 70 memory card

Claims (2)

[Claims] 1. An information processing apparatus capable of accessing a plurality of different types of storage means having the same file system, comprising: an individual library serving as an individual file system API for each storage means; Each of the individual libraries uses the common library by replacing the function of the common library with its own function when operating the corresponding storage means. An information processing apparatus characterized in that the information processing apparatus is configured to function. 2. A file system corresponding to a plurality of different storage units having the same file system, each individual library serving as an individual file system API for each storage unit, and a common file for each storage unit. A common library, which is a system API, wherein each of the individual libraries functions using the common library by replacing the function of the common library with its own function when operating on the corresponding storage means. A file system characterized in that: