JP2002006981A - Digital control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To structure as a synchronous order circuit and to realize high processing capability which fits to the response speed of a hardware about a digital control device which realizes a prescribed function in cooperation with input and output devices. SOLUTION: This is structured as a synchronous order circuit which works synchronously to a clock signal, and it has a main processing means which generalizes the movement of one device or more N by conducting a prescribed process based upon RISK logic and accumulative logic and has a clock generating means which supplies clock signals to the main processing means. The main processing means checks whether access is correct or not to one specified device or more n (<=N) in one device or more N. The clock generating means changes the frequency of the clock signals, and sets the frequency of the clock signals under the maximum frequency which the result of the main processing means's check is true under the clock signals of the frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital control device configured as a synchronous sequential circuit and realizing a predetermined function by accessing an input / output device based on wiring logic or storage logic.

[0002]

2. Description of the Related Art In recent years, many electronic devices are equipped with inexpensive and high-performance microprocessors, and a variety of added values are aggressively given the technological development and competition of manufacturers of these electronic devices. It is included. In addition, among such electronic devices, in particular, for a terminal device of a mobile communication system, for example, access to the Internet, display of a color image, and other various functions are strongly required to be achieved at low cost, And the processing power to be achieved by the on-board microprocessor is also increasing.

FIG. 7 is a diagram showing a configuration example of a terminal device equipped with a microprocessor. In the figure, an antenna terminal of a radio unit 42 is connected to a feed end of an antenna 41, and a modulation input and a demodulation output of the radio unit 42 are connected to a modulation output and a demodulation input of a baseband processing unit 43.
The demodulated output and the modulated input of the baseband processing unit 43 are connected to a receiver 45 and a microphone 46 via an audio front end unit 44, respectively. Control terminals of the radio unit 42, the baseband processing unit 43, and the audio front end unit 44 are connected to corresponding input / output ports of the control unit 50.

The control unit 50 includes a main control unit 51 configured as an LSI, a bus 52 connected to a bus terminal of the main control unit 51, and an external device connected to the main control unit 51 via the bus 52. Interface RAM 53, external RAM 5
4 and an external ROM 55, and connected to this bus 52,
The input / output interface unit 56 forms an input / output port connected to a corresponding control terminal of the radio unit 42, the baseband processing unit 43, and the audio front end unit 44.

A main controller 51 includes a processor (CPU) 62 having an internal memory 61 as a part of a main memory, a frequency setting circuit 63 to which a set value F described later is given, and an output of the frequency setting circuit 63. A reference clock signal having a frequency of fin is provided from the outside and a clock generator 64 whose output is connected to a clock terminal of the processor 62.

In a conventional example having such a configuration, the processor 62 executes a program stored in the internal memory 61 and the external ROM 55 corresponding to the main memory described above, and in the process, the external interface RAM 53
And the external RAM 54 are appropriately accessed, and the operations of the radio unit 42, the baseband processing unit 43, and the audio front-end unit 44 are controlled via the input / output interface unit 56. And transmission and reception of a call signal based on the channel control procedure.

The processing to be performed by the processor 62 under the stored program control method in which the above-described program is executed is not a feature of the present invention and can be realized by applying various known techniques. Therefore, the description is omitted here. The main control unit 5
The frequency setting circuit 63 provided with 1 is provided with a setting value F which is determined in advance as a design value or an actual measurement value and is proportional to the frequency of a clock signal which gives a speed at which the processor 62 executes the above-described program.

In accordance with the set value F, the frequency setting circuit 63 gives the clock generator 64 a frequency division ratio m that is inversely proportional to the set value F. The clock generation unit 64 calculates a frequency according to a reference clock signal supplied from the outside and the frequency division ratio m.
A clock signal having a frequency fc given by the following equation with respect to the frequency fin of the reference clock signal is generated, and this clock signal is provided to the processor 62.

Fc = fin · m / n (1) Further, the processor 62 includes an external interface RAM.
The access to the external RAM 53, the external RAM 54, the external ROM 55, and the input / output interface unit 56 is given by the following equation with respect to the above-described clock signal cycle Tc (= 1 / fc) and a predetermined integer N. Try a standard bus cycle Tbus which is achieved with high accuracy.

Tbus = NTc / 2 Also, external interface RAM 53, external RAM 5
4. External ROM 55 and input / output interface unit 56
Those which cannot respond within the above-described standard bus cycle Tbus provide a wait signal to the processor 62 via the bus 52 for a period during which the bus cycle Tbus is to be extended.

The processor 62 suspends the start of the following bus cycle during the period when the wait signal is being given. That is, as long as the above-mentioned set value F and the frequency fin of the reference clock signal are both appropriate, the processor 62 outputs the external interface RAM via the bus 52.
53, the external RAM 54, the external ROM 55, and the input / output interface 56
2. The operations of the baseband processing unit 43 and the audio front end unit 44 can be stably and accurately controlled.

Therefore, the user of the terminal device has a high added value under the channel control performed by the processor 62 as described above based on the stored program control method under various environmental conditions such as temperature, and Various communication services are provided.

[0013]

By the way, in the above conventional example, the external interface RAM 53, the external RAM
54, external ROM 55 and input / output interface unit 5
Even if the deviation associated with the characteristic of No. 6 is the maximum value, under the environmental conditions where the operation is to be guaranteed, the processor 62 surely connects the external interface RAM 53, the external RAM 54, the external ROM 55 and the input / output interface unit 56 to each other. The set value F described above has been set to a value that can be accessed.

In the following, the value M expressed by the following equation with respect to these set value F and the maximum set value Fmax that can be set within the range of the performance of the processor 62 is simply referred to as "margin". It shall be. M = Fmax-F That is, the frequency fc of the clock signal to be supplied to the processor 62 is set to a value lower than the frequency at which the above-mentioned margin M is secured and the maximum processing speed achievable by the processor 62 is given. Was.

Further, an external interface RAM 53,
The response speed of the external RAM 54, the external ROM 55, and the input / output interface unit 56 depends on the characteristics and remaining amount of the battery that supplies the driving power to them, the temperature and other environments, and the deviation of the performance of the components actually mounted. Can be large depending on However, since the processing capability of the processor 62 must be high enough to secure the above-mentioned margin M, even if the margin M becomes unnecessarily large, it is not effectively used. I never did.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital control device capable of realizing a high processing capacity adapted to the actual response speed of the hardware without largely changing the configuration of the hardware. .

[0017]

A first aspect of the present invention is a principle block diagram of the present invention.

According to the first aspect of the present invention, the main processing means 1
1 performs predetermined processing based on wiring logic or storage logic in synchronization with the clock signal supplied by the clock generation means 12, and performs single or multiple N devices 10- based on the processing procedure. Controls 1 to 10-N operations.
Further, in the course of such processing, the main processing unit 11 normally accesses one or a plurality of n (≦ N) specific devices among these devices 10-1 to 10-N. It is determined whether or not there is. The clock generating means 12 varies the frequency of the above-described clock signal based on a predetermined algorithm, and reduces the frequency to below the maximum frequency at which the result of the determination made by the main processing means 11 under the clock signal of that frequency becomes true. Set the frequency of the clock signal.

That is, the higher the responsiveness of the single or plural specific devices described above, the higher the frequency of the clock signal is set. Therefore, the processing capacity of the main processing unit 11 is increased on average, compared to the conventional example in which this frequency is constant regardless of the response of the specific device described above.

According to the second aspect of the present invention, the processing capacity required for each processing which can be performed by the main processing means 11 is registered in the processing capacity storage means 13 in advance. The clock generation means 12 grasps the processing actually performed by the main processing means 11 and, in response to the processing, stores the processing capacity storage means 1
3, the frequency of the clock signal is set to a value that ensures the processing capability.

That is, the surplus processing capacity of the main processing means 11 is utilized properly and effectively. Therefore, the desired performance can be maintained and the power consumption can be saved with higher accuracy than when the processing capacity of the main storage unit 11 is kept constant. According to the third aspect of the invention, when the result of the determination made by the main processing unit 11 is false, the clock generation unit 12 causes the main processing unit 11 to access one or a plurality of n specific devices. Set the frequency of the clock signal to a specific frequency that is guaranteed to be normal.

That is, if any trouble occurs due to the incorrect frequency of the clock signal set or updated by the clock generating means 12, the frequency of the clock signal is changed to the above-mentioned specific frequency. Set automatically. Thus, the duration and extent to which such failures propagate is minimized, and unnecessary loss of function and performance is avoided.

According to the first sub-concept of the present invention, the remaining amount monitoring means 15 monitors the remaining amount of the battery 14 for supplying the driving power. Clock generation means 1
2 compares the remaining amount of the battery 14 monitored in this way with a prescribed lower limit, and when the former falls below the latter, the main processing means 11 sends a single or plural n specific devices to The frequency of the clock signal is set to a specific frequency at which normal access is guaranteed.

That is, in a state where the remaining amount of the battery 14 becomes lower than the above lower limit, the increase in power consumption that can be accelerated due to the setting of the frequency of the clock signal to a large value is automatically increased. Avoidance. Therefore, the operating time to be continued in a state where the remaining amount of the battery 14 is small does not significantly decrease due to the application of the inventions of the first and second aspects.

In the invention of the second sub-concept of the first and second aspects of the present invention, the temperature monitoring means 17 monitors the temperature of a portion thermally coupled to the main processing means 11. The clock generation means 12 compares the temperature monitored in this way with a prescribed upper limit value, and when the former exceeds the latter, the main processing means 11 normalizes access to one or a plurality of n specific devices. The frequency of the clock signal is set to a specific frequency that is guaranteed to be performed at the same time.

That is, in a state where the temperature of the above-mentioned portion has risen to such an extent that the operating temperature is not guaranteed, the main processing means 1
A further increase in temperature due to the frequency of the clock signal to be supplied to 1 being updated to a large value is avoided. Thus, a stable maintenance of a given performance is achieved in parallel with a flexible adaptation to environmental conditions.

According to the first aspect of the present invention, the man-machine interface means takes a man-machine interface for notifying the frequency of the clock signal set by the clock generation means. That is, the frequency of the clock signal actually supplied to the main processing unit 11 or the processing capability of the main processing unit 11 is appropriately notified to the operator according to the frequency.

Therefore, it is possible to save labor and increase the efficiency of the work related to the adjustment and the failure recovery test performed at the time of shipment, and to easily grasp the frequency fc of the clock signal at the time of occurrence of any failure. Even if the failure occurs only once, it is easy to determine the cause. According to the second aspect of the present invention, all or a part of the single or plural specific devices is configured as a RAM. The main processing means 11 performs all of the single or plural n specific devices based on a known correlation to be established between information previously written to the RAM and information read from the RAM. Alternatively, it is determined whether or not access to a part is normally performed.

That is, for a specific device configured as a RAM, the main processing unit 11 writes data as described above due to the hardware and software configuration as long as the above-described correlation is reliably given. Even when the read information is different from the read information, or when the information is written or the storage area to be read is different, the above-described determination can be performed with high accuracy.

Therefore, it is possible to set a suitable frequency of the clock signal to be supplied to the main processing unit 11 with high accuracy, in addition to the flexible adaptation to various configurations of hardware and software. In the third invention related to the inventions described in claims 1 to 3, all or a part of the single or multiple n specific devices is selected from among the single or multiple N devices 10-1 to 10-N. The total processing capacity to be provided to the main processing unit 11 is specified in advance in descending order according to the frequency and / or form of the access performed by the main processing unit 11.

That is, the frequency of the clock signal to be supplied to the main processing means 11 is automatically maintained at a value at which the processing capacity required for the processing to be actually performed by the main processing means 11 is accurately achieved. You. Therefore, an increase in power consumption, which may occur when the frequency of the clock signal is set to an unnecessarily large value, is avoided, and running costs are reduced and overall reliability is improved.

[0032]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 is a diagram showing the first to seventh embodiments of the present invention. The difference between the present embodiment and the conventional example shown in FIG. 7 is that a main controller 20 is provided instead of the main controller 51.

The differences between the main control unit 20 and the main control unit 51 are as follows. A frequency setting circuit 21 is provided instead of the frequency setting circuit 63. A specific output port of the processor 62 is connected to the control input of the frequency setting circuit 21; FIG. 3 is an operation flowchart of the first to third embodiments of the present invention.

The operation of the first embodiment of the present invention will be described below with reference to FIGS. Among the software which is executed by the processor 62 and realizes the functions to be provided as the terminal device, a program for giving a procedure of an initialization process to be performed at the time of startup, and a constant to be referred in the process of the initialization process. Is stored in the internal memory 61 in advance, or is stored in the internal memory 61 by block transfer from a specific storage area of the external ROM 55 immediately after the start.

The technique for realizing such block transfer is not a feature of the present invention but can be realized by applying various known techniques.
Here, the description is omitted. Also, the internal memory 61
In the specific storage area, the external interface RAM 53
And the external RAM 54, are individually arranged in both or one of which the time (or the number of bus cycles) required for the access performed by the processor 62 via the bus 52 is the largest, and in the process of processing described later. Pointers (columns) each indicating a specific storage area to be accessed are stored in advance as the above-described constants.

In the process of the above-described initialization processing, the processor 62 sets a predetermined initial value (here, “0” for simplicity) as an offset value Δ to be given to the frequency setting circuit 21 together with the above-mentioned set value F. (FIG. 3 (1)). The frequency setting circuit 21 obtains a value inversely proportional to the sum of the set value F and the offset value Δ as the above-described division ratio m, and calculates the division ratio m as the clock generation unit 6.
Give to 4.

The frequency of the clock signal generated by the clock generation unit 64 and supplied to the processor 62 is calculated by the above-described equation (1) with respect to the frequency division ratio m and the frequency fin of the reference clock signal. It is set to a given value fc. Further, the processor 62 and the internal memory 61
Is smaller than the maximum frequency of the clock signal that can be generated by the clock generation unit 64 in accordance with the above-described set value F and the offset value Δ. Frequency fcm
It is configured in advance as a circuit in which n has a sufficiently large value.

Further, the processor 62 performs the following processes (1) to (7) in the process of the above-described initialization process. (1) Write known information via the bus 52 to all the storage areas indicated by the (rows) of the pointers (FIG. 3).
(2)). (2) The information stored in these storage areas is read, and it is determined whether or not the information is equal to the previously written known information (FIG. 3 (3)).

(3) The following processes (4) to (6) are omitted only when one of the results of these determinations is false. (4) Update the offset value Δ to a large value over a specified increment δ (> 0, ≪Δ) (FIG. 3 (4)). (5) Waiting for the time required for the frequency of the clock signal generated by the clock generation unit 64 to reach the steady value in accordance with the offset value Δ updated in this manner (FIG. 3)
(5)) Thereafter, the above-mentioned processing (1) and thereafter are repeated.

(6) The above process (2) and subsequent processes are repeated. (7) A predetermined margin Δm from the latest offset value Δ
The offset value Δ is updated to a value Δf obtained by subtracting (0 or an integer multiple of the increment δ) (FIG. 3 (6)). In the following, the updated offset value is simply referred to as “offset value Δf” for simplicity.

That is, the frequency fc of the clock signal generated by the clock generator 64 is
And the maximum value at which access to the storage area indicated by the above-mentioned pointer (column) is normally performed by the processor 62, or a desired margin is secured for this maximum value. Is automatically set to a large value.

As described above, according to the present embodiment, the access to the storage areas indicated by the above-mentioned pointers (columns) corresponds to the deviation of the characteristics and performance of the external interface RAM 53 and the external RAM 54 to be formed in these storage areas. The processing is performed at high speed within the range of the performance of the processor 62 while flexibly adapting to Therefore, the frequency fc of the clock signal is equal to the external interface RAM 53 and the external R
Since the value is set to a constant value regardless of the characteristics and performance of the AM 54, a predetermined value is set under the initiative of the processor 62 as compared with the conventional example in which the surplus performance of the processor 62 is not utilized at all. The performance of the terminal device having the above function is improved on average without changing the basic configuration of the hardware.

Hereinafter, a second embodiment of the present invention will be described. The difference between this embodiment and the first embodiment described above is that, as shown in FIG. 4, a set of records consisting of the following fields is defined, and the contents are registered in advance as known information. That is, the control table 61T is provided in a specific storage area of the internal memory 61.

Individual states that are previously determined as software that performs the above-described channel control and other functions, are identified by the processor 62 during the execution of the software, and can be taken by a wireless terminal equipped with these functions. "State identifier" field storing a "state identifier" indicating the offset value Δ in proportion to the processing capability that the processor 62 should have in the state indicated by these “state identifiers”
"Proper offset value" field in which an offset value .DELTA.opt (hereinafter referred to as "proper offset value .DELTA.opt") given in advance is stored. FIG. 4 is an operation flowchart of the second and third embodiments of the present invention. .

Hereinafter, the operation of the second embodiment of the present invention will be described with reference to FIGS. 2, 4 and 5. The feature of the present embodiment lies in the following processing procedure performed by the processor 62. When the processor 62 specifies the above-described offset value Δf in the process of the above-described initialization processing, the processor 62 holds the offset value Δf in a specific storage area of the internal memory 61.

Further, the processor 62 appropriately obtains and updates the offset value Δf to be given to the frequency setting circuit 21 by performing the following processes (a) to (e). (a) By executing the above-mentioned software, the above-mentioned state is identified. (b) Each time the status is updated, a record in which a status identifier indicating a new status is stored in the “status identifier” field among the records of the control table 61T is specified (FIG. 5 (1)).

(C) "Appropriate offset value" of this record
The appropriate offset value Δopt, which is the value of the field, is obtained (FIG. 5 (2)). (d) The appropriate offset value Δopt is compared with the offset value Δf previously held. (e) These proper offset value Δopt and offset value Δ
The smaller one of f and f is given to the frequency setting circuit 21 (FIG. 5 (3)).

The operations of the frequency setting circuit 21 and the clock generator 64 are the same as those of the first embodiment described above, and a description thereof will be omitted. As described above, according to the present embodiment, the surplus processing capacity of the processor 62 is effectively used, and the processing capacity is automatically set to an appropriate value to be secured in the above-described state.

Therefore, as compared with the case where such a processing capacity is simply set to a constant value larger than that of the conventional example, it is possible to reduce the power consumption while maintaining the desired performance with high accuracy. Hereinafter, the operation of the third embodiment of the present invention will be described with reference to FIGS. The difference between this embodiment and the above-described first and second embodiments lies in the following processing procedure performed by the processor 62.

The specific storage area of the internal memory 61 satisfies all of the following conditions and has the external interface RA
An offset value (hereinafter, referred to as a “nominal offset value”) S calculated in advance as a value adapted to a deviation that may accompany the characteristics of the M53, the external RAM 54, the external ROM 55, and the input / output interface unit 56 is stored. The external interface RAM 53 and the external RA
A standard value of the time (number of bus cycles) required when the processor 62 accesses the M54, the external ROM 55, and the input / output interface unit 56 via the bus 52 is secured.

The minimum performance required for a wireless terminal device is guaranteed. The processor 62 outputs the “clock signal” in accordance with the result of the determination process performed in the process of the internal process in the process of executing the above-described software, or information or an interrupt request given by some external hardware. Is identified, the above-mentioned nominal offset value S is provided in place of the offset value Δf previously given to the frequency setting circuit 21 (see FIG. 3 (a), FIG. 5 (a)), and subsequently, the process of updating the offset value Δf is restricted (FIGS. 3 (b), 5 (b)).

In other words, if any malfunction or failure occurs due to the improper setting of the updated offset value Δf under the initiative of the processor 62, the offset value Δf is immediately set to the nominal offset. It is changed to the value S. Therefore, the period and range in which these malfunctions and failures propagate are limited to a minimum, and unnecessary reduction in function and performance is avoided.

The present embodiment does not disclose the procedure of processing to be performed by the processor 62 to identify the above-described malfunction or failure as an event, and the configuration and operation of hardware associated with the processor 62. . However, the hardware configuration and operation are not the features of the present invention in conjunction with such processing procedures, and, for example, runaway of the processor 62 and other abnormal operations such as a watchdog timer are detected. Since it can be realized under the application of various known techniques described above, the description thereof is omitted here.

Hereinafter, a fourth embodiment of the present invention will be described. The difference between the present embodiment and the above-described first to third embodiments is that the main control unit 2 is replaced with the main control unit 2.
0A, and a threshold table 61V described later is arranged in a predetermined storage area of the internal memory 61.
The difference between the configurations of the main control unit 20A and the main control unit 20 is that, as indicated by the dashed line and the dotted line in FIG.
In that a monitoring unit 30 connected to the corresponding input / output port is provided.

The monitoring control unit 30 is composed of the elements listed below. An analog switch 32 having a control input terminal connected to a corresponding output port of the processor 62 in addition to an output of the temperature sensor 31 and two input terminals connected to terminals of a battery (not shown). A / D converter (A / D) 33 which is arranged at the subsequent stage of the switch 32 and whose output terminal is connected to the corresponding input port of the processor 62. Further, as shown in FIG. It is configured as a set of records consisting of fields.

"Temperature" field in which a value that can be taken by a temperature T around a battery (not shown) for supplying drive power is stored in advance as a discrete value with a predetermined accuracy. "Temperature" of the same record The remaining amount of the battery is such that the temperature around the battery is equal to the value of the field, and the above-mentioned offset value Δf is restricted from being set to a value exceeding the above-described nominal offset value S. The operation of the fourth embodiment of the present invention will be described below with reference to FIGS. 2 and 6 below a "threshold" field in which the nominal value Vth of the electromotive force of the battery in the lowered state is stored in advance.

The feature of this embodiment is that the processor 62 determines the point in time at which the above-mentioned nominal offset value S is to be applied instead of the offset value Δf previously applied to the frequency setting circuit 21. The procedure is as follows. In the monitoring unit 30, the temperature sensor 31 outputs a monitor signal indicating the above-described temperature around the battery as the instantaneous value v of the voltage.

The processor 62 gives the analog switch 32 a selection signal alternately indicating one of the instantaneous value v of the monitor signal and the terminal voltage Vb of the battery as binary information at a predetermined frequency. The analog switch 32 selects one of the instantaneous value v and the terminal voltage Vb corresponding to the logical value of the above-described selection signal, and supplies the selected value to the A / D converter 33.

The A / D converter 33 compares the instantaneous value v and the terminal voltage Vb alternately selected by the analog switch 32 in this way with a predetermined word length (here, for simplicity, it is assumed that the bit length is 8 bits). Assume that this is the case). The processor 62 converts the instantaneous value v indicated by the digital signal into a corresponding temperature T, and identifies a record in the threshold table 61V in which the value of the “temperature” field is equal to the temperature T.

Further, the processor 62 acquires the value Vth of the "threshold" field of the record, and determines whether or not the above-mentioned terminal voltage Vb falls below this value Vth. Further, the processor 62 continues to supply the above-described nominal offset value S to the frequency setting circuit 21 instead of the above-described offset value Δf as long as the result of the determination is true.

That is, the terminal voltage V of the battery is reduced to a level below the threshold Vth given in advance as a value adapted to the temperature.
In the state where b has decreased, it is possible to avoid an increase in power consumption or a rapid decrease in the remaining power due to the frequency fc of the clock signal to be supplied to the processor 62 being set to a large value. You. Therefore, even when the remaining amount of the battery is low, a longer time for which the standby state or the call state is to be maintained is secured than in the first to third embodiments described above.

In this embodiment, the remaining amount of the battery is indirectly monitored as the terminal voltage of the battery. However, the present invention is not limited to such a configuration. For example, by applying the following configuration,
The remaining amount of the battery may be obtained without providing 0.

As shown by the dotted line in FIG. 5, in the state indicated by the value of the “state identifier” field, the processor 62 according to the corresponding appropriate offset value Δopt
Is provided with a “unit power” field in which the total power consumed per unit time under the clock signal supplied to the control table 61Tr is added in advance.

The processor 62 determines whether the state indicated by the value of each “state identifier” field lasts,
Among the records of the control table 61Tr, the complement of the product sum of the value and the value of the “unit power” field of the common record is obtained for “the nominal value of the amount of power that can be supplied by the battery”. The operation of the fifth embodiment of the present invention will be described below with reference to FIGS.

The difference between this embodiment and the fourth embodiment lies in the following processing procedure performed by the processor 62. When obtaining the instantaneous value v by cooperating with the monitoring unit 30, the processor 62 converts the instantaneous value v into a corresponding temperature T. Further, the processor 62 determines whether or not the temperature T belongs to a predetermined operating temperature range. If the determination result is false, the above-described nominal offset is substituted for the offset value Δf. The value S is given to the frequency setting circuit 21.

That is, in a state where the temperature T has risen to an extent that the operating temperature is not guaranteed, the temperature T further increases due to the fact that the frequency fc of the clock signal supplied to the processor 62 is updated to a large value. Ascent is avoided. Therefore, according to the present embodiment, the performance is stably maintained while flexibly adapting to the environmental conditions.

In the present embodiment, no part where the above-mentioned temperature T should be monitored is specified at all. But,
Any place where the temperature T should be monitored is a place where the temperature increases in accordance with an increase in the frequency fc of the clock signal, such as the surface of the package of the main control units 20 and 20A. Location.

Hereinafter, the operation of the sixth embodiment of the present invention will be described with reference to FIGS. 2, 3 and 5. The present embodiment is different from the above-described first to fifth embodiments in that the processor 62 performs the following processing. Processor 62
Performs the following processing every time the offset value Δf to be given to the frequency setting circuit 21 is updated.

The latest offset value Δf (S) is represented by the frequency f of the clock signal represented by the offset value Δf (S);
c (FIGS. 3A and 5A). Output the frequency fc to a display (not shown) via the bus 52 and the external interface RAM 53 (FIGS. 3B and 5B).

That is, the frequency fc of the clock signal actually supplied to the processor 62 is notified to the operator as appropriate. Therefore, it is possible to save labor and increase the efficiency of the work related to the adjustment performed at the time of shipment and the recovery test for failure, and to easily obtain the frequency fc of the clock signal at the time of occurrence of any failure, and to perform one-shot operation. It is easy to find out the cause of the trouble or malfunction that has occurred in the machine.

In the present embodiment, the frequency fc of the clock signal is always displayed on the display. However, the present invention is not limited to such a configuration, and the frequency fc may be displayed only when a specific instruction is given by the operator or when a predetermined event occurs, for example. Good.

In this embodiment, the frequency fc of the clock signal is displayed as an absolute value. However, the present invention is not limited to such a configuration, and the frequency fc may be displayed, for example, in the following form. The deviation of the frequency fc from the standard value The value normalized by the standard value of the frequency fc Further, in the present embodiment, the frequency fc of the clock signal is displayed via the above-described display.

However, the present invention is not limited to such a configuration. For example, the above-described frequency fc may be converted into voice information, or a predetermined frequency may be transmitted to a terminal device connected via some communication path. May be transmitted. Hereinafter, a seventh embodiment of the present invention will be described.

The difference between this embodiment and the above-described second embodiment is that a control table 61Ti described below is provided instead of the control table 61T. Hereinafter, the operation of the seventh embodiment of the present invention will be described with reference to FIGS. The feature of this embodiment lies in the value of the proper offset value Δopt stored in the “proper offset value” field of the control table 61Ti.

In the "proper offset value" field of each record of the control table 61Ti, the state indicated by the state identifier stored in the "state identifier" field of the common record is individually calculated in advance based on the following procedure. The offset value Δ that gives the processing capability to be provided to the processor 62 and is stored as an appropriate offset value Δopt.

A combination of the external interface RAM 53, the external RAM 54, the external ROM 55, and the input / output interface unit 56 that the processor 62 accesses via the bus 52 is specified. For the elements of the combination, the product sum of the number of times of individual access by the processor 62 and the time required for one access (the number of bus cycles of the bus 52) is calculated.

An appropriate offset value Δopt is determined as a value obtained by obtaining the frequency fc of the clock signal at which the processing capability corresponding to the sum of products is secured within a desired time in combination with the above-mentioned set value F. Can be That is, the frequency fc of the clock signal provided to the processor 62 is automatically maintained at an appropriate value that is substantially proportional to the processing capability of the processing to be performed by the processor 62.

As described above, according to the present embodiment, an increase in power consumption caused by setting the frequency fc of the clock signal to an unnecessarily large value is suppressed to a minimum, so that the power supplied by the battery is reduced. The duration of continuous operation performed according to the driving power is maintained for a long time, and the overall reliability is improved along with the reduction in running cost.

In each of the above embodiments, the main control units 20 and 20A are configured as a single LSI,
I has an external interface RAM 53, an external RAM 54, and an external ROM via a bus 52 formed outside.
55 are connected. However, the present invention is not limited to such a configuration.
3. If the time required to access the internal memory 61 is shorter than the time required to access the external RAM 54 and the external ROM 55, the main control units 20, 20
A may be configured as a single or a plurality of LSIs.

Further, in each of the above-described embodiments, the present invention is applied to a wireless terminal in which a predetermined function and performance are realized under storage logic realized as software executed by a processor 62 operating in synchronization with a clock signal. The invention has been applied. However, the present invention is not limited to a device having such a configuration, and is configured as a synchronous sequential circuit that operates in synchronization with the clock signal described above, and that is a dedicated digital circuit that performs predetermined processing based on wiring logic. It is also applicable to devices equipped with.

Further, in each of the above-described embodiments, the internal memory 61 is configured as a part of the main memory of the processor 62. However, the present invention is not limited to such a configuration. For example, the internal memory 61 stores a program to be executed by the processor 62 to perform the above-described processing without fail and is accessed by the processor 62. For example, if a response can be made within a shorter time than the bus cycle of the bus 52, the memory may belong to an address space other than the main memory or a cache memory.

In each of the embodiments described above, the clock generator 64 is configured as a phase locked loop that performs indirect frequency synthesis. However, the present invention is not limited to such a configuration. If a clock signal having a frequency fc given as a function with respect to the above-described division ratio m or a variable in place of the division ratio m is generated, any method may be used. May be configured as a circuit for performing frequency synthesis on the basis of the above or a circuit for directly varying the oscillation frequency.

Further, in each of the above-described embodiments, the storage area indicated by (the column of) the above-described pointers is the external interface RAM 53 and / or the external RAM 54. However, the present invention is not limited to such a configuration, and the time and the number of bus cycles to be secured when the processor 62 accesses via the bus 52 are maximized, and whether the access is normally completed or not is determined. If the criterion for the determination is reliably given, for example, the storage area indicated by (the column of) the pointer
Any of the following may be used.

An input port for providing known information in response to a read performed by the processor 62; a read provided in the radio unit 42, the baseband processing unit 43, the audio front end unit 44, and other input / output devices and performed by the processor 62. A register that outputs known information according to the information provided in the radio unit 42, the baseband processing unit 43, the audio front-end unit 44, and other input / output devices, and written in advance by the processor 62 (commands and parameters). A) a control register that outputs known information according to the above. In each of the above-described embodiments, information written in advance in a storage area individually indicated by (columns of) the pointers described above and subsequent information from the storage area Access to the storage area is normally performed Dolphin whether the determination has been performed.

However, the present invention is not limited to such a configuration. For example, when the correlation to be established between the previously written information and the subsequently written information is known, A similar determination may be made as the success or failure of the correlation.

Further, in each of the above-described embodiments, such determination is performed only once for each storage area. However, the present invention is not limited to such a configuration. For example, determinations relating to individual storage areas are performed continuously for a predetermined number of times, and whether or not all of the determination results are true is determined. May be determined, and the information to be written in this process may not necessarily be the same information.

In each of the above-described embodiments, the offset value Δ is simply updated to a larger value by the increment δ described above.
In the process, the maximum value at which access to a desired device is normally performed is determined. However, the present invention is not limited to such a configuration, and the offset value Δ
May be varied based on any algorithm, provided that it is determined to a suitable value with the desired accuracy and speed.

Hereinafter, the configurations of the invention disclosed in the above embodiments are arranged hierarchically and multilaterally, and are sequentially listed as additional items. (Supplementary Note 1) The device is configured as a synchronous sequential circuit that operates in synchronization with a clock signal, performs predetermined processing based on wiring logic or storage logic, and performs single or multiple N devices based on the processing procedure. 10-1 to 10-N; a main processing unit 11 for controlling the operation of the main processing unit 11; and a clock generating unit 12 for generating the clock signal and supplying the clock signal to the main processing unit 11.
Determines whether or not access to a single or a plurality of n (≦ N) specific devices among the single or a plurality of N devices 10-1 to 10-N is normally performed;
The clock generation means 12 varies the frequency of the clock signal based on a predetermined algorithm, and reduces the frequency of the clock signal to a value lower than the maximum frequency at which the result of the determination made by the main processing means 11 under the clock signal of that frequency becomes true. A digital control device for setting a frequency of a clock signal.

(Supplementary Note 2) The digital control device according to Supplementary Note 1, further comprising: a processing capability storage unit 13 in which processing capabilities required for individual processes that can be performed by the main processing unit 11 are registered in advance; 12 is
The main processing means 11 grasps the processing actually performed, and sets the frequency of the clock signal to a value at which the processing capacity registered in the processing capacity storage means 13 is secured in accordance with the processing. Digital control device characterized.

(Supplementary Note 3) In the digital control device according to Supplementary Note 1 or 2, the clock generation means 1
2 is a specification that ensures that the main processing unit 11 normally accesses the single or plural n specific devices when the result of the determination made by the main processing unit 11 is false. A digital control device, wherein the frequency of the clock signal is set to the frequency of (1).

(Supplementary Note 4) The digital control device according to Supplementary Note 1 or 2, further including a remaining amount monitoring unit 15 for monitoring the remaining amount of the battery 14 that supplies the driving power, and the clock generation unit 12 includes the remaining amount monitoring unit 15. The main processing unit 11 compares the remaining amount of the battery 14 monitored by the amount monitoring unit 15 with a prescribed lower limit, and when the former falls below the latter, the main processing unit 11 A digital control device, wherein the frequency of the clock signal is set to a specific frequency at which access is normally performed.

(Supplementary Note 5) The digital control device according to Supplementary Note 1 or 2, further comprising a temperature monitoring unit 17 for monitoring a temperature of a portion thermally coupled to the main processing unit 11, and the clock generation unit 12 includes: Comparing the temperature monitored by the temperature monitoring means 17 with a prescribed upper limit, and when the former exceeds the latter, the main processing means 11;
Wherein the frequency of the clock signal is set to a specific frequency at which it is guaranteed that access to the single or plural specific devices is performed normally.

(Supplementary Note 6) In the digital control device according to any one of Supplementary Notes 1 to 5, a man-machine that takes a man-machine interface related to notification of a frequency of the clock signal set by the clock generation unit 12 is provided. A digital control device comprising an interface means 18.

(Supplementary Note 7) In the digital control device according to any one of Supplementary Notes 1 to 6, all or a part of the single or plural n specific devices may be R
The main processing means 11 is configured as an AM and based on a known correlation to be established between information previously written in the RAM and information read from the RAM, A digital controller which determines whether or not access to all or a part of n specific devices is normally performed.

(Supplementary Note 8) In the digital control device according to any one of Supplementary Notes 1 to 7, all or a part of the single or plural n specific devices may be the single or plural N devices. Among the 10-1 to 10-N, in accordance with the frequency and / or form of the access performed by the main processing unit 11, the total processing capacity to be provided by the main processing unit 11 is set in descending order in advance. A digital control device, characterized by being specified.

[0096]

As described above, according to the first aspect of the present invention, the processing capacity can be increased as compared with the conventional example. According to the second aspect of the present invention, it is possible to maintain desired performance and reduce power consumption with high accuracy.

Further, according to the third aspect of the present invention, the period and range over which a fault caused by an improper clock signal frequency is limited to a minimum, and unnecessary reduction in function and performance is prevented. Is avoided. In the invention of the first sub-concept of the invention described in claims 1 and 2,
Even if the inventions described in claims 1 and 2 are applied, the operating time to be continued in a state where the remaining amount of the battery is low does not significantly decrease.

Further, in the invention of the second sub-concept of the first and second aspects of the present invention, predetermined performance is stably maintained in parallel with flexible adaptation to environmental conditions. Further, in the first invention related to the inventions according to claims 1 to 3, labor and efficiency of work related to adjustment performed at the time of shipping and a recovery test for failure can be saved, and some trouble occurs. The frequency of the clock signal at the point in time can be easily obtained, and the cause of a single failure or malfunction can be easily determined.

Further, according to the second aspect of the present invention, a suitable frequency of the clock signal is set with high accuracy in addition to flexible adaptation to various configurations of hardware and software. It is possible to do. According to the third aspect of the present invention, an increase in power consumption caused by setting the frequency of the clock signal to a uselessly large value is avoided, and the running cost is reduced. And the overall reliability is improved.

Therefore, in the devices to which these inventions are applied, the average high performance can be stably achieved while flexibly adapting to the environmental conditions and the availability of parts in accordance with the deviation of the characteristics of the constituent elements. Furthermore, technical restrictions on standardization of the configuration are alleviated, and work related to adjustment and maintenance is reduced.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a diagram showing first to seventh embodiments of the present invention.

FIG. 3 is an operation flowchart of the first and third embodiments of the present invention.

FIG. 4 is a diagram showing a configuration of a control table.

FIG. 5 is an operation flowchart of the second and third embodiments of the present invention.

FIG. 6 is a diagram showing a configuration of a threshold table.

FIG. 7 is a diagram illustrating a configuration example of a terminal device equipped with a microprocessor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Device 11 Main processing means 12 Clock generation means 13 Processing capacity storage means 14 Battery 15 Remaining amount monitoring means 17 Temperature monitoring means 18 Man-machine interface means 20, 20A, 51 Main control unit 21, 63 Frequency setting circuit 31 Temperature sensor 32 Analog Switch 33 A / D converter (A / D) 41 Antenna 42 Radio unit 43 Baseband processing unit 44 Audio front end unit 45 Receiver 46 Microphone 50 Control unit 52 Bus 53 External interface RAM 54 External RAM 55 External ROM 56 Input / output interface Unit 61 Internal memory 61T, 61Tr, 61Ti Control table 61V Threshold table 62 Processor (CPU) 64 Clock generation unit

Claims (3)

[Claims] 1. A synchronous sequential circuit which operates in synchronization with a clock signal, performs predetermined processing based on wiring logic or storage logic, and performs single or plural N processing based on the processing procedure. A main processing unit that controls the operation of the device; and a clock generation unit that generates the clock signal and supplies the clock signal to the main processing unit. The main processing unit includes the single or multiple N devices. And determining whether access to a single or a plurality of n (≦ N) specific devices is normally performed, and the clock generation unit varies a frequency of the clock signal based on a predetermined algorithm. Then, the frequency of the clock signal is set to be equal to or less than the maximum frequency at which the result of the determination made by the main processing unit under the clock signal of that frequency is true. Digital controller, characterized in that. 2. The digital control device according to claim 1, further comprising: a processing capability storage unit in which processing capabilities required for individual processes that can be performed by the main processing unit are registered in advance. Understand the processing actually performed by the main processing means,
A digital control device, wherein the frequency of the clock signal is set to a value at which the processing capability registered in the processing capability storage means is secured in accordance with the processing. 3. The digital control device according to claim 1, wherein said clock generation means is configured to output said clock signal to said main processing means when a result of the determination made by said main processing means is false. A digital control device, wherein the frequency of the clock signal is set to a specific frequency that guarantees normal access to one or more specific devices.