JP2001358785A - Device for eliminating phase noise - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a signal can not be received when C/N is low owing to deterioration to the C/N in a phase noise elimination circuit. SOLUTION: A phase error detector for detecting a phase error θdetects the phase error θ=tan-1(y/x) or θ=±|y| and also makes only the phase error effective at the time of x(X1. Thus, performance deterioration to the C/N does not take phase any more when the signal is made to pass through a phase noise eliminating device compared with when the signal is made not to pass through the phase noise eliminating both in the case phase noise exists and in the case the phase noise does not exist.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving apparatus for television broadcasting, particularly a digital broadcasting receiver.

[0002]

2. Description of the Related Art FIG. 6 shows the configuration of a conventional phase noise eliminator for a terrestrial digital broadcast receiver. Numeral 1 denotes demodulated demodulated data obtained by demodulating a modulated signal. Numeral 3 denotes a Hilbert filter for generating data x 'having an orthogonal relationship between the I-axis and the Q-axis from data y' of only the I-axis as shown in FIG. 3
Delay device with the same delay amount as that of I, 4 is I-axis data
a complex multiplier that corrects the phase error between y ′ and Q-axis data x ′,
5 is the output of the phase noise eliminator, 6 is the output of the complex multiplier 4
a phase error detector for detecting a phase error from y "and x; 8 an integrator for integrating the phase error of the phase error detector 6; 9 an output of sinφ and cosφ from the output φ of the integrator; This is a sine / cosine wave generator input to the complex multiplier 4. The configuration of the complex multiplier 4 in FIG. 6 is shown in FIG. 2, the configuration of the phase error detector 6 in FIG. 6 is shown in FIG. 5 shows the configuration of the integrator 8. The complex multiplier 4 includes multipliers 10, 11, 12,.
13, a subtractor 14 and an adder 15, and outputs y ″ and x are output with respect to inputs x ′ and y ′ as shown in Expressions (1) and (2). Phase error detector 6 Is an input as shown in FIG.
a slicer 16 that outputs y "'to y", a subtractor 17 that subtracts the output y "' of the slicer from y", and tan ^-1 from x and y.
θ = tan ⁻¹ (y / x) 18 for obtaining a phase error by (y / x). When there is phase noise as shown in FIG. 15, data exists on a straight line whose phase has been rotated by θ, and when there is no phase error, the data has a linear shape of θ = 0 as shown in FIG. Exists. The integrator 8 includes a delay unit 22 and an adder 23.

[0003]

In the conventional phase noise elimination device, the phase error θ is obtained by θ = tan ⁻¹ (y / x).
As shown in FIG. 16, when the carrier-to-noise ratio (C / N) is low, the value of the I-axis is more dispersed than when the C / N is high. The axis value x is small,
In the case where the value y of the I axis is large, the phase error detected by the error detector may be erroneously detected as large as compared with the case where the value x of the Q axis is large as indicated by the black square in FIG. is there. As shown in FIG. 18, the phase noise (70 dBc / Hz (10
(when detuning kHz) and 90dBc / Hz (when detuning 100kHz)), the reception performance deteriorates by C / N = 0.5dB when passing through the phase noise elimination device compared to when not passing through the phase noise elimination device. When there is no phase noise, the reception performance when passing through the phase noise eliminator is C / N = 0.
There is a problem that the reception performance is deteriorated when the C / N is poor by 6 dB.

[0004]

Means for Solving the Problems (1) First invention A phase noise eliminator according to a first invention has a complex multiplier for inputting data having an orthogonal relationship, and a phase multiplier is provided from the output of the complex multiplier. There is a phase error detector that creates data x and y for detecting an error and outputs a phase error θ = tan ⁻¹ (y / x), and the phase error θ output by the phase error detector is There is a discriminator that discriminates whether to enable or disable the phase error and outputs the phase error θ ′ after the discrimination, and the discriminator is I-axis data x (when X1 is the output of the complex multiplier) And outputs the phase error θ = tan ⁻¹ (y / x) as the output θ ′ of the discriminator, and the discriminator outputs I, which is the output of the complex multiplier.
There is an integrator that outputs the phase error 0 as the output θ ′ of the discriminator when the axis data x ′ <X1, and integrates the output of the discriminator, and outputs sinφ and cosφ from the output φ of the integrator. A sinusoidal cosine wave generator, wherein sinφ and cosφ from the sine wave cosine wave generator are input to the complex multiplier, and a phase error due to phase noise is corrected. .

[0005] In the phase noise elimination apparatus according to the first invention, it is possible to provide a reception apparatus in which the reception performance does not deteriorate even when the C / N is poor.

(2) Second invention The phase noise elimination device according to the first invention has a complex multiplier for inputting data having an orthogonal relationship, and detects a phase error from an output of the complex multiplier. There is a phase error detector that creates data x and y and outputs a phase error θ = y, and an integrator that integrates the output of the phase error detector, and outputs sinφ and cosφ from the output φ of the integrator There is a sinusoidal cosine wave generator
A phase noise eliminator characterized in that φ and cos φ are input to the complex multiplier to correct a phase error due to phase noise. In the phase noise elimination device according to the second invention, the reception performance does not deteriorate even when the C / N is poor,
In addition, a receiving device having a small circuit scale can be provided.

(3) Third invention A phase noise eliminator according to a third invention has a complex multiplier for inputting data having an orthogonal relationship, and detects a phase error from an output of the complex multiplier. There is a phase error detector that creates data x and y and outputs a phase error θ = y, and determines whether to enable or disable the phase error of the phase error θ detected by the phase error detector. And there is a discriminator that outputs the phase error θ ′ after the discrimination, and the discriminator outputs the phase error θ = y when the I-axis data x (X1 is the output of the complex multiplier, the output θ of the discriminator. And the discriminator outputs the phase error 0 as the discriminator output θ when the I-axis data x <X1 which is the output of the complex multiplier, and integrates the output of the discriminator. There is an integrator, and there is a sinusoidal cosine wave generator that outputs sinφ and cosφ from the output φ of the integrator. sinφ from the sine wave cosine wave generator, the cosφ input to the complex multiplier, a phase noise elimination device and correcting the phase error due to phase noise. 3
In the phase noise elimination apparatus according to the invention, even if the C / N is poor, the reception performance does not deteriorate and the reception apparatus can be provided with a small circuit scale.

(4) Fourth invention A phase noise elimination apparatus according to a fourth invention is a phase noise elimination apparatus according to the first invention and the third invention,
C / N that outputs the carrier-to-noise ratio (C / N) of the RF input signal
A phase noise eliminator, comprising: a detector for changing a value of X1 used in the discriminator based on a magnitude of cn outputted from the C / N detector. In the phase noise elimination apparatus according to the invention of the present invention, it is possible to provide a phase noise elimination apparatus that does not deteriorate the reception performance even when the C / N is poor and increases the phase noise elimination ability when the C / N is good. .

(5) Fifth invention The phase noise elimination apparatus according to the fifth invention is the same as the phase noise elimination apparatus according to the first invention and the third invention,
A phase noise eliminator characterized by changing a value of X1 used in the discriminator based on a value of an output φ from the integrator. In the phase noise elimination device according to the fifth invention, it is possible to provide a phase noise elimination device that changes the phase noise elimination capability in accordance with the phase noise situation and minimizes the performance degradation with respect to C / N.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A receiving apparatus according to the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 shows the configuration of a phase noise elimination apparatus according to Embodiment 1 of the present invention. Numeral 1 denotes demodulated demodulated data obtained by demodulating a modulated signal, and numeral 3 denotes data x 'which is orthogonal to the I-axis and the Q-axis from data y' of only the I-axis as shown in FIG.
, A delay unit having the same delay amount as that of the Hilbert filter 3, a complex multiplier 4 for correcting the phase error between the I-axis data y 'and the Q-axis data x', and 5 The phase noise eliminator output, 6 is a phase error detector for detecting a phase error from the output y ", x of the complex multiplier 4, and 7 is to enable or disable the phase error detected by the phase error detector 6. Discriminators 7 and 8 for determining whether or not the integrator integrates the error signal from the discriminator 7;
It is a sinusoidal cosine wave generator that outputs φ and cosφ. Since the configurations of the complex multiplier 4, the phase error detector 6, and the integrator 8 are the same as those of the conventional example, the description is omitted here. Hereinafter, the configuration of the discriminator in FIG. 1 will be described with reference to FIG. In the discriminator 7, the phase error θ detected by the error detector 6 is output from the absolute value circuit 36 through the switch 19 when | x | (X1 is satisfied, and is switched when | x | <X1. 0 through 19
Is output. That is, the phase error θ detected by the error detector 6 is made valid when | x | (X1, and the phase error θ detected by the error detector 6 is made invalid when | x | <X1. The reason is that when the C / N of the input signal is poor,
When the data is dispersed as shown in (b) and the value of x is small and the value of y is large as shown in FIG. 17 (● in FIG. 17).
The reason is that the phase error θ detected by the phase error detector 6 is erroneously detected as a large value by the phase error detector 6, which causes a problem that the reception performance is deteriorated. The reception performance is set to X1 = 6.5, and phase noise (70 dBc / Hz (at 10 kHz detuning), 90 dBc / Hz (at 100 kHz detuning)) as shown in FIG. 17 is added. In the case, the performance degradation with respect to C / N when passing through the phase noise eliminator when not passing through the phase noise eliminator was compared.

When there is phase noise, the reception performance is improved by C / N = 0.1 dB when passing through the phase noise elimination device as compared with when the phase noise elimination device is not passed, and C / N = 0.6 dB as compared with the conventional example. Get better. When there is no phase noise, the reception performance is the same when passing through the phase noise elimination device than when not passing through the phase noise elimination device.
C / N = 0.6dB better.

(Second Embodiment) A receiving apparatus according to a second embodiment of the present invention is the same as the conventional example, as shown in FIG. Since the configurations of the complex multiplier 4, the phase error detector 6, and the integrator 8 are the same as those of the conventional example, the description is omitted here. Figure 7 below
The configuration of the phase noise detector 6 will be described with reference to FIG. The phase error detector 6 has a slicer 16 which becomes an output y "'with respect to an input y" as shown in FIG. 14, and a slicer output y "' from y".
Subtractor 17, an absolute value circuit 24 for taking the absolute value of y, a multiplier 25 for multiplying the output | y | of the absolute value circuit 24 by -1, a constant -1 (26), y "and x" Sign (+ or-)
A switch 30 for outputting | y | or-| y |
A sign bit extractor 27 for extracting the sign bit of x, a sign bit extractor 28 for extracting the sign bit of x,
(Exclusive OR) 29. As shown in FIG.
If the signs of x and y "are the same,-| y
Is output, and if x and y "have different signs, | y | is output.
In order to determine the phase error, it is necessary to determine the phase error at θ = tan ⁻¹ (y / x) as in the conventional example and the first embodiment.
A ROM (Read Only Memory) with a phase error θ = tan ⁻¹ (y / x) is required, and the circuit scale becomes large. However, the phase error θ = ± | y |
There is an advantage that the circuit scale can be reduced by approximating by.
The reception performance is set to X1 = 6.5, and phase noise (70 dBc / Hz (at 10 kHz detuning), 90 dBc / Hz (at 100 kHz detuning)) as shown in FIG. 18 is added, and there is no phase noise. In the case, the performance degradation with respect to C / N when passing through the phase noise eliminator when not passing through the phase noise eliminator was compared. When there is phase noise, the reception performance is the same when passing through the phase noise elimination device than when not passing through the phase noise elimination device.
C / N = 0.5 dB is improved as compared with the conventional example. When there is no phase noise, the reception performance is degraded by 0.1 dB when passing through the phase noise eliminator when not passing through the phase noise eliminator, and is improved by C / N = 0.5 dB as compared with the conventional example.

(Embodiment 3) A receiving apparatus according to Embodiment 1 of the present invention is the same as that of Embodiment 1 and is as shown in FIG. The difference from the first embodiment is a phase noise detector 6, and the configuration of the phase noise detector 6 is the same as the configuration in FIG. 7 of the second embodiment. The description of each block in FIG.
Therefore, the description is omitted here.

In the third embodiment, in order to reduce the circuit scale and eliminate performance degradation due to C / N, the phase error θ = ±
approximating by | y |, the phase error θ detected by the error detector 6 is made valid when x (X1, and the phase error θ detected by the error detector 6 is made invalid when x <X1. X1 =
6.5, the phase noise (70 dBc / H
z (at the time of 10kHz detuning), 90dBc / Hz (at the time of 100kHz detuning)), and C / when passing through the phase noise removing device with and without phase noise N
And the performance degradation was compared. When there is phase noise, the reception performance is improved by C / N = 0.1dB when passing through the phase noise elimination device compared to when not passing through the phase noise elimination device,
C / N = 0.6 dB better than the conventional example. In the case where there is no phase noise, the reception performance is the same when passing through the phase noise elimination device than when not passing through the phase noise elimination device, and is improved by C / N = 0.6 dB as compared with the conventional example.

(Embodiment 4) As shown in FIG. 9, the configuration of Embodiment 4 of the present invention is such that a C / N detector 31 is added to FIG. 1 of Embodiments 1 and 3. Except for the discriminator 7 in FIG. 9, the configurations of the complex multiplier 4, the phase error detector 6, and the integrator 8 are the same as those in the first and third embodiments, so only the configuration of the discriminator 7 in FIG. This will be described with reference to FIG. 32 is a comparator that outputs a value of 1 when the value of C / N detected by the C / N detector is cn (CN1), and 33 is a comparator (cn (CN1)
When the output of 32 is 1, X2 is output and the comparator (cn (CN1) 3
2 is a switch that outputs X3 when the output is 0, 36 is an absolute value circuit that outputs the absolute value of x, 21 is a comparator that outputs | x | (1 when X1, and 19 is a comparator (| x When the output of | (X1) 21 is 1, θ is output, 19 is a switcher that outputs 0 when the output of | x | (X1) 21 is 0, and 20 is a constant 0. In X1 of the forms 1 and 3, as the value of X1 is reduced, the number of error detections to be enabled can be increased, and the phase error can be tracked when the phase noise is poor. On the other hand, when the value of X1 is increased, the degradation to C / N is reduced, but the number of error detections to be enabled is reduced, so that it may not be possible to follow the phase error when the phase noise is bad. Therefore, in the case of a high C / N that enables reception even if the C / N is degraded in the phase noise eliminator, a condition in which the phase noise is poor. By giving priority to the case where the signal of interest is input to the phase noise eliminator, reducing the value of X1 and increasing the number of error detections to be enabled,
Be able to follow bad phase noise. In the case of a low C / N that cannot be received if there is performance degradation to the C / N, consider the case where the phase noise is bad, and reduce the value of X1 to increase the number of error detections that are enabled. Since reception becomes impossible due to performance degradation for C / N, priority is given to performance degradation for C / N, and the number of C / N detections is reduced to prevent performance degradation for C / N. More specifically, referring to FIG. 10, when the value of cn detected by the C / N detector is larger than CN1 (in the case of high C / N), the smaller value X2 is output from the switch 33 as X1. I do. Cn detected by C / N detector
Is smaller than CN1 (low C / N), the large value X3 is output from the switch 33 as X1. X2 and X3
Have a relationship of X2 <X3. Then, when | x | (X1, the phase error θ detected by the phase error detector 6 is output from the switch 19, and when | x | <X1, the phase error 0 is switched.
Output from By this means, when C / N is high, performance degradation due to bad phase noise can be prevented, and when C / N is good, performance degradation with respect to C / N can be prevented.

(Embodiment 5) The configuration of Embodiment 4 of the present invention is to feed back the output φ from the integrator 8 to the discriminator 7 in FIG. 1 of Embodiments 1 and 3, as shown in FIG. Since it is the same as Embodiments 1 and 3 except for this point, the configuration of the discriminator 7 in FIG. 11 will be described here with reference to FIG. 35 is 1 when the output φ of the integrator is φ (φ1
Are output from the comparators (φ (φ1) 3)
When the output of 5 is 1, X2 is output and the comparator (φ (φ1) 35
When the output of is 0, the switches 33 and 34 that output X3 are |
The comparators 34 and 19 that output 1 when x | (x1 are comparators (| x
When the output of | (x1) 34 is 1, θ is output, and the comparator (| x |
(x1) A switch that outputs 0 when the output of 34 is 0, 2
0 is a constant 0. In the first and third embodiments, the smaller the value of X1, the larger the number of error detections that can be made effective, and can follow the phase error when the phase noise is poor. Performance degradation for N occurs. Conversely X
When the value of 1 is increased, the deterioration with respect to C / N is reduced, but the number of error detections to be enabled is reduced, so that it may not be possible to follow the phase error when the phase noise is bad. Low C /
In the case of N, considering the case where the phase noise is bad, if the value of X1 is reduced and the number of error detections to be enabled is increased, reception becomes impossible due to performance deterioration with respect to C / N. Prioritizing degradation, reduce the number of C / N detections so that there is no performance degradation for C / N. More specifically, referring to FIG. 12, when the output φ of the integrator 8 is φ (φ1 (when the phase noise is poor), the small value X2 is set to X1 and the switch 3
Output from 3. If the output φ of the integrator 8 is φ <φ1 (when the phase noise is good), the large value X3 is set to X1 and the switch 3
Output from 3. X2 and X3 have a relationship of X2 <X3. Then, when | x | (X1, the phase error θ detected by the phase error detector 6 is output from the switch 19, and when | x | <X1, the phase error 0 is output from the switch 19. By
If the phase noise is bad, performance degradation due to bad phase noise can be prevented, and if the phase noise is good, C / N
Can be prevented from deteriorating in performance.

[0018]

As described above, according to the receiving apparatus of the present invention, when the phase error θ = tan-1 (y / x) is obtained, the phase error θ is made effective when x (X1). In addition, it is possible to provide a phase noise elimination device that does not deteriorate the C / N performance both in the case where the phase noise exists and in the case where the phase noise does not exist, and by approximating the phase error by θ = ± | y | Low C / N with and without phase noise
, A phase noise elimination device with almost no performance degradation can be provided. Also, by approximating the phase error with θ = ± | y | and enabling the phase error θ when x (X1, the circuit scale is small, and C / N is obtained both with and without phase noise. It is possible to provide a phase noise elimination device that does not cause performance degradation for X. In addition, the value of X1 that makes the phase error θ effective when X (X1) is changed by the C / N detected by the C / N detector. In this way, it is possible to prevent the reception performance deterioration when the phase noise is bad and the reception performance deterioration with respect to C / N.In addition, depending on the magnitude of the phase error value, the phase error θ is made effective when x (X1. By changing the value of X1, it is possible to prevent reception performance degradation when phase noise is poor and reception performance degradation for C / N.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a phase noise elimination device according to first and third embodiments of the present invention.

FIG. 2 is a block diagram showing a configuration of a complex multiplier shown in FIGS. 1, 6, 9, and 11;

FIG. 3 is a block diagram showing a configuration of a phase error detector shown in FIG. 1;

FIG. 4 is a block diagram showing a configuration of a discriminator shown in FIG.

FIG. 5 is a block diagram showing a configuration of the integrator shown in FIGS. 1, 6, 9, and 11;

FIG. 6 is a block diagram illustrating a configuration of a phase noise removing apparatus according to a second embodiment of the present invention and a conventional example.

FIG. 7 is a diagram showing the phase error detector of FIGS. 1 and 7;

FIG. 8 is a diagram showing an input / output relationship of the phase error detector shown in FIG. 7;

FIG. 9 is a block diagram showing a configuration of a phase noise elimination device according to a fourth embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a discriminator in FIG. 9;

FIG. 11 is a block diagram showing a configuration of a phase noise elimination device according to a fifth embodiment of the present invention.

12 is a diagram showing input data of the Hilbert filter of FIGS. 1, 6, 9, and 11 on I-axis and Q-axis coordinates.

FIG. 13 is a diagram showing output data of the Hilbert filter in FIGS. 1, 6, 9 and 11 on I-axis and Q-axis coordinates.

FIG. 14 is a diagram showing an input / output relationship of the slicer shown in FIGS. 3 and 7;

FIG. 15 is a diagram showing output data of a Hilbert filter on the I-axis and Q-axis coordinates when there is phase noise;

FIG. 16 (a) is a diagram showing the distribution of Hilbert filter output data on the I-axis and Q-axis coordinates when phase noise is present when C / N is high. (B) When C / N is low, Diagram showing the distribution of Hilbert filter output data with phase noise on the I-axis and Q-axis coordinates

FIG. 17 is a diagram showing the difference between the phase error θ when the value of | x | is small and the value of | y | is large, and the phase error θ when the value of | x |

FIG. 18 is a diagram illustrating the influence of a spectrum indicating an index of phase noise on reception performance.

[Explanation of symbols]

Reference Signs List 1 demodulated data 2, 22 delay unit 3 Hilbert filter 4 complex multiplier 5 phase noise eliminator output 6 phase error detector 7 discriminator 8 integrator 9 sine wave cosine wave generator 10, 11, 12, 13 multiplier 14, Reference Signs List 17 subtractor 15, 23 adder 16 slicer 18 θ = tan ^-1 (y / x) 19, 30, 33 switcher 20 0 21 | x | (X1 (comparator) 24, 36 absolute value circuit 25 multiplier 26 −1 27,28 Sign bit extractor 29 XOR (exclusive OR circuit) 31 C / N detector 32 cn (CN1 (comparator) 35 φ (φ1 (comparator)

Continuing on the front page (72) Inventor Hiroshi Azakami 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. Reference) 5C025 AA17 AA20 BA30 DA01 5K004 AA01 AA03 BA02 BB06 DA15 5K052 AA01 EE26 EE28 FF32 GG00 GG11 GG19 GG20 GG42

Claims (5)

[Claims] 1. A complex multiplier for inputting data having an orthogonal relationship is provided. Data x and y for detecting a phase error are created from an output of the complex multiplier, and a phase error θ = tan ⁻¹ (y /
x), and determines whether to enable or disable the phase error of the phase error θ output by the phase error detector, and outputs the determined phase error θ ′. There is a classifier, the classifier is the output of the complex multiplier I-axis data x (X1 when the phase error θ = tan ^-1 (y / x)
Is output as the output θ ′ of the discriminator, and the discriminator outputs the phase error 0 as the output θ ′ of the discriminator when the I-axis data x ′ <X1, which is the output of the complex multiplier, There is an integrator that integrates the output of the discriminator, and the output φ of the integrator is
There is a sine wave cosine wave generator that outputs sinφ and cosφ from, and sinφ and cosφ from the sine wave cosine wave generator are input to the complex multiplier to correct a phase error due to phase noise. Phase noise removal device. 2. A complex multiplier for inputting data having an orthogonal relationship, generating data x and y for detecting a phase error from an output of the complex multiplier, and outputting a phase error θ = y There is an error detector, an integrator for integrating the output of the phase error detector, and sin from the output φ of the integrator.
There is a sine wave cosine wave generator that outputs φ and cos φ, and sin φ and cos φ from the sine wave cosine wave generator are input to the complex multiplier to correct a phase error due to phase noise. Noise removal device. 3. A complex multiplier for inputting data having an orthogonal relationship, generating data x and y for detecting a phase error from an output of the complex multiplier, and outputting a phase error θ = y There is an error detector, there is a discriminator that discriminates whether to validate or invalidate the phase error of the phase error θ detected by the phase error detector and outputs the phase error θ ′ after the discrimination, The discriminator outputs the I-axis data x (X1 which is the output of the complex multiplier, the phase error θ = y as the output θ ′ of the discriminator, and the discriminator is the output of the complex multiplier. There is an integrator that outputs the phase error 0 as the output θ ′ of the discriminator when I-axis data x <X1, and integrates the output of the discriminator, and outputs sinφ and cosφ from the output φ of the integrator. There is a sine wave cosine wave generator, and sinφ and cosφ from the sine wave cosine wave generator are And enter
A phase noise removing device for correcting a phase error caused by phase noise. 4. A carrier-to-noise ratio (C / N) of an RF input signal.
2. A C / N detector for outputting the value of X1, wherein the value of X1 used in the discriminator is changed based on the magnitude of cn output from the C / N detector. 3, the receiving device. 5. Based on the value of the output φ from the integrator,
4. The receiving apparatus according to claim 1, wherein the value of X1 used for said discriminator is changed.