JP2001358519A - Two-dimensional vector normalizing device, two- dimensional vector phase extracting device and beam forming circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To remarkably reduce a scale of a hardware and to stably assure a desired responsivity and an accuracy. SOLUTION: A two-dimensional vector normalizing device comprises a memory means for previously registering a unit vector equal at a declination to a declination of its complex number individually corresponding to all combinations of values of binary numbers capable of being taken in a reel part and an imaginary part of the complex number; a quadrant limiting means for obtaining a sequence by conserving codes of the real part and the imaginary part of the complex number, and rearranging a descending order of absolute values of the real part and the imaginary part to obtain a complex vector given by a sequence of coordinates of an end point in a complex plane; and a quadrant restoring means for acquiring coordinates of the end point registered with the memory means corresponding to coordinates of the end point of the obtained complex vector, and executing a reversible rearrangement to the rearrangement in the coordinates and restoration of the code to obtain the unit vector.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-dimensional vector normalizing apparatus for setting an absolute value of a complex number obtained as a result of an operation or obtained as an operation result in a process of digital signal processing to a specified value, and a complex number The present invention relates to a two-dimensional vector phase extracting device for obtaining a phase angle, and a beam forming circuit on which both or one of these devices is mounted.

[0002]

2. Description of the Related Art In recent years, digital signal processing technology has advanced to a high degree, and hardware that realizes various forms of digital signal processing based on a storage program control method while reducing power consumption with high speed and high accuracy. Can be realized. Therefore, in such digital signal processing, not only communication equipment to be subjected to various filtering processing, equalization processing, encoding and decoding, but also speech synthesis, pattern recognition, image processing and other processing are performed as complex operations. It is being applied to a variety of devices that should be used.

In these digital signal processing processes, the amplitude component (absolute value) of a complex number given as an operation target or representing a two-dimensional vector obtained as an operation result is normalized to a prescribed value, or By extracting only the phase component of the complex number, efficiency, optimization, and simplification of the operation to be performed subsequently can be appropriately achieved.

FIG. 13 is a diagram showing a configuration example of an arithmetic circuit for realizing a complex number normalization. In the figure, a real part R and an imaginary part I of a complex number to be operated are respectively
1-r and 131-i are squared, and the obtained individual square values are added by an adder 132. The result is given to the conversion table 133 as a read address (= R ² + I ² ). The conversion table 133 includes an adder 13
2, a value equal to the reciprocal of the square root of the read address (= 1 / (R ² + I ² ) ^1/2 ) is individually registered in advance, corresponding to all values that can be given as such a read address.

[0005] The multipliers 134-r and 134-i
The real part R and the imaginary part I described above and the conversion table 133 are described above.
Reciprocal (= 1 / (R^Two
+ I ^Two)^1/2). Therefore, these multipliers
The outputs of 134-r and 134-i are described above on the complex plane
The two-dimensional vector represented by the real part R and the imaginary part I have the same declination.
Of the unit vector whose end point is located on the unit circle
Part r (= R / (R^Two+ I^Two)^1/2) And the imaginary part amplitude i (= I / (R^Two+
I^Two)^1/2) Is obtained.

[0006]

By the way, in such a conventional example, for example, when the real part R and the imaginary part I are each given as a 13-bit word based on a fixed-point system, the conversion table The word length of the read address given to 133 increases with the multiplication performed by multipliers 131-r and 131-i and the addition performed by adder 132, and increases by 27 (=
13 × 2 + 1) bits.

Further, when the word length of each reciprocal is 20 bits, the information amount of the reciprocal to be registered in the conversion table 133 in advance is 82 (≒ 2 ²⁵ × 20 / (8 × 1
0 ⁶ )) A huge value of megabytes. Therefore, FIG.
In the arithmetic circuit shown in FIG. 3, the time required for the arithmetic operation is shortened by looking up the conversion table 133, and high-speed processing can be easily realized. However, the arithmetic circuit is related to the circuit scale, power consumption, thermal design, reliability, and mounting. Unless a margin was secured, it was actually difficult to apply.

The processing performed by the arithmetic circuit shown in FIG. 13 is performed by a DSP (D
digital signal processor) may be implemented as an arithmetic operation performed based on a stored program control method. However, the time required for such an arithmetic operation is generally longer than when it is performed by a dedicated arithmetic circuit, especially when the frequency at which a complex number to be subjected to an individual arithmetic operation is given can be extremely large. However, even if a desired signal processing algorithm to be achieved by a series of processing including these arithmetic operations is optimized, there is a possibility that real-time performance of the signal processing is not ensured.

Further, a dedicated hardware for performing digital signal processing in place of the DSP includes an FPGA (Field Program).
In the case of a configuration using a rammable gate array, the above-described arithmetic operation can be performed by a floating point arithmetic unit (FPU) incorporated in the hardware. However, such hardware has a plurality of floating-point arithmetic units having substantially the same configuration and equal to the number of times when the above-described arithmetic operation is to be performed many times in the course of the desired digital signal processing. Vessels must be incorporated.

[0010] That is, even if the desired response and real-time characteristics are ensured, such a configuration is actually large in scale of the overall circuit, so that power consumption, thermal design, reliability, and mounting can be reduced. It was often difficult to apply because of the constraints involved. An object of the present invention is to provide a two-dimensional vector normalizer, a two-dimensional vector phase extractor, and a beam forming circuit in which the scale of hardware is significantly reduced and desired responsiveness and accuracy are stably secured. And

[0011]

FIG. 1 is a principle block diagram (1) of a two-dimensional vector normalizing device and a two-dimensional vector phase extracting device according to the present invention. According to the first aspect of the present invention, the storage means 11 stores the argument of the complex number as the argument of the complex number corresponding to each possible combination of the binary values of the real part and the imaginary part of the complex number. And the coordinates of the end point on the complex plane of the unit vector whose absolute value is “1” are registered in advance. The quadrant limiting means 12 stores the sign of the real part and the imaginary part of the complex number described above. Further, the quadrant limiting means 12 obtains a permutation by rearranging the absolute values of the real part and the imaginary part in descending order, and obtains the complex vector in which the coordinates of the end point on the complex plane are given by the permutation. Get. The quadrant restoring means 13
The coordinates of the end point registered in the storage means 11 are acquired corresponding to the coordinates of the end point of the complex vector obtained in this manner, and the coordinates obtained by the By performing the reversible rearrangement and the code restoration, a unit vector obtained by converting the absolute value of the complex number into “1” is obtained.

That is, in the storage means 11, for a complex number having a desired real part and imaginary part in a region corresponding to half of the first quadrant on the complex plane, the argument is equal to the argument of the complex number. And the coordinates of the end point of the unit vector whose absolute value is “1” are stored. Further, the quadrant limiting means 12 and the quadrant restoring means 13 cooperate with each other to obtain a mapping of a desired complex number for such an area, and refer to the storage means 11 to obtain a complex vector given as the mapping. After obtaining a unit vector having a declination equal to the declination, the unit vector is mapped to the original quadrant based on the above-described rearrangement form and the stored code.

[0013] Regarding the coordinates to be stored in the storage means 11, the end point of the complex vector given as the above-described mapping is limited to an area of one eighth or less of the first to fourth quadrants on the complex plane. In general, it is possible to set the word length of the coordinates to a desired value different from the word lengths of the real part and the imaginary part of the complex number. Further, the storage and restoration of codes, the reversible coordinate rearrangement, and the reference to the storage unit 11 performed by the quadrant limiting unit 12 and the quadrant restoring unit 13 are performed under a simple combination of the combinational circuit and the sequential circuit. It can be realized by:

Therefore, the scale of the hardware is greatly reduced, and the desired complex number can be normalized accurately and at high speed. FIG. 2 is a principle block diagram (2) of the two-dimensional vector normalizing device and the two-dimensional vector phase extracting device according to the present invention. According to the second aspect of the present invention, the storage means 21 stores the argument of the complex number in correspondence with each possible combination of the binary values of the real part and the imaginary part of the complex number. And the coordinates of the end point on the complex plane of the unit vector whose absolute value is “1” are registered in advance. The scaler 22 shifts the real part and the imaginary part of the complex number in parallel in units of bits, and sets a value that is less than the upper limit value “2 ⁿ ” and greater than or ^equal to “2 ^n-1 ” given to the natural number n. Next, these real parts and imaginary parts are scaled. The vector conversion means 23 obtains the coordinates of the end point registered in the storage means 21 corresponding to the result of the scale, thereby obtaining a unit vector in which the absolute value of the complex number is converted to "1". .

That is, the coordinates registered in the storage means 21 and which can be obtained by the vector conversion means 23 are effective real parts and imaginary parts obtained under the scale performed by the scale means 22 based on the natural number n described above. Is limited to the number of words equal to the product of the maximum values of the bits, and the more effective bits included in the real part and the imaginary part in the scale process, the more accurate the number of words.

Therefore, as compared with the conventional example in which such a scale is not performed at all, the scale of the hardware is greatly reduced, and a desired complex number is normalized with a desired precision. Further, in the invention of the first sub-concept of the invention described in claim 2, the scaler 22 sets the ratio of the relative error of the rounding error generated individually in the real part and the imaginary part to a value within a predetermined upper limit value or less. The real part and the imaginary part are shifted. In addition, the coordinates of the end point corresponding to all of the scales that can be applied by the scaler 22 are registered in the storage 21 in advance.

That is, since the relative error of the rounding error generated in the scale process between the real part and the imaginary part of the desired complex number is set, the information amount of the coordinates to be registered in the storage means 21 is allowed. , The accuracy of the normalization of the complex number is increased. Further, according to the invention of the second subordinate concept of the invention described in claim 2, the vector conversion means 23
Of the result of the scale performed by the scale means 22 is the LSB of both or one of the real part and the imaginary part.
Is rounded up or truncated in accordance with the magnitude relationship between the lower order value and the predetermined threshold value.

That is, even if both the real part and the imaginary part of the desired complex number must be shifted to the LSB side in the process of scaling, the above-mentioned rounding and rounding down are performed. Is performed, the rounding error is compressed. Therefore, the accuracy of the normalization to be performed on the desired complex number is kept high.

According to another aspect of the present invention, the alarm means 10 includes the storage means 11 and 2.
Among the real part and the imaginary part to be applied to the reference of 1, a combination of all bits whose value is “0” is identified, and a status indicating the combination is output. That is,
Even though both or one of the real part and the imaginary part as a result of the normalization is a value uniquely determined, the time required for the operation becomes excessive due to the combination of these values, or the predetermined accuracy is A state in which unobtainable processing should be regulated or avoided can be reliably obtained as the above status.

Therefore, since such a status is not obtained at all, the performance and the responsiveness are maintained higher than when the above-described processing is simply performed. Claim 3
According to the invention described in (1), the argument of the complex number is registered in advance in the storage unit 31 in correspondence with all combinations of binary values that the real part and the imaginary part of the complex number can take. The quadrant limiting means 32 stores the sign of the real part and the imaginary part of the complex number described above. Further, the quadrant limiting means 32 obtains a permutation by rearranging the absolute values of the real part and the imaginary part in descending order, and obtains a complex vector in which the coordinates of the end point on the complex plane are given by the permutation. Get. The quadrant restoring unit 33 acquires the argument registered in the storage unit 31 corresponding to the coordinates of the end point of the complex vector thus obtained, and stores the argument in the quadrant limiting unit 32.
The correction of the change generated in the rearrangement process performed by the above and the restoration of the quadrant shown on the complex plane as a combination of codes are performed to obtain the argument of the complex number described above.

That is, the storage means 31 stores the argument of a complex number having a desired real part and imaginary part in an area corresponding to half of the first quadrant on the complex plane. Further, the quadrant limiting means 32 and the quadrant restoring means 33 cooperate with each other to obtain a mapping of a desired complex number to such an area, and refer to the storage means 31 to obtain a complex vector given as the mapping. The argument is determined, and based on the above-described rearrangement form and the stored code, the end point is located in the original quadrant, and a unit vector having the argument corresponding to this argument is mapped.

Regarding the argument to be stored in the storage means 31, the end point of the complex vector given as the above-mentioned mapping is limited to an area of one eighth or less of the first to fourth quadrants on the complex plane. And, in general, the word length may be set to a desired value. Furthermore, quadrant limiting means 3
The storage and restoration of codes, rearrangement of coordinates, and reference to the storage means 31 performed by the second and quadrant restoration means 33 can be generally realized under a simple combination of a combinational circuit and a sequential circuit. .

Therefore, the scale of the hardware is greatly reduced, and the desired complex number can be normalized accurately and at high speed. According to the fourth aspect of the present invention, the storage means 41
, The argument of the complex number is registered in advance for each combination of the possible binary values of the real part and the imaginary part of the complex number. The scale unit 42 shifts the real part and the imaginary part of the complex number in parallel in units of bits, and sets a value that is less than the upper limit value “2 ⁿ ” and equal to or more than “2 ⁿ⁻¹ ” given to the natural number n. Next, these real parts and imaginary parts are scaled. The vector conversion unit 43 obtains the argument registered in the storage unit 41 corresponding to the result of the scale.

That is, regarding the argument which is registered in the storage means 41 and which can be obtained by the vector conversion means 43, the effective real part obtained by the scaling means 42 under the scale performed based on the natural number n and the imaginary real part It is limited to the number of words equal to the product of the maximum value of the part and the number of effective bits included in the real part and the imaginary part in the scale process.

Therefore, as compared with the conventional example in which such a scale is not performed at all, the scale of hardware is greatly reduced, and a desired complex number is normalized with a desired precision. Further, in the invention of a lower concept of the invention described in claim 3, the quadrant restoring means 33 includes, among the coordinates of the end point of the complex vector applied upon referring to the storage means 31, the difference between the real part and the imaginary part of the coordinates. For either or one of them, carry up or cut off according to the magnitude relationship between the value of the lower order of the LSB and a predetermined threshold.

That is, the rounding error that can occur in the real part and the imaginary part of a desired complex number is compressed as long as the above-mentioned rounding and truncation are properly performed. Therefore, the accuracy of the normalization to be performed on the desired complex number is kept high. Further, in the invention according to the first sub-concept of the invention described in claim 4, the scaler 42 adjusts the ratio of the relative error of the rounding error individually generated in the real part and the imaginary part to a range equal to or less than a predetermined upper limit value. The real part and the imaginary part are shifted. Further, in the storage unit 41, the declination corresponding to all the scales that can be applied by the scale unit 42 is registered in advance.

That is, since the relative error of the rounding error generated in the scale process between the real part and the imaginary part of the desired complex number is set to a limit, the information amount of the argument to be registered in the storage means 41 is allowed. As long as it is small, the precision of the normalization of the complex number is increased. Further, according to the invention of the second subordinate concept of the invention described in claim 4, the vector conversion means 43
Of the result of the scale performed by the scale means 42, for both or one of the real part and the imaginary part,
Is rounded up or truncated in accordance with the magnitude relationship between the lower order value and the predetermined threshold value.

That is, even if both the real part and the imaginary part of the desired complex number need to be shifted to the LSB side in the process of scaling, the above-mentioned rounding and truncation are performed. Is performed, the rounding error is compressed. Therefore, the accuracy of the normalization to be performed on the desired complex number is kept high.

Further, in another invention of a lower conception according to the third and fourth aspects of the present invention, the alarm means 30 comprises a storage means 31,
41. Identify the combination of the real part and the imaginary part to be applied to the reference of 41, wherein the value of all bits is “0”;
A status indicating the combination is output. That is, although the argument of the unit vector as a result of the normalization is a value that is uniquely determined, the time required for the operation becomes excessively long due to the combination of these values, or a predetermined accuracy cannot be obtained. A state in which the processing should be regulated or avoided can be reliably obtained as the above status.

Therefore, since no such status is obtained, the performance and the responsiveness are maintained higher than when the above-described processing is simply performed. FIG.
Principle block diagram of the beam forming circuit according to the present invention (1)
It is. FIG. 4 is a principle block diagram (2) of the beam forming circuit according to the present invention. In the invention according to claim 5,
According to the fifth aspect of the present invention, the phase difference monitoring means 52 is connected to (N-1) sets of two antennas adjacent to each other among a plurality of N antennas 51-1 to 51-N arranged at equal intervals. The products of the received waves arriving in parallel are taken, and the average value of these products is obtained. The normalizing means 53 obtains a unit vector whose phase is equal to the argument of a complex number indicating the average value, according to the average value thus obtained. The weight generation unit 54 outputs “0”
An individual integer k that is not less than and not more than (N-1);
N weights W1 to WN given by Z ^k with respect to a complex number Z indicating a unit vector obtained by the normalizing means 53 on a complex plane are generated. The phase shift synthesizing unit 55 includes a reception wave arriving in parallel with the plurality of N antennas 51-1 to 51-N and N weights W1 generated by the weight generation unit 54.
To the sum of WN.

Further, the normalizing means 53 is provided with the above-mentioned claim 1.
Alternatively, it is configured by mounting the two-dimensional vector normalizing device according to claim 2. Therefore, the direction of the transmitting end of the received wave arriving in parallel to the antennas 51-1 to 51-N can be accurately and quickly determined as the N weights described above without significantly increasing the hardware configuration. The component of the received wave estimated and arriving from that direction can be obtained with high accuracy and stability at the output terminal of the phase shift synthesizing means 55.

According to the first aspect of the present invention, the phase-shift difference monitoring means 52 is adjacent to the plurality of N antennas 51-1 to 51-N arranged at equal intervals. Then, the product of the received waves arriving in parallel at the (N-1) sets of two antennas is obtained, and the average value of these products is obtained. The normalizing means 53A calculates, according to the average value thus obtained,
Obtain a complex argument whose phase indicates its average value. The weight generation unit 54A calculates N pieces of integers k that are greater than or equal to “0” and less than or equal to (N−1) and the declination θ obtained by the normalization unit 53A by kθ. N weights W1 to WN having individual declination angles and equal absolute values are generated. The phase shift synthesizing unit 55A includes a plurality of N antennas 51.
Received waves arriving in parallel to -1 to 51-N and weight generation means 5
The product sum with the N weights W1 to WN generated by 4A is calculated.

Further, the normalizing means 53A is constituted by mounting the two-dimensional vector phase extracting device according to the third or fourth aspect. Therefore, the direction of the transmitting end of the received wave arriving in parallel to the antennas 51-1 to 51-N can be accurately and quickly determined as the N weights described above without significantly increasing the hardware configuration. Estimated components of the received wave arriving from that direction can be obtained with high accuracy and stability at the output terminal of the phase shift synthesizing means 55A.

Further, in the second invention related to the invention described in claim 5, the phase shift synthesizing means 62 arrives in parallel with a plurality of N antennas 61-1 to 61-N arranged at equal intervals. The product sum of the plurality of N received waves and the plurality of N weights W1 to WN is calculated, and predetermined components of these received waves are extracted. The monitoring means 63 calculates the product of the component thus extracted and the known standard signal, and obtains a complex number indicating the average value of the product. The normalizing means 64 obtains a unit vector whose phase is equal to the argument of the complex number according to the complex number. The estimating unit 65 calculates the product of the unit vector obtained by the normalizing unit 64 and the average value of the effective values of the amplitudes of the plurality of N received waves, and calculates a change in the direction of arrival among the components of the received waves. A phase shift component whose phase fluctuates accordingly is estimated. Control means 66
Are based on an algorithm for compressing the difference between the component extracted by the phase shift synthesizing unit 62 and the phase shift component estimated by the estimating unit 65, and
Update WN.

Further, the normalizing means 64 is constituted by mounting the two-dimensional vector normalizing device according to the first or second aspect. Therefore, the direction of the transmitting end of the received wave arriving in parallel to the antennas 61-1 to 61-N is not greatly increased even if the received wave is accompanied by fading without significantly increasing the hardware configuration. The N weights W1 to WN are accurately and rapidly estimated as the above-mentioned N weights, and the component of the received wave arriving from that direction is obtained with high accuracy and stability at the output terminal of the phase shift synthesizing means 62.

In the third aspect of the present invention, the phase shift synthesizing means 62 arrives in parallel with a plurality of N antennas 61-1 to 61-N arranged at equal intervals. The product sum of the plurality of N received waves and the plurality of N weights W1 to WN is calculated, and predetermined components of these received waves are extracted. The monitoring means 63 calculates the product of the component thus extracted and the known standard signal, and obtains a complex number indicating the average value of the product.
The normalizing means 64A obtains the argument of the complex number. The estimating means 65A calculates the product of the unit vector having the argument obtained by the normalizing means 64A and the average value of the effective values of the amplitudes of the plurality of N received waves, and arriving from the components of these received waves. A phase shift component whose phase varies according to a change in direction is estimated. The control unit 66A updates the above-described plurality N of weights W1 to WN based on an NLMS algorithm that compresses a difference between the component extracted by the phase shift combining unit 62 and the phase shift component estimated by the estimation unit 65A. .

The normalizing means 64A is constituted by mounting the two-dimensional vector phase extracting device according to the third or fourth aspect. Therefore, the direction of the transmitting end of the received wave arriving in parallel to the antennas 61-1 to 61-N is not greatly increased even if the received wave is accompanied by fading without significantly increasing the hardware configuration.
The N weights W1 to WN are accurately and rapidly estimated as the above-mentioned N weights, and the component of the received wave arriving from that direction is obtained with high accuracy and stability at the output terminal of the phase shift synthesizing means 62.

FIG. 5 is a block diagram showing the principle of a digital signal processor to which the present invention is applied. In the first digital signal processor shown in FIG. 5, the control means 71 individually sets the operation target, the operation mode, and the handling of the operation result in a storage program control method for a series of operations to be performed as signal processing. Specify based on. The calculating means 72 sequentially performs the calculation on the calculation target specified by the control means 71, the form of the calculation, and the handling of the calculation result. When the form of the operation specified as described above corresponds to the normalization of a complex number, the control unit 71 adds, to the form of the operation, the complex number that is the operation target specified together with the form of the operation, and the operation result Normalization means 7
Give to 3. The normalizing means 73 obtains a unit vector whose argument is equal to the argument of the complex number as an operation result in accordance with the complex number to be operated on. .

The normalizing means 73 is constituted by mounting the two-dimensional vector normalizing device according to the first or second aspect. Therefore, normalization of a complex number to be operated can be realized at a much higher speed and with desired accuracy as compared with the case where it is performed as an arithmetic operation, without a significant increase in hardware size.

Further, in the second digital signal processor shown in FIG. 5, the control means 71 individually determines an operation target, an operation form, and handling of an operation result for a series of operations to be performed as signal processing. Specify based on the storage program control method. The calculating means 72 sequentially performs the calculation on the calculation target specified by the control means 71, the form of the calculation, and the handling of the calculation result. When the form of the operation specified as described above corresponds to the normalization of a complex number, the control unit 71 adds, to the form of the operation, the complex number which is the operation target specified together with the form of the operation, The handling of the result is given to the normalizing means 73A. The normalizing means 73A obtains the argument of the complex number to be operated on as the operation result.

Further, the normalizing means 73A is constituted by mounting the two-dimensional vector phase extracting device according to the third or fourth aspect. Therefore, normalization of a complex number to be operated can be realized at a much higher speed and with desired accuracy as compared with the case where it is performed as an arithmetic operation, without a significant increase in hardware size.

[0042]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 6 is a diagram showing the first to fifth embodiments of the present invention. In the figure, a real part R and an imaginary part I of a complex number to be operated are given to the inputs of latches 81-r and 81-i, respectively.
Outputs of 1-r and 81-i are absolute value converting units 82-r and 82-r, respectively.
Connected to -i input. Further, latches 81-r, 81-i
Are connected to the corresponding control input of the quadrant restoring unit 83. Absolute value conversion units 82-r, 82
The outputs of -i are respectively connected to the corresponding inputs of the comparator 84 and the inputs of the address generators 90-r and 90-i. The two selection outputs of the comparator 84 are connected to the corresponding inputs of the scaling selection unit 85, and the single validity determination output and the two scaling outputs of the scaling selection unit 85 are combined with the address generation units 90-r and 90. Connected to the corresponding input of -i. Outputs of the address generation units 90-r and 90-i are connected to corresponding inputs of the selector 86, and a selection output of the selector 86 is connected to a judgment output of the comparator 84. The output of the selector 86 is connected to the address input of the conversion table 87, and the output of the conversion table 87 is connected to the input of the quadrant restoring unit 83 via the loopback determining unit 88. From the output of the quadrant restoring unit 83, the real part r and the imaginary part i of the unit vector obtained by normalizing the absolute value of the two-dimensional vector given by the real part R and the imaginary part I are obtained.

The return determination unit 88 includes a conversion table 87
Out of the outputs of the selectors 91-1 and 91-1, the outputs corresponding to the upper order and the lower order are input in opposite permutations, and the selection input of the comparator 84 is connected to the selection input. -2. The quadrant restoring unit 83 includes the following selectors 92-r and 92-i and the complement converter 9
3-r and 93-i.

A selector 92-r in which the output of the selector 91-1 is directly connected to one input and the above-mentioned code bit Rs is given to the selection input among the outputs of the latch 81-r; The output of the selector 91-2 is directly connected, and among the outputs of the latch 81-i, the selector 92-i in which the above-mentioned code bit Is is given to the selection input. The output of the selector 91-1 and the output of the selector 92-r. The complement converter 93-r arranged between the other input and the complement converter 93-i arranged between the output of the selector 91-2 and the other input of the selector 92-i. It is a figure explaining operation of an embodiment.

The operation of the first embodiment of the present invention will be described below with reference to FIGS. Latch 81-r, 81
-i holds a value of a real part R and an imaginary part I whose sign is added from the outside and a sign bit is added as an MSB and whose negative number is represented as "two's complement". Absolute value conversion unit 82
-r and 82-i determine the absolute values of the real part R and the imaginary part I held in the latches 81-r and 81-i, respectively.

In the following, the absolute values obtained in this manner are represented as absolute values | R | and | I |, respectively. Comparator 84 calculates these absolute values | R
│, │I│, one of which has a larger value (hereinafter simply referred to as
That. ) Is given to the scaling selector 85.

Further, the comparator 84 determines whether or not the absolute value | R | is greater than the absolute value | I |, and outputs the result of the determination (hereinafter, referred to as selector 86, 91-r, 91-i). , "Binary identifier"). For the sake of simplicity, the result of such a determination will be described below as a logical value “1” when the result of the determination is true, and a logical value “0” when the result of the determination is false. Suppose that it is given as binary information.

The scaling selecting section 85 determines "whether or not the logical value of any bit included in the large term is valid" 1 "", and the result of the determination (hereinafter, "validity determination result") ) And “bit number” indicating the most significant bit whose logical value is valid “1” among the bits included in the large term. Give to -i.

Only when the above-mentioned "validity determination result" is true, the address generation units 90-r and 90-i use the "bit number" paired with the "validity determination result" as "scaling information". Contains as an MSB the order indicated by
Bit strings Br and Bi whose word lengths are specified values are extracted from the absolute values | R | and | I |, respectively.

In the following, the above-described bit sequence Br,
The absolute values given as Bi are referred to as “scale absolute value Ras” and “scale absolute value Ias”, respectively. In the following, it is assumed that such a word length is “6 bits” for simplicity.

However, when the "validity determination result" is false, the address generators 90-r and 90-i output the value "0" as the scale absolute value Ras and the scale absolute value Ias, respectively. By the way, in the conversion table 87, both the real part X and the imaginary part Y are given as positive integers on the complex plane, and an inequality expression Only when it is satisfied, these real parts X in accordance with the read address given by (2 ⁶ · Y + X)
And the imaginary part Y, the absolute value of the two-dimensional vector represented by is converted to “1”, and the argument θ
Are stored in advance with the coordinates of the end point of the unit vector in which is stored.

If the above-mentioned general term identifier is "1", the X≥Y selector 86 generates a 12-bit address in which the scale absolute value Ras is packed lower than the scale absolute value Ias. And that address is given to the conversion table 87 as a read address.

On the other hand, when the major item identifier is “0”, the selector 86 generates a 12-bit address in which the scale absolute value Ras is packed higher than the scale absolute value Ias, and The address is given to the conversion table 87 as a read address.

Accordingly, the process of generating such a read address by the selector 86 is described as follows: "In the first quadrant on the complex plane shown in FIG. 7, the selector 86 virtually passes through the origin and has a gradient of 45 degrees. This corresponds to “turnback processing for artificially generating a vector corresponding to“ a vector indicated by coordinates (Ras, Ias) of an end point ”” for a straight line.

Further, the conversion table 87 indicates that the read address given by any of the following formulas in the two-dimensional vector whose end point is located only in the area indicated by shading in FIG. When given, a positive number coordinate (xt, yt) indicating the end point of the unit vector corresponding to the vector to which the coordinate of the end point is given by the read address is output as a binary number (= 2 ⁶ · yt + xt).

²⁶ · Ias + Ras · ²⁶ · Ras + Ias In the return determination unit 88, the selectors 91-1 and 91-2 are:
If the above-described large-term identifier is “0”, a binary number (= 2 ⁶ · xt + yt) is generated by transposing the order of the upper 6 bits and the lower 6 bits of the binary number, and the binary number is generated. To the quadrant restoring unit 83.

On the other hand, when the general identifier is “1”, the selectors 91-1 and 91-2 store the binary numbers ( = 2 ⁶ · yt + xt). In the quadrant restoration unit 83, the complement conversion units 93-r and 93-i
The absolute value is equal to the positive number given by the lower 6 bits and the upper 6 bits of the binary number given by, and a negative number represented by "two's complement" is output.

The selectors 92-r and 92-i are, respectively, a positive number indicated by the lower order of the binary number and a negative number generated by the complement converter 93-r in accordance with the logical values of the sign bits Rs and Is. By selecting either one of the positive number indicated by the higher order of the binary number and the plurality generated by the complement converter 93-i.
The two-dimensional vector represented by the real part R and the imaginary part I held by the latches 81-r and 81-i and the real part r and the imaginary part of the unit vector located in the same quadrant on the complex plane and having the same declination angle. And outputs the part i.

Here, these real part r and imaginary part i
Is assumed to be 16 bits for simplicity. As described above, according to the present embodiment, the conversion table 87 is hatched in FIG. 7 and, as shown in FIG. 8, the size thereof is the same as that of the conversion table 13 shown in FIG. Value less than one-eighth (= 8 kilobytes
^{(≒ 16 × 2 12/8} ) ... corresponds to about 0.01% of the conventional example. ) And converted into the number of gates, the latches 81-r, 81i, and the absolute value conversion unit 82-r, which are configured by hardware smaller than the size of the conversion table 87,
82-i, a comparator 84, a scaling selecting unit 85, an address generating unit 90-r, 90-i, a selector 86, a loopback determining unit 88, and a quadrant restoring unit 83,
Even when the absolute value and the phase angle of a desired two-dimensional vector frequently and widely change, normalization for rapidly and accurately converting the absolute value to “1” is achieved.

Therefore, in an apparatus or system equipped with the two-dimensional vector normalizing apparatus according to the present embodiment,
The reliability is improved in conjunction with the reduction in cost, size and weight without performance degradation, and a margin for thermal design is secured especially for small devices that require high-density mounting. In addition, various added values can be flexibly achieved.

In the present embodiment, the real part r and the imaginary part i of the unit vector obtained by converting the absolute value of the desired two-dimensional vector into "1" are obtained. However, the present invention is not limited to such a configuration, for example,
By configuring the “two-dimensional vector normalizing device” according to the present embodiment and a “two-dimensional vector phase angle extracting device” that differs in the following points, it is also possible to obtain only the phase angle of a desired two-dimensional vector. is there.

In the conversion table 87, as shown in FIG. 7, the end points are the real part X (0 ≦ X ≦ 2 ⁷ −1) and the imaginary part Y (0
≦ Y ≦ only deflection angle θ of the given vector 2 ⁷ -1) Ru stored in advance. When the logical value of the large identifier is “0”, the loopback determining unit 88 takes the complement of the phase angle θ given by the conversion table 87, and when the logical value of the large identifier is “1”, the return angle determination unit 88 sets the phase angle θ to any The correction angle is calculated by not performing the processing.

The quadrant restoring unit 83 outputs a code bit Rs,
A desired two-dimensional vector phase angle is obtained by adding any one of 0 radian, 90 degrees, 180 degrees, and 270 degrees to this correction angle according to the combination of the logical values of Is. Hereinafter, the operation of the second embodiment of the present invention will be described with reference to FIGS. The difference between the present embodiment and the above-described first embodiment is that two inputs directly connected to the outputs of the absolute value conversion units 82-r and 82-i as shown by a dashed line in FIG. The point is that the scaling selecting unit 85A provided in place of the scaling selecting unit 85 is provided.

Note that such a scaling selection unit 85
The operation of each unit other than A is the same as the operation in the first embodiment described above, and the description thereof is omitted here. The scaling selection unit 85A stores the absolute value conversion unit 8 in two built-in shift registers (not shown).
The absolute values given by 2-r, 82-i | R |, | I |
And by repeatedly determining whether the logical value of any of the MSBs is "1" while shifting both bits by one bit in parallel, these absolute values |
R |, | I | are identified as words having a common word length of 6 bits or less, and the “bit number” indicating the position of the most significant bit included in these words is shifted in these shift registers. Obtained as the number of bits performed.

Further, the scaling selection unit 85a determines whether the above-mentioned “bit number” is obtained during a period in which the number of bits shifted in the above-mentioned shift register is given as a value equal to or more than a prescribed upper limit value. , And the "validity determination result" whose logical value is "1" is given to the address generation units 90-r and 90-i together with the "bit number". That is, the scaling of the absolute values | R | and | I | is achieved by the scaling selecting unit 85A configured to include a sequential circuit and performing an operation equivalent to the operation performed by the scaling selecting unit 85.

Therefore, as long as the speed at which the above-described shift register can repeatedly perform the shift operation is large enough to ensure the desired response and real-time performance, the absolute value |
Even if the word lengths of R | and | I | are long or set to various values, the circuit size can be reduced with high accuracy. Hereinafter, a third embodiment of the present invention will be described.

The difference between the present embodiment and the above-described second embodiment is that, as shown in FIG. 6, a scaling selecting section 85B is provided instead of the scaling selecting section 85A, and a conversion table 87 is provided instead of the conversion table 87. Conversion table 87A
Is provided. In the present embodiment, the scaling selection unit 85B identifies, as relative errors, rounding errors that occur in the absolute values | R | and | I | due to shifting of the two shift registers described above, and determines that these relative errors are predetermined. If the value exceeds the upper limit, the shift operation is interrupted, and a "bit number" is output at that time.

As shown by hunting in FIG. 7, the conversion table 87B corresponds to the value that the "bit number" can take in response to the interruption of the shift operation, and the phase angle is 45 degrees or less. For a region that shows a two-dimensional vector on a complex plane, it corresponds to all possible values of the real part and the imaginary part of the two-dimensional vector, and the end point of the unit vector having the same phase angle as the two-dimensional vector. The coordinates are registered in advance.

Note that such a scaling selection unit 85
The operation of each unit other than B is basically the same as the operation in the above-described second embodiment, and a description thereof will be omitted. That is, the scaling of the absolute values | R | and | I | is flexibly performed within a range where the above-described relative error does not exceed the predetermined upper limit, and the conversion table 87A that is adaptable to such scaling is provided.

Therefore, according to this embodiment, for example, as shown by hatching in FIGS. 9A and 9B, the word length L of the absolute values | R | and | I | Generator 90-r, 9
0-i, the number k of valid bits cut out from these absolute values | R |, | I | and given to the conversion table 87B as a read address via the selector 86, and stored in the conversion table B in advance. With the accuracy according to the combination with the number of words W to be performed,
Compared with the above-described second embodiment, normalization of a desired two-dimensional vector is realized with higher accuracy.

Hereinafter, a fourth embodiment of the present invention will be described. The difference between the present embodiment and the second embodiment described above is that, as shown in FIG.
The point is that a scaling selection unit 85C is provided instead of 5A. In the present embodiment, the scaling selection unit 85C
Is true when absolute values | R | and | I | are rounded by the shift of the two shift registers (the logical value of a bit that disappears as a borrow is “1”). When the shift is completed, “1” is added to the lower bit of the LSB, and then “bit number” is obtained.

As described above, according to the present embodiment, the absolute value |
Since the error generated in the process of scaling R | and | I | is reduced, for example, as shown by hunting in FIG. 9, compared with the second and third embodiments described above,
The desired two-dimensional vector normalization is accurately achieved.

Hereinafter, a fifth embodiment of the present invention will be described. The difference between the present embodiment and the second to fourth embodiments is that the scaling selecting units 85A and 85A
The following processing is performed by 5B and 85C. The scaling selection units 85A, 85B, and 85C determine the real part | R | and the imaginary part | I
| And outputs a 2-bit status indicating the combination, as indicated by the two-dot chain line in FIG. 6.

That is, according to the present embodiment, an apparatus including and / or one of the “two-dimensional vector normalizing device” and the “two-dimensional vector phase angle extracting device” according to these embodiments is provided. In the system, a state in which both or one of the real part R and the imaginary part I is given or regarded as “0” is identified, and a process adapted to such a state can be started.

Therefore, it is possible to flexibly adapt to various specifications and environments as compared with the case where the above-described second to fourth embodiments are applied. FIG. 10 is a diagram showing a sixth embodiment of the present invention. In FIG. 10A, antennas 101-1 to 101-4 are arranged at equal intervals, and feed ends of these antennas 101-1 to 101-4 are connected to one input of multipliers 102-1 to 102-4, respectively. And the corresponding input of the correlation processing unit 103. An output of the correlation processing unit 103 is connected to an input of a weight generation unit 105 via a normalization processing unit 104, and first to fourth outputs of the weight generation unit 105 are output from multipliers 102-1 to 102-4. Connected to the other input. The outputs of these multipliers 102-1 to 102-4 are connected to the corresponding inputs of adder 106,
In 6, a received wave is obtained.

Hereinafter, the operation of this embodiment will be described. Correlation processing section 103 couples received wave pairs (3) of three sets of two antennas adjacent to each other, among received waves E1 to E4 arriving in parallel to antennas 101-1 to 101-4, respectively. E1, E2), (E2, E3),
By taking the product of (E3, E4), a phase difference having the phase difference Δθ1 to Δθ3 of the pair of these received waves as a phase angle is obtained.
Generate two vectors.

Further, the correlation processing unit 103 calculates the sum of these vectors, and further integrates the sum in the order of time series (actually, it is realized as a weighted integration based on an exponential smoothing method or the like). , (E1, E2), (E2, E3), (E3, E4)
Phase differences Δθ1 to Δθ1 generated according to both the arrangement of the antennas 101-1 to 101-4 and the above-mentioned arrival direction of the received wave.
A complex number C having an average value Δθa of θ3 as an argument is obtained.

The normalization processing section 104 includes a correlation processing section 103
Regardless of the absolute value of the complex number C calculated by the above, the complex number Cn is generated by normalizing the absolute value of the complex number C to “1”, and the complex number Cn is given to the weight generation unit 105. The weight generation unit 105 includes the multiplier 102
Each to -1～102-4 "1 + j0", Cn, Cn ^2,
Cn ³ is given as a weight.

Multipliers 102-1 to 102-4 and adder 106
Means that the total directivity of the array antenna composed of the antennas 101-1 to 101-4 is maintained in the above-described direction of arrival by calculating the product sum of the received waves E1 to E4 and these weights. The normalization processing unit 104 is configured by applying the two-dimensional vector normalization device according to any of the first to fifth embodiments described above.

That is, the size of the hardware of the beam forming circuit constituting the array antenna in cooperation with the antennas 101-1 to 101-4 is greatly reduced as compared with the conventional example.
Further, as described above, “the process of obtaining the complex number Cn by normalizing the absolute value of the complex number C to“ 1 ”” is performed between the transmitting ends of the reception waves E1 to E4 and the antennas 101-1 to 101-4. Even when the transmission characteristics of the individually formed wireless transmission path or the transmission power transmitted from the transmission end thereof changes widely or suddenly, the transmission is performed accurately and stably.

Therefore, the array antenna to which the present invention is applied is applicable to various multiple access systems, modulation systems, frequency allocations, channel allocations, zone configurations, transmission speeds, channel control systems, etc. applied as a radio transmission system. In addition to flexible adaptation, mounting on small devices becomes possible. Furthermore, devices and systems to which such an array antenna is applied can be reduced in size, weight, and cost without deteriorating performance, and are restricted by the physical environment and space to be installed. Significantly eased.

In this embodiment, the correlation processing unit 103
The normalization processing unit 104 and the weight refining unit 105 connected in cascade are arranged at the subsequent stage. However, the present invention is not limited to such a configuration. For example, as shown in FIG. 10 (b), the two-dimensional vector phase angle extracting device according to any one of the above-described first to fifth embodiments is applied. Is provided in place of the normalization processing unit 104, and a weight generation unit 108 is provided in place of the weight generation unit 105. The phase difference extraction unit 107 and the weight generation unit 108 May be configured by performing the above processing.

The phase difference extracting section 107 is provided with the correlation processing section 1
03 is output as a scalar quantity. The weight generation unit 108 ^calculates e ^j0 , e
given ^j θ, e ^j2 θ, respectively four complex numbers represented by e ^j3 theta multiplier 102-1 to 102-4 as a "weight"
You.

FIG. 11 is a diagram showing a seventh embodiment of the present invention. In the drawing, antennas 111-1 to 111-4 are arranged at equal intervals, and these antennas 111-1 to 111-4 are arranged at equal intervals.
-4 is connected to one input of each of the multipliers 112-1 to 112-4, and the amplitude component reproducing unit 113 and the control unit 114
Connected to the corresponding input. Multipliers 112-1 to 11
A corresponding output of the control unit 114 is connected to the other input of 2-4, and outputs of the multipliers 112-1 to 112-4 are connected to corresponding inputs of the adder 115, respectively. The outputs of the adder 115 include the antennas 111-1 to 111-1.
A received wave generated by combining received waves arriving in parallel with 1-4 under processing described later is obtained, and the received wave is provided to one input of a multiplier 116 and a subtractor 117. . The other input of the multiplier 116 is provided with a reference signal d which is a pilot signal or a training sequence to be superimposed on the received wave and applied to the identification of the received wave as described later. The output of the multiplier 116 is connected to one input of a multiplier 120 via an averaging unit 118 and a normalization processing unit 119 which are cascaded.
A first output of the amplitude component reproducing unit 113 is connected to the other input of 0. The output of the multiplier 120 is connected to the other input of the subtractor 117, and the output of the subtracter 117 and the second output of the amplitude component reproducing unit 113 are connected to the corresponding input of the control unit 114.

Hereinafter, the operation of the present embodiment will be described. The multipliers 112-1 to 112-4 and the adder 115 are connected to the antenna 1
Received waves x ⁽¹⁾ , x arriving in parallel with 11-1 to 111-4
^(2), x ^(3), the product-sum of x ^(4), the weight W provided by the control unit 113 as will be described later ^(1), and W ^(2), W ^(3), W ⁽⁴⁾ To obtain a channel estimation vector y.

On the other hand, the multiplier 116 obtains a product of such a channel estimation vector y and the above-mentioned reference signal d, thereby obtaining a complex number having a phase difference between the two as an argument. The averaging section 118 averages the complex numbers, thereby suppressing the variation in the argument of the complex number caused by the variation in the transmission characteristics of the wireless transmission path and the like. The normalization unit 119 generates a unit vector indicating the phase difference between the channel estimation vector y and the reference signal d by normalizing the absolute value of the complex number in which the variation of the argument is suppressed to “1”.

The amplitude component reproducing section 113 outputs the received wave x
^{For (1)} , x ⁽²⁾ , x ⁽³⁾ , and x ⁽⁴⁾ , the amplitude coefficient K represented by the following expression is set to a predetermined period (for example, a positive number of the symbol period of these received waves). Equal).

K = 1 / [| x ⁽¹⁾ | ² + | x ⁽²⁾ | ² + | x ⁽³⁾ | ² + | x ⁽⁴⁾ | ² ] ^1/2 = 1 / S ^1/2 (1) The multiplier 120 takes the product of the unit vector described above and the amplitude coefficient K to obtain a channel estimation vector y
And a component ξd corresponding to the phase difference between the channel estimation vector y and the reference signal. The subtractor 117
An error ε given by the following equation for the component ξd and the channel vector y is calculated.

Ε = ξd−y (2) The control unit 114 receives the reception wave represented by S in the above equation (1).
The sum of squares S of the amplitude of
Based on the constant step coefficient μ,
Weights given by the following four recurrence formulas
⁽¹⁾ _n, W⁽²⁾ _n, W ⁽³⁾ _n, W^(Four) _nIs the weight W described above.⁽¹⁾,
W⁽²⁾, W⁽³⁾, W^(Four)Are sequentially calculated.

W ⁽¹⁾ _n = W ⁽¹⁾ _n-1 + μ · ε _n-1 ^* · x ⁽¹⁾ _n-1 / S _n-1 W ⁽²⁾ _n = W ⁽²⁾ _n-1 + μ .Epsilon.n _-1 ^* .x ⁽²⁾ _n-1 / _Sn- 1W ⁽³⁾ _n = W ⁽³⁾ _n-1 + .mu..epsilon.n _-1 ^* .x ⁽³⁾ _n-1 / _{Sn -1} W ⁽⁴⁾ _n = W ⁽⁴⁾ _n-1 + μ ・ ε _n-1 ^* · x ⁽⁴⁾ _n-1 / S _{n-1 In} these recurrence formulas, the symbol “*” is a complex Means conjugate.

As described above, in the present embodiment, the unit vector indicating the phase difference between the channel estimation vector y and the reference signal is obtained by the two-dimensional vector normalizer according to any of the first to fifth embodiments described above. The NLMS (Normalized LeastMeasurement) is achieved by applying the NLMS (Normalized LeastMeasurement), which is accurately and quickly calculated and achieved by referring to the unit vector.
an square error), weights W ⁽¹⁾ , W ⁽²⁾ , W ⁽³⁾ , W
^{In (4)} , the error of the amplitude and the phase of the received waves x ⁽¹⁾ , x ^{( 2)} , x ⁽³⁾ , and x ⁽⁴⁾ are both highly accurately and stably maintained.

Therefore, due to fading or the like, the amplitudes and phases of the received waves x ⁽¹⁾ , x ⁽²⁾ , x ⁽³⁾ , x ⁽⁴⁾ vary widely, and the above-described variation in the arrival direction. Even if the phase difference between these received waves x ⁽¹⁾ , x ⁽²⁾ , x ⁽³⁾ , x ⁽⁴⁾ can be similarly changed due to the By accurately normalizing the step coefficient μ by the sum of squares (= S), a desired received wave can be received stably.

FIG. 12 is a diagram showing an eighth embodiment of the present invention. In the figure, a program counter 120, a main memory 121, and an operation unit 122 are connected to corresponding input / output terminals of a control unit 123, and the operation unit 122 is a general-purpose operation unit 125 connected to an internal bus 124, a normalization unit 126
And the declination extractor 127. Further, the internal bus 124 has a data RAM 128, a data ROM 12
9 and an input / output interface (I / O) 130 are connected, and the input / output interface 130 forms a bidirectional data link with an externally connected device (not shown).

Hereinafter, the operation of the present embodiment will be described. The main memory 121 stores in advance a machine language sequence that individually indicates a form of operation to be sequentially performed as a program indicating a predetermined signal processing procedure, an operation target, and a combination of operation results. In the following, for the sake of simplicity, the relevant information is stored or stored in the storage area of the data RAM 128 or the data ROM 129 or the input / output interface unit 130 for the purpose of simplification. It is assumed that a data link (port) to be formed and provided to input and output of the information is provided as a pointer indicating based on a predetermined addressing scheme.

Further, in the data ROM 129, constants to be appropriately referred to in the course of calculation are stored in a predetermined format in advance. Further, in the storage area of the data RAM, variable registers and arrays in which variables generated in the course of the operation or externally given should be stored as appropriate are arranged in advance.

The control unit 123 analyzes the machine language stored in the storage area indicated by the program counter 120 out of the machine language sequence stored in the main memory 121 to obtain the form of the operation to be executed, The calculation target and the calculation result are specified, and the analysis result including the calculation target and the calculation result is supplied to the calculation unit 122. Further, the arithmetic unit 122 includes a general-purpose arithmetic unit 125
Only if this analysis result means that the operation target is a complex number and the form of the operation does not correspond to either "normalization" or "declination extraction" of the complex number. And the data RAM 1 opposing via the internal bus 124
In cooperation with the data ROM 129 and the input / output interface unit 130, an operation (including a complex operation) adapted to the analysis result is performed.

When the above-described analysis result indicates that the complex number to be operated should be normalized, the normalizer 126 stores the complex number (stored in the data RAM 128 or the data ROM 129, or The calculation is performed to update the absolute value to “1” while keeping the argument of the interface unit 130). Furthermore, when the above-described analysis result means “extraction of the argument of a complex number to be operated on”, the argument extractor 127 performs an operation to acquire the argument of the complex number.

When any one of the general-purpose calculator 125, the normalizer 126, and the argument extractor 127 completes the predetermined process, the calculator 122 performs the following process. If a corresponding operation result is to be given to the data RAM 128 or the input / output interface unit 130, the operation result is stored or output autonomously, and then the control unit 123 is notified.

The corresponding operation result is stored in the data RAM 12
8 or the input / output interface unit 130
If it is not necessary to output to the outside via
The calculation result is delivered to the control unit 123 together with the above notification.

If the corresponding machine language is a "branch instruction", the control unit 123 sets the address of the branch destination included in the machine language in the program. After incrementing the program counter, the operation described above is repeated. Also, the normalizer 126
The declination extractor 127 is configured by applying the two-dimensional vector normalizer and the two-dimensional vector phase angle extractor according to the above-described first to fifth embodiments, respectively.

That is, the normalization of complex numbers and the extraction of declination performed by the normalizer 126 and the declination extractor 127, for example, are performed in such a manner that the value of the absolute value varies widely and rapidly. Even if it is obtained, the size of the hardware is not greatly increased as compared with the case where it is performed as an arithmetic operation by the general-purpose arithmetic unit 125 operating under the wiring logic or microprogram control,
Performed at high speed and with high accuracy.

Therefore, the DSP according to this embodiment
Devices with increased performance and the ability to incorporate a wide variety of added values in any combination without being constrained by power consumption, packaging density, thermal design, or other physical constraints. . In the sixth to eighth embodiments described above, the present invention is applied to the beam forming circuit configuring the array antenna and the DSP performing signal processing based on a program control method.

However, a predetermined complex operation is performed on a complex number whose absolute value can change widely or at a high speed, and such a complex number is normalized or an argument of the complex number is extracted. If required, the invention is not limited to the beamforming circuits and DSPs described above, but includes, for example, filters such as fading equalizers and echo cancellers, modulators, demodulators, encoders, decoders, It can be applied to the fields of voice synthesis, image synthesis, image processing, pattern recognition, etc. in addition to dedicated hardware for realizing a receiver, a diversity receiver, and the like. The present invention can also be applied to realizing each of the receiving processes including the compensation for the offset of.

(Supplementary Note 1) The argument is equal to the argument of the complex number, and the absolute value is “10” for each combination of the possible binary values of the real part and the imaginary part of the complex number. The storage means in which the coordinates of the end point of the unit vector on the complex plane, which is "1", are stored in advance, and the signs of the real part and the imaginary part of the complex number are stored. A quadrature limiting means for obtaining a permutation by rearranging in descending order and obtaining a complex vector whose end point coordinates on the complex plane are given by the permutation; and coordinates of an end point of the complex vector obtained by the quadrant limiting means. The coordinates of the end point registered in the storage means are acquired corresponding to the above, and the coordinates are reversibly rearranged with respect to the rearrangement performed by the quadrant limiting means, and the code restoration is performed. Applying A two-dimensional vector normalizing device, comprising: a quadrant restoring means for obtaining a unit vector obtained by converting the absolute value of the complex number into "1".

(Supplementary Note 2) The argument is equal to the argument of the complex number, and the absolute value is “10” for each combination of the possible binary values of the real part and the imaginary part of the complex number. The storage means in which the coordinates of the end point of the unit vector on the complex plane, which is "1", are registered in advance, and the real part and the imaginary part of the complex number are shifted in bit units in parallel, and the upper limit given to the natural n Less than the value "2 ⁿ " and "2 ^n-1 "
A value that is the above, a scale unit that scales the real part and the imaginary part, and obtains coordinates of an end point registered in the storage unit corresponding to a result of the scale performed by the scale unit, A two-dimensional vector normalizing device, comprising: vector conversion means for obtaining a unit vector obtained by converting the absolute value of the complex number to “1”.

(Supplementary Note 3) In the two-dimensional vector normalizing device according to Supplementary Note 2, the scaler may be configured so that a ratio of a relative error of a rounding error generated separately between a real part and an imaginary part is equal to or less than a predetermined upper limit value. A two-dimensional vector normalization apparatus, wherein the real part and the imaginary part are shifted, and the coordinates of the end point corresponding to all of the scales that can be applied by the scaler are registered in the storage in advance.

(Supplementary Note 4) In the two-dimensional vector normalizing apparatus according to Supplementary Note 2, the vector conversion unit may determine whether the real part and / or the imaginary part of the result of the scale performed by the scale unit is LSB. A two-dimensional vector normalizing apparatus that carries out rounding up or truncation in accordance with the magnitude relationship between a lower order value and a predetermined threshold value.

(Supplementary Note 5) In the two-dimensional vector normalization apparatus according to any one of Supplementary Notes 1 to 4, all bits of a real part and an imaginary part to be applied to the storage means are referred to. Identify combinations whose value is "0",
A two-dimensional vector normalization device comprising an alarm unit for outputting a status indicating the combination.

(Supplementary Note 6) A storage unit in which the argument of the complex number is registered in advance in correspondence with all possible combinations of binary values of the real part and the imaginary part of the complex number, respectively, The signs of the real and imaginary parts of are stored, and the permutation is obtained by rearranging the absolute values of these real and imaginary parts in descending order, and the coordinates of the end point on the complex plane are given by the permutation. Quadrant limiting means for obtaining a complex vector to be obtained, and a declination registered in the storage means corresponding to the coordinates of the end point of the complex vector obtained by the quadrant delimiting means. Correction of the change caused by the sorting process performed by the means,
A two-dimensional vector phase extracting apparatus, comprising: a quadrant restoring means for restoring a quadrant shown on the complex plane as a combination of the codes, and obtaining a declination of the complex number.

(Supplementary Note 7) A storage unit in which the argument of the complex number is registered in advance for each combination of the possible binary values of the real part and the imaginary part of the complex number, The real part and the imaginary part of are shifted in bit units in parallel, and the upper limit value “2 ⁿ ” given to the natural n
A scaler that scales the real part and the imaginary part to a value that is less than and equal to or greater than “2 ⁿ⁻¹ ”; and the storage means corresponding to a result of the scale performed by the scaler. A two-dimensional vector phase extracting apparatus, comprising: a vector converting means for obtaining a registered argument.

(Supplementary Note 8) In the two-dimensional vector phase extracting apparatus according to supplementary note 6, the quadrant restoring means may include a real part and an imaginary part of the coordinates of the end point of the complex vector applied when referring to the storage means. A two-dimensional vector phase extraction apparatus, which performs rounding up or down of both or one of them according to the magnitude relationship between the value of the lower order of the LSB and a predetermined threshold value.

(Supplementary Note 9) In the two-dimensional vector phase extracting apparatus according to Supplementary Note 7, the scaler may be configured so that a ratio of a relative error of a rounding error individually generated between a real part and an imaginary part is equal to or less than a predetermined upper limit value. By shifting these real and imaginary parts,
A two-dimensional vector phase extracting apparatus, wherein a declination adapted to all of the scales that can be applied by the scaler is registered in the storage in advance.

(Supplementary Note 10) In the two-dimensional vector phase extracting apparatus according to Supplementary Note 7 or 8, the vector conversion means may include one or both of a real part and an imaginary part of the result of the scaling performed by the scaling means. About LSB
A two-dimensional vector phase extracting apparatus, which carries out rounding up or truncation according to the magnitude relationship between a lower order value and a predetermined threshold value.

(Supplementary Note 11) In the two-dimensional vector phase extracting apparatus according to any one of Supplementary Notes 6 to 10, in all bits of a real part and an imaginary part to be applied to the reference of the storage means. A two-dimensional vector phase extracting apparatus, comprising: a warning unit that identifies a combination having a value of “0” and outputs a status indicating the combination.

(Supplementary Note 12) A plurality of N arranged at equal intervals
Of the received waves arriving in parallel at (N-1) sets of two antennas adjacent to each other, and a phase difference monitoring means for obtaining an average value of these products; Wherein the two-dimensional vector normalization device according to any one of the above is mounted, and according to the average value obtained by the phase difference monitoring means, the phase of a complex number whose phase indicates the average value is determined. Normalizing means for obtaining a unit vector equal to an angle, individual integers k which are equal to or greater than "0" and equal to or less than (N-1), and a unit vector obtained by the normalizing means are shown on a complex plane. For complex numbers Z and Z ^k
Weight generation means for generating N weights W1 to WN given by the following formulas: received waves arriving in parallel with the plurality of N antennas, and N weights W generated by the weight generation means
1. A beam forming circuit, comprising: a phase-shift combining means for calculating the sum of products of the received waves from 1 to WN and extracting the components of the received waves arriving at these antennas from the direction of the transmitting end of the received waves.

(Supplementary Note 13) A plurality of N arranged at equal intervals
Of the received waves arriving in parallel with (N-1) sets of two antennas adjacent to each other, and a phase difference monitoring means for obtaining an average value of these products; and Appendix 6 to Appendix 11 And a complex number whose phase indicates the average value in accordance with the average value obtained by the phase difference monitoring means. Normalization means for obtaining a declination;
Each of the integers k equal to or greater than “0” and equal to or less than (N−1) and the argument θ obtained by the normalizing means has N argument angles given by kθ. Weight generating means for generating N weights W1 to WN having the same absolute value, receiving waves arriving in parallel with the plurality of N antennas, and N weights W1 generated by the weight generating means.
A phase-synthesizing means for calculating the sum of products of the received waves and the components of the received waves arriving at these antennas from the direction of the transmitting end of the received waves.

(Supplementary Note 14) A plurality of N arranged at equal intervals
N received waves arriving in parallel with the
And a phase shift synthesizing means for extracting predetermined components of these received waves, and a product of the component extracted by the phase shift synthesizing means and a known standard signal, A monitoring means for obtaining a complex number indicating an average value of the products, and a two-dimensional vector normalizing device according to any one of Supplementary notes 1 to 5 are mounted, and the monitoring means is provided by the monitoring means. Means for obtaining a unit vector whose phase is equal to the argument of the complex number according to the complex number, the unit vector obtained by the normalization means, and the average value of the effective values of the amplitudes of the plurality of N received waves. And estimating means for estimating a phase shift component of which the phase fluctuates according to a change in the direction of arrival among the components of the received waves,
A control unit that updates the weights W1 to WN of the plurality N based on an algorithm that compresses a difference between the component extracted by the phase shift combining unit and the phase shift component estimated by the estimation unit. A beam forming circuit characterized by the above.

(Supplementary Note 15) A plurality of N arranged at equal intervals
N received waves arriving in parallel with the
And a phase shift synthesizing means for extracting predetermined components of these received waves, and a product of the component extracted by the phase shift synthesizing means and a known standard signal, A monitoring means for obtaining a complex number indicating an average value of the product, and a two-dimensional vector phase extracting apparatus according to any one of Supplementary notes 6 to 11, are provided, and are obtained by the monitoring means. Normalization means for obtaining the argument of the complex number in accordance with the complex number, a unit vector having the argument obtained by the normalization means, and an average value of the effective values of the amplitudes of the plurality of N received waves. Estimating means for estimating a phase shift component whose phase varies in accordance with a change in the direction of arrival among components of the received wave, and estimating the component extracted by the phase shift synthesizing means and the estimating means. Phase shift component Based on the algorithm the difference is compressed, the beam forming circuit, characterized in that a control means for updating the weights W1~WN of the plurality N.

(Supplementary Note 16) For a series of operations to be performed as signal processing, control means for individually specifying an operation target, an operation form, and handling of an operation result based on a storage program control method, An arithmetic means for sequentially performing, on the operation object, an operation object specified by the means, an operation form, and handling of the operation result; and a two-dimensional image described in any one of the additional notes 1 to 5 And a control unit configured to include a vector normalization device, and a normalization unit configured to obtain, as an operation result, a unit vector whose argument is equal to the argument of the complex number in accordance with the complex number to be operated, and When the specified form of the operation corresponds to the normalization of a complex number, a complex number that is an operation target specified together with the form of the operation, together with the form of the operation, A digital signal processor, wherein handling of a calculation result is provided to the normalizing means.

(Supplementary Note 17) For a series of operations to be performed as signal processing, control means for individually specifying an operation target, an operation form, and handling of an operation result based on a stored program control method, An arithmetic means for sequentially performing an operation suitable for the operation object specified by the means, the form of the operation, and the handling of the operation result on the operation object; and the two-dimensional structure described in any one of the additional notes 6 to 11 A normalization unit configured to include a vector phase extraction device, and obtaining a declination of a complex number to be calculated as a calculation result. When applicable,
A digital signal processor, wherein the normalization means is provided with a complex number, which is an operation target specified together with the operation form, and handling of the operation result, together with the operation form.

[0121]

As described above, claims 1 and 3 (Appendix 1,
According to the invention described in (6), normalization of a desired complex number can be achieved accurately and at high speed while significantly reducing the scale of hardware. Further, according to the inventions described in claims 2 and 4 (supplementary notes 2 and 7), the direction of the transmitting end of the received wave arriving in parallel with the plurality of antennas can be accurately determined without a significant increase in the hardware configuration. , And a component of the received wave arriving from that direction is accurately and stably obtained.

Further, according to the invention described in claim 5 (supplement 12) and appendix 14, the scale of hardware is greatly reduced as compared with the conventional example, and normalization of a desired complex number can be performed with desired accuracy. Will be In addition, in the inventions described in Supplementary notes 4, 8, and 10, the accuracy of normalization to be performed on a desired complex number is maintained high.

Further, in the inventions described in Supplementary Notes 3 and 9, as long as the information amount of the information to be registered in the storage means is small enough to be allowed, the accuracy of the normalization of the complex number can be increased. Further, in the invention described in Appendix 511, performance and responsiveness are maintained at a high level. Further, according to the inventions described in Supplementary notes 14 and 15, the direction of the transmitting end of the received wave arriving in parallel with the plurality of antennas is significantly different from the hardware configuration even when the received wave is accompanied by fading. It is estimated accurately and at high speed without increasing, and the component of the received wave arriving from that direction can be obtained with high accuracy and stability.

In the inventions described in Supplementary Notes 16 and 17,
The normalization of a complex number to be operated is realized at a much higher speed and with a desired accuracy as compared with the case where it is performed as an arithmetic operation, without a large increase in hardware size. Therefore, in the devices and systems to which these inventions are applied, the reliability and the increase in power consumption are minimized without being restricted by the restrictions on mounting and thermal design, and various operations performed as complex operations are performed. In addition to signal processing, it is possible to incorporate many added values.

[Brief description of the drawings]

FIG. 1 is a principle block diagram (1) of a two-dimensional vector normalizing device and a two-dimensional vector phase extracting device according to the present invention.

FIG. 2 is a principle block diagram (2) of a two-dimensional vector normalizing device and a two-dimensional vector phase extracting device according to the present invention.

FIG. 3 is a principle block diagram (1) of a beam forming circuit according to the present invention.

FIG. 4 is a principle block diagram (2) of a beam forming circuit according to the present invention.

FIG. 5 is a principle block diagram of a digital signal processor to which the inventions of claims 1 to 4 are applied.

FIG. 6 is a diagram showing first to fifth embodiments of the present invention.

FIG. 7 is a diagram illustrating the operation of the present embodiment.

FIG. 8 is a diagram illustrating the size of a conversion table reduced according to the present embodiment.

FIG. 9 is a diagram showing the accuracy of an angle obtained in the present embodiment.

FIG. 10 is a diagram showing a sixth embodiment of the present invention.

FIG. 11 is a diagram showing a seventh embodiment of the present invention.

FIG. 12 is a diagram showing an eighth embodiment of the present invention.

FIG. 13 is a diagram illustrating a configuration example of an arithmetic circuit that realizes normalization of a complex number.

[Explanation of symbols]

10, 30 alarm means 11, 21, 31, 41 storage means 12, 32 quadrant limiting means 13, 33 quadrant restoring means 22, 42 scaling means 23, 43 vector conversion means 51, 61, 101, 111 antenna 52 phase difference monitoring means 53, 53A, 64, 64A, 73, 73A Normalizing means 54, 54A Weight generating means 55, 55A, 62 Phase shift synthesizing means 63, 63A Monitoring means 65, 65A Estimating means 66, 66A, 71 Control means 72 Calculation means 81 Latch 82 Absolute value conversion unit 83 Quadrant restoration unit 84 Comparator 85, 85A, 85B, 85C Scaling selection unit 86, 91, 92 Selector 87, 87A, 87B, 133 Conversion table 88 Fold determination unit 90 Address generation unit 93 Complement conversion unit 102, 112, 116, 120, 131, 134 Multiplier 103 Correlation processing unit 104, 119 Normalization processing unit 105, 108 Weight generation unit 106, 115, 132 Adder 107 Phase detection unit 113 Amplitude component reproduction unit 114 Control unit 117 Subtractor 118 Averaging unit 120 Program counter 121 Main storage 122 Arithmetic unit 123 Control unit 124 Internal bus 125 General-purpose arithmetic unit 126 Normalizer 127 Argument extractor 128 Data RAM 129 Data ROM 130 Input / output interface unit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B056 AA01 AA04 BB42 CC03 HH00 HH03 HH05 5J021 AA04 DB01 EA05 FA14 FA16 FA20 FA22 FA29 FA30 GA02 HA06 JA07

Claims (5)

[Claims] 1. The argument is equal to the argument of the complex number and the absolute value is “1” for each combination of binary values that the real part and the imaginary part of the complex number can take respectively. Storage means in which the coordinates of the end point of the unit vector on the complex plane are registered in advance, and the signs of the real part and the imaginary part of the complex number are stored, and the absolute values of the real part and the imaginary part are stored in descending order. A quadrant limiting means for obtaining a permutation by performing the rearrangement and obtaining a complex vector in which the coordinates of the end point on the complex plane are given by the permutation correspond to the coordinates of the end point of the complex vector obtained by the quadrant limiting means. By obtaining the coordinates of the end point registered in the storage means, performing reversible rearrangement on the coordinates performed by the quadrant limiting means and restoring the code, Said Absolute dimensional vector normalizing apparatus characterized by comprising the a quadrant restoration means for obtaining a unit vector comprising been converted to "1" in the prime. 2. The argument of the complex number is equal to the argument of the complex number and the absolute value is “1” for each combination of the possible binary values of the real part and the imaginary part of the complex number. Storage means in which the coordinates of the end point of the unit vector on the complex plane are registered in advance, and the real part and the imaginary part of the complex number are shifted in units of bits in parallel, and the upper limit value given to the natural n A scaler that scales the real part and the imaginary part to a value less than 2 ^{n and} greater than or equal to 2 ^n-1 , and the storage corresponding to a result of the scale performed by the scaler. Get the coordinates of the end point registered in the means,
A two-dimensional vector normalizing device, comprising: vector conversion means for obtaining a unit vector obtained by converting the absolute value of the complex number to “1”. 3. A storage unit in which the argument of the complex number is registered in advance in correspondence with all possible combinations of binary values of the real part and the imaginary part of the complex number, respectively; The permutation is obtained by preserving the sign of the part and the imaginary part, and by rearranging the absolute values of the real part and the imaginary part in descending order, and obtaining the coordinates of the end point on the complex plane by the permutation. A quadrant limiting means for obtaining a vector, acquiring the argument registered in the storage means corresponding to the coordinates of the end point of the complex vector obtained by the quadrant limiting means, and obtaining the argument by the quadrant limiting means A quadrant restoring means for compensating for a change caused in the process of the rearrangement performed and restoring a quadrant indicated on the complex plane as a combination of the signs, and obtaining a declination of the complex number. Characterized by Dimensional vector phase extractor. 4. A storage unit in which the argument of the complex number is registered in advance in correspondence with each possible combination of binary values of the real part and the imaginary part of the complex number, respectively; The part and the imaginary part are shifted in units of bits in parallel, and the real part and the imaginary part are set to a value that is less than the upper limit value “2 ⁿ ” and greater than or ^{equal to} “2 ⁿ⁻¹ ” given to the natural n. Two-dimensional, comprising: a scaler that scales an imaginary part; and a vector converter that obtains a declination registered in the storage corresponding to a result of the scale performed by the scaler. Vector phase extraction device. 5. A product of received waves arriving in parallel with (N-1) sets of two antennas adjacent to each other among a plurality of N antennas arranged at equal intervals, and an average value of these products And a phase difference monitoring means for obtaining the average obtained by the phase difference monitoring means, and a two-dimensional vector normalization device according to any one of claims 1 to 4. Normalizing means for obtaining a unit vector whose phase is equal to the argument of a complex number indicating its average value according to the value; an individual integer k which is equal to or more than "0" and equal to or less than (N-1); Weight generation means for generating N weights W1 to WN given by Z ^k with respect to a complex number Z indicating a unit vector obtained by the normalization means on a complex plane; The incoming received wave and the weight generation means Weights W1 to WN generated by
And a phase shift synthesizing means for extracting a product sum of the received waves and extracting components of the received waves arriving at these antennas from the direction of the transmitting end of the received waves.