JP2001356880A - Data write/read device for hard disk drive - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the write/read device of a hard disk drive capable of reducing costs without reducing any IDE access speed. SOLUTION: This device is provided with an exclusive IDE driver for starting an operation monitoring timer 52 in performing a write/read access, and allowing an IDE bus switching IC circuit 51 to perform the write/read access so that the write/read of data can be simultaneously performed to two normal IDE hard disk drivers 60A and 60B, time reset control means (10, 20) for resetting the operation monitoring timer after the end of the write/read of the data, and related error processing control means (10, 20) for performing related error processing by using an interrupting signal when the operation monitoring timer is timed up beyond the write/read access time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data write / read device for an IDE hard disk drive.

[0002]

2. Description of the Related Art IDE (Integrated Device Ele) used in personal computers and special purpose computers (for example, electronic cash registers).
tronics) Hard Disk Drive (HDD)
Of the data write / read device of RAID (Redund
ant ・ Arrey ・ of ・ Inexpensive ・
5 and 8 are known as a method (configuration) for constructing in the Discus 1 system.

FIG. 5 shows an operating system (OS).
The HDD master 61 and the HDD slave 62 are connected in parallel by the (stem) method, and the entire HDD master 61 and HDD slave 62 are regarded as one hard disk device 60P1 and controlled via the IDE bus, thereby increasing the speed of data write / read and endurance against failure. It is constructed to improve the performance.

That is, the CPU 10P activates the OS stored in the main memory 20P and, as shown in FIG. 6, transfers the data to the HD via the chip sets 31P and 32P.
Writing to the D master 61 continuously. If an error occurs, a warning message is displayed on the screen 34P via the image processing card 33P to notify the user. Next, the data is continuously written to the HDD slave 62. Also in this case, when an error occurs, a warning message is displayed on the screen 34P to notify the user.

[0005] On the other hand, as shown in FIG.
Start the OS stored in the main memory 20P, and
Data is continuously read from the D master 61. If an error occurs, a warning message is displayed on the screen 34P to notify the user, and the data is switched to the HDD slave 62 to continuously read the data.

Incidentally, reference numerals 35 to 37 in FIG. 5 denote PCI slots.

[0007] The dedicated card system shown in FIG.
Commercially available PCI / IDE / RAI connected via I bus
HDD master 61 and HDD in D1 card 51P2
IDE hard disk drives (mirror IDE0, mirror IDE1) 60P2A, 60P2 including slave 62
B constitutes a hard part 50P2 to which B is connected, and C
The PU 10P activates a dedicated IDE driver for the card 51P2 stored in the main memory 20P, and
A commercially available PCI / IDE / RAID1 card 51P2 is controlled via the I bus.

That is, as shown in FIG. 9, the IDE driver includes a mirror IDE0 (60P2A) and a mirror I
HDD masters 61 and H of DE1 (60P2B)
Data is continuously written to the DD slave 62. If an error occurs, a warning message is notified via the PCI bus.

Similarly, the IDE driver continuously reads data from the HDD master 61 and the HDD slave 62 of either the mirror IDE0 or the mirror IDE1, as shown in FIG. If an error occurs, P
A warning message is notified via the CI bus.

[0010]

The OS shown in FIG.
The method can be realized only by the OS on the current hardware such as a personal computer (CPU 10P, main memory 20P, etc.) without depending on the dedicated hardware.
It is low cost. However, since data cannot be simultaneously written to the HDDs 61 and 62 connected in parallel, the IDE access speed decreases.

In the dedicated card system shown in FIG.
Since writing (reading) to the master 61 and the HDD slave 62 can be performed simultaneously, the IDE access speed does not decrease, but the cost increases. Another problem is that one PCI slot is occupied, that is, the load on the PCI bus increases.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a hard disk drive write / read device capable of reducing cost without lowering IDE access speed.

[0013]

According to the first aspect of the present invention, an operation monitoring timer is activated at the time of write access and an IDE is provided.
Operate the bus switching IC circuit for write access and
Data can be written to two IDE hard disk drives at the same time, and the operation monitoring timer is started at the time of read access, and the IDE bus switching IC circuit is read-accessed to select two normal IDE hard disk drives so that data can be read simultaneously. Dedicated IDE driver that can be switched, timer reset control means for resetting the operation monitoring timer after the end of data writing to the IDE hard disk drive, after the end of data reading, or after completion of related error processing, and when the write access time to the IDE hard disk drive is exceeded. Alternatively, the data of the hard disk drive is provided with related error processing control means for performing related error processing using an interrupt signal when the operation monitoring timer times out due to the read access time being exceeded. Light is a read apparatus.

In this invention, the dedicated IDE driver activates the operation monitoring timer at the time of write access and operates the IDE bus switching IC circuit for the write access operation so that two IDE hard disk drives (for example, mirror IDE0 And mirror ID
E1), a normal IDE hard disk drive (e.g., HDD master of mirror IDE0 and H
DD write), starts an operation monitoring timer at the time of read access, and operates the IDE bus switching IC circuit for read access operation to simultaneously perform IDE access of two IDE hard disk drives capable of read access at the same time. It is selectively switched so that data can be read from a hard disk drive (for example, an HDD master or an HDD slave of the mirror IDE0).

[0015] The timer reset control means has a normal ID.
After the data writing to the hard disk drive is completed (or after the data reading is completed or after the related error processing is completed), the operation monitoring timer is reset. The related error processing control means performs related error processing when a write access time to the IDE hard disk drive is exceeded. Also, when the operation monitoring timer times out due to the read access time being exceeded, the related error processing is performed using the interrupt signal.

Therefore, since two units can be simultaneously written and read, the cost can be greatly reduced without lowering the IDE access speed and without using a commercially available PCI / IDE / RAID1 card.

According to a second aspect of the present invention, the IDE bus switching IC circuit and the operation monitoring timer are provided between a chipset under CPU control and the IDE hard disk drive without using a PCI slot. It is a data write / read device for a hard disk drive.

In this invention, the IDE bus switching IC circuit and the operation monitoring timer are provided between the chipset under CPU control and the IDE hard disk drive and do not use a PCI slot.
In addition to providing the same operation and effect as the case of the invention, the PCI bus load can be further reduced.

Further, the invention according to claim 3 is characterized in that the IDE bus switching IC circuit is a Near-Zer of a high-speed CMOS semiconductor.
o A write / read device for a hard disk drive created using the delay characteristics.

In this invention, the IDE bus switching IC circuit is made using the Near-Zero delay characteristic of the high-speed CMOS semiconductor, so that the same operation and effect as those of the first and second inventions are obtained. In addition to being able to play, the cost can be further reduced.

Furthermore, a fourth aspect of the present invention is a write / read device for a hard disk drive, wherein the IDE bus switching IC circuit has a delay characteristic of Tpd ≦ 250 ps.

In this invention, the delay characteristic of the IDE bus switching IC circuit is selected to be Tpd ≦ 250 ps, so that the same operation and effect as those of the invention of claim 3 can be obtained, and more reliably. Speed reduction can be prevented.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

The data write / read device (10, 20, 50) of the present hard disk drive, as shown in FIG.
Operation monitoring timer 52 during write (read) access
And a dedicated IDE driver capable of simultaneously writing (reading) data to two normal IDE hard disk drives 60A and 60B by operating the IDE bus switching IC circuit 51 for write (read) access, and writing (reading) data. ) Timer reset control means (CPU 10, main memory 20) for resetting the operation monitoring timer after termination or after related error processing, and operation monitoring timer 52 when write (read) access time is exceeded.
Related error processing control means (CPU 10, CPU 10) for performing related error processing using an interrupt signal when
A main memory 20) is provided so that the IDE access speed is not reduced as compared with the conventional OS system and the cost can be reduced as compared with the conventional dedicated card system.

In FIG. 1, a hardware unit 50 includes two IDE hard disk drives (mirror IDE) each having an HDD master 61 and an HDD slave 62.
0, mirror IDE 1) 60A, 60B, an IDE bus switching IC circuit 51 for switching these, and an operation monitoring timer (Watchdog Timer) 52.

In this embodiment, the data write / read device is a control unit (CPU 10) for activating a product sales data processing program stored in the main memory 20.
And an external storage device (hard disk drive 60A, 60B) for storing product sales data, which is used as an electronic cash register type product sales data processing system.

Here, the IDE bus switching IC circuit 51
Near-Zero delay characteristics (T
pd ≦ 250 ps. ) And the CPU 1 via the IDE bus and the chip sets 32 and 31.
Connected to 0. Commercially available PCI / IDE / RAID1
It is cheaper than a card.

The operation monitoring timer 52 is started (started) / stopped (stopped) by the dedicated IDE drivers (20, 10), and is capable of monitoring the IDE bus switching IC circuit 51 connected via the IDE bus. Generates an interrupt signal. It is inexpensive compared to commercially available PCI, IDE, and RAID1 cards.

The dedicated IDE driver activates the operation monitoring timer 52 at the time of write access and operates the IDE bus switching IC circuit 51 for write access so that data can be simultaneously written to the two normal IDE hard disk drives 60A and 60B. At the same time, the operation monitoring timer 52 is started at the time of read access, and the IDE bus switching I
The C circuit 51 is operated for read access, and two normal I
This is dedicated software for selectively switching the DE hard disk drives 60A and 60B so that data can be read simultaneously. Stored in the main memory 20;
It is started and executed by the CPU 10.

More specifically, the Truth Tab shown in FIG.
switching signal condition (S1, S2, IOW)
#, IOR #), the IDE bus switching IC circuit 51 switches the buses (A, B1, B2).

Timer reset control means (CPU 10,
The main memory 20) resets the operation monitoring timer 52 after the data write to the IDE hard disk drives 60A and 60B is completed, after the data read is completed, or after the related error processing is completed. This means may be integrally formed as a part of the dedicated IDE driver.

The related error processing control means (CPU 10, main memory 20)
The operation monitoring timer 52 when the write access time to 0A or 60B is exceeded or when the read access time is exceeded.
Performs related error processing using an interrupt signal when the time has expired. This means may be integrally formed as a part of the dedicated IDE driver.

In this embodiment, at the time of write access, the dedicated IDE driver (10, 20) uses the IDE / HDD 60A (6) with "Flag" of the interrupt service program of the operation monitoring timer 52 as shown in FIG.
1, 62), 60B (61, 62)
If there is no problem, the operation monitoring timer 52 is started.

If there is a problem, a warning message is displayed on the screen 34 to notify the user. The operation monitoring timer 52 does not start.

Thus, the IDE bus switching IC circuit 51
Is switched to the write access direction by the signal IOW #, and a normal IDE hard disk drive (60A or 60B) is selected by the signals S1 / S2,
Data is continuously written to the selected IDE hard disk drive [for example, 60A (61, 62)].

In this process, the IDE hard disk drives [60A (61, 62), 60B (61, 6)
2)], when an interrupt signal is output from the operation monitoring timer 52, the dedicated IDE driver activates the interrupt service program.

That is, the mirror IDE0 is output by the signals S1 / S2.
(60A) and the HDD status of the mirror IDE1 (60B) are read, the position of the damaged HDD is subsequently determined, and the S1 / S2 level is set according to the normal IDE. That is, a normal IDE HDD to which data is to be written [60B (61, 6
2)] is automatically set (switched). Finally, dedicated I
DE driver is "Flag" for IDE driver
And exit.

When all data writing is completed, the timer reset control means (10, 20) resets the operation monitoring timer 52 with a start / stop signal.

On the other hand, at the time of read access,
The driver (10, 20), as shown in FIG.
lag ", the IDE / HDD 60A (61, 62) and 60B (61, 62) are diagnosed as to whether or not there is a problem. If there is no problem, the operation monitoring timer 52 is started.

If there is a problem, a warning message is displayed on the screen 34 to notify the user. The operation monitoring timer 52 does not start.

Thus, the IDE bus switching IC circuit 51
Is switched to the read access direction by the signal IOR #, and the normal IDE hard disk drive (60A or 60B) is selected by the signals S1 / S2,
Data is continuously read from the selected IDE hard disk drive [for example, 60A (61, 62)].

In this process, when an abnormality occurs in the IDE hard disk drives 60A and 60B and an interrupt signal is output from the operation monitoring timer 52,
Run the interrupt service program.

That is, the operating mirror IDE0 (60)
A) and the HDD status of the mirror IDE 1 (60B) are read, and the cause of the abnormality is recorded. Continued normal I
The S1 / S2 level is set according to DE. That is, a normal IDE to read data from now on
• Automatically set (switch) to HDD [in this case, 60B (61, 62)]. Finally, the dedicated IDE driver sets “Flag” for the IDE driver and ends the processing.

When all data reading is completed, the timer reset control means (10, 20) resets the operation monitoring timer 52 with a start / stop signal.

According to this embodiment, the operation monitoring timer 52 is activated at the time of write (read) access, and the IDE bus switching IC circuit 51 is written (read).
A dedicated IDE driver (20, 10) capable of simultaneously writing (reading) data to two normal IDE hard disk drives 60A, 60B by performing an access operation, and operating after completion of data writing (reading) or after completion of related error processing Timer reset control means (10, 20) for resetting the monitoring timer, and related error processing for performing related error processing using an interrupt signal when the operation monitoring timer 52 times out due to the write (read) access time being exceeded. A control means (CPU 10 and main memory 20) is provided, and an inexpensive IDE bus switching IC circuit 51 and operation monitoring timer 52 can be employed as compared with the dedicated card system shown in FIG.
DE hard disk drive [60A ... IDE0 (HD
D61, 62) and 60B ... IDE1 (HDD61
62)], it is possible to write and read simultaneously, so that the cost can be greatly reduced and
Does not reduce access speed.

The IDE bus switching IC circuit 51 and the operation monitoring timer 52 do not use PCI slots provided between the chip sets 31 and 32 under the control of the CPU 10 and the IDE hard disk drives 60A and 60B. The PCI bus load can be reduced.

Further, since the IDE bus switching IC circuit 51 is made using the near-zero delay characteristic of a high-speed CMOS semiconductor, the cost can be further reduced.

Further, since the delay characteristic of the IDE bus switching IC circuit 51 is selected so that Tpd ≦ 250 ps,
Slowing can be reliably prevented.

Furthermore, it is possible to provide a low-cost commodity sales data processing system capable of quickly performing commodity sales data processing.

[0050]

According to the first aspect of the present invention, the operation monitoring timer is started at the time of write (read) access and the ID
A dedicated IDE driver capable of simultaneously writing (reading) data to two normal IDE hard disk drives by operating the E bus switching IC circuit for write (read) access, and after completion of data write (read) or related error processing Timer reset control means for resetting the operation monitoring timer later; and related error processing control means for performing related error processing using an interrupt signal when the operation monitoring timer times out due to the write (read) access time being exceeded. Since the data write / read device of the hard disk drive is provided, the cost can be reduced without lowering the IDE access speed.

According to the second aspect of the present invention, the IDE bus switching IC circuit and the operation monitoring timer are provided between the chipset under CPU control and the IDE hard disk drive without using the PCI slot. Therefore, the same effect as that of the first aspect can be obtained, and the load on the PCI bus can be further reduced.

According to the third aspect of the present invention, the IDE bus switching IC circuit is a high-speed CMOS semiconductor Near-Ze
Claim 1 because it is created using the ro delay characteristic.
In addition to achieving the same effects as in the case of the invention of claim 2, the cost can be further reduced.

Further, according to the invention of claim 4, IDE
Since the delay characteristic of the bus switching IC circuit satisfies Tpd ≦ 250 ps, the same effect as in the case of the third aspect of the invention can be obtained, and further, the speed can be more reliably prevented from being reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram for explaining a Truth Table that regulates a switching operation of an IDE bus switching IC circuit.

FIG. 3 is a flowchart for explaining a write operation of a dedicated IDE driver.

FIG. 4 is also a flowchart for explaining a read operation of a dedicated IDE driver.

FIG. 5 is a block diagram for explaining a conventional example (1).

FIG. 6 is a flowchart illustrating a write operation.

FIG. 7 is a flow chart for explaining a read operation.

FIG. 8 is a block diagram for explaining a conventional example (2).

FIG. 9 is a flowchart for explaining a write operation.

FIG. 10 is a flowchart illustrating a read operation.

[Explanation of symbols]

10 CPU (dedicated IDE driver, timer reset control means, related error processing control means) 20 Main memory (dedicated IDE driver, timer reset control means, related error processing control means) 31, 32 chipset 33 image processing card 34 screen 35, 36, 37 PCI sto 50 Hardware section 51 IDE bus switching IC circuit 52 Operation monitoring timer 60A, 60B IDE hard disk drive 61 HDD master 62 HDD slave

Claims (4)

[Claims] 1. An operation monitoring timer is activated at the time of a write access, and data can be simultaneously written to two normal IDE hard disk drives by operating an IDE bus switching IC circuit for a write access, and an operation monitoring timer at the time of a read access. Is activated and the IDE bus switching IC circuit is read-accessed to operate two normal IDs.
A dedicated IDE driver capable of selectively switching data read to the E hard disk drive at the same time; timer reset control means for resetting an operation monitoring timer after data write to the IDE hard disk drive is completed, after data read is completed, or after related error processing is completed; A related error processing control means for performing related error processing using an interrupt signal when an operation monitoring timer times out due to an excess of a write access time or an excess of a read access time to an IDE hard disk drive. Data write / read device. 2. The IDE bus switching IC circuit and the operation monitoring timer are provided between a chipset under CPU control and the IDE hard disk drive without using a PCI slot.
A data write / read device for a hard disk drive as described. 3. The IC bus switching IC circuit according to claim 1, wherein
3. The write / read device for a hard disk drive according to claim 1, wherein the write / read device is created by using Near-Zero delay characteristics of an OS semiconductor. 4. The write / read device for a hard disk drive according to claim 3, wherein a delay characteristic of the IDE bus switching IC circuit is Tpd ≦ 250 ps.