JP2001356152A - Integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a test result from being affected even when flip-flops constituting a scan path are operated at the same time. SOLUTION: A driver circuit D2 having the driving capability smaller than that of a normally used driver circuit D1 is provided on the flip-flops constituting the scan path, and the driver circuit D2 having the smaller driving capability is used in a scan mode guiding data on the scan path. Since the driver circuit having small electric power is used, switching noise is reduced, and a stable test can be conducted. The data stored on the flip-flops are not changed by the through current generated when the flip-flops constituting the scan path are simultaneously operated, and the diagnostic result on an LSI(large scale integration) tester is prevented from failing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit, and more particularly to an integrated circuit having a scan path operation mode for performing a test using a scan path.

[0002]

2. Description of the Related Art Generally, a test of an integrated circuit is performed by setting a circuit state one clock before, operating the circuit, and checking whether data output as a result of the operation matches an expected value. In order to set the circuit state, a scan path circuit may be provided in the integrated circuit in advance.

This scan path circuit is realized by forming a shift register by flip-flops. If this scan path circuit is provided in an integrated circuit in advance, the circuit can be operated with each flip-flop holding predetermined data, and the output result can be derived. By comparing this output result with the expected value, it is possible to judge the quality of the integrated circuit itself. That is,
If the output result does not match the expected value, the integrated circuit can be determined to be defective.

The scan path circuit is realized by connecting flip-flops in series in a chain to form a shift register. For example, as shown in FIG. 3, flip-flops 11 to 16 are connected in series to form a shift register. Each flip-flop 1
When the predetermined data is held in 1 to 13, the shift input S
Data is applied to I and a clock C is applied. Thereby, the data is sequentially shifted to the position to be held. The clock C is cut off at the position to be held, and the shift operation is stopped. In this state, the integrated circuit operates normally.

[0005] The output of the result of this operation is held in flip-flops 14 to 16 constituting a shift register, and then a clock C is applied to perform a shift operation. By doing so, the output result for the data input by the scan path circuit can be externally derived as the shift output SO. Then, by comparing the output result with the expected value, the quality of the integrated circuit can be determined.

Incidentally, as shown in FIG. 4, a selector SEL is generally provided at the input stage of each flip-flop 10 constituting the shift register. In addition to the normal input IN, this selector SEL
A shift input SI is provided, and these are alternatively input by a control signal SE.

FIG. 5 shows an example of the internal configuration of the flip-flop 10.
Is shown in Referring to FIG. 1, a flip-flop 10 is a well-known D-type flip-flop, and includes a master-side latch circuit M, a slave-side latch circuit S to which an output of the latch circuit M is input, and a clock supplied to the latch circuit M. The circuit includes an inverter 5 for inverting C and applying the inverted signal to the latch circuit S, and a driver circuit D1 for leading the output of the latch circuit S to the outside.

The master-side latch circuit M includes inverters 1 and 2 connected to each other to receive the output of the other side as an input.
And has a well-known latch circuit configuration. Similarly, the slave side latch circuit S also includes inverters 3 and 4 connected to each other so as to receive the output of the other side, and has a well-known latch circuit configuration.

According to this configuration, the D input is held in the master latch circuit M at the rising transition timing of the clock C, and the held content is held in the slave latch circuit S at the falling transition timing of the clock C. The contents held by the slave side latch circuit S are led out to the outside by the driver circuit D1. The driving capability of the driver circuit D1 is determined according to the number of signal branches to an externally connected circuit.

[0010]

In the above-described shift operation of the scan path circuit, all flip-flops constituting the shift register operate simultaneously. The output stage of each flip-flop is CMOS (Complement
tarry Metal Oxide Semiconductor
(actor) transistor structure, when all flip-flops operate simultaneously, a through current flows.
At the same time, the output terminal of the integrated circuit operates in synchronization with the operation of the flip-flop, and a through current flows. Then, switching noise occurs, and the operation of the integrated circuit itself becomes unstable.

By the way, a transistor having a large driving capability (a large driving current) is generally used for an output portion of each flip-flop constituting the shift register. This is because the output of the flip-flop is often branched and input to a plurality of circuits. At the same time, the output terminal of the final output stage of the integrated circuit operates in synchronization with the operation of the flip-flop, and a through current flows. Such a transistor having a large driving capability has a high operation speed of the device itself and has large switching noise. This means that the test result becomes unstable even though the scan circuit is provided for the test.

In order to solve this problem, it is conceivable to prevent the flip-flops from operating simultaneously. However, it is impossible to prevent simultaneous changes due to the characteristics of the scanning operation.

As described above, in the conventional integrated circuit, the data stored in the flip-flop changes due to the simultaneous operation of the flip-flop and the through current caused by the simultaneous change of the output terminal. There is a disadvantage that the diagnosis result may be failed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and its purpose is to affect the test results even when the flip-flops operate at the same time and the output terminals change simultaneously. It is to provide an integrated circuit that does not provide.

[0015]

SUMMARY OF THE INVENTION An integrated circuit according to the present invention is an integrated circuit that operates in one of a first operation mode in which normal operation is performed and a second operation mode in which internal circuits operate simultaneously. A first driver circuit used for deriving data in the first operation mode; and a second driver circuit used for deriving data in the second operation mode, wherein the driving capability of the first driver circuit is included. The driving capability of the second driver circuit is smaller than that of the second driver circuit. In addition, the control circuit further includes a control circuit for selectively controlling the first driver circuit and the second driver circuit to an enabled state.

The first driver circuit and the second driver circuit are provided at a data output stage of a scan path constituted by connecting flip-flops in series,
The second operation mode is a scan path operation mode for performing a test using the scan path. In the test, the own circuit is operated in a state where predetermined data is input to flip-flops constituting the scan path, and an operation result is derived by the scan path.

Further, the first driver circuit and the second driver circuit are provided at a final output stage of the own circuit,
The second operation mode may be a mode in which the internal circuit operates simultaneously in synchronization with an internal clock.

In short, according to the present invention, a driver circuit having a smaller driving capability than a normally used driver circuit is provided, and when data is derived from the scan path circuit, the driver circuit having the smaller driving capability is used. . In the test, since high-speed operation is not required, there is no problem even if operation is slower than normal operation.

Similarly, the driver circuit at the final output stage of the integrated circuit itself also corresponds to the two operation modes.
Different types of driver circuits are provided, and a driver circuit having a small driving capability is used in a mode in which the internal circuits operate simultaneously, and a driver circuit having the same driving capability as in the related art is used in a normal operation mode. As a result, the through current does not increase at the output terminal due to the simultaneous operation of the internal circuits.

[0020]

Next, an embodiment of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, the same parts as those in the other drawings are denoted by the same reference numerals.

FIG. 1 is a block diagram showing an embodiment of an integrated circuit according to the present invention. As shown in the figure, the integrated circuit according to the present embodiment is different from the conventional integrated circuit in that driver circuits D1 and D2 having different driving capabilities are provided, and these are used alternatively. . The driving capability of the driver circuit D2 is smaller than that of the driver circuit D1. The control signal SE for controlling the selector SEL (not shown) is input to the driver circuit D2 as it is. On the other hand, a signal obtained by inverting the control signal SE by the inverter 6 is input to the driver circuit D1.

With such a configuration, in the normal operation mode, the driver circuit D1 is controlled to an effective state, and data is derived using this. At this time, the driver circuit D
2 is not used and its output is in a high impedance state.

On the other hand, in a scan path operation mode for performing a test using the scan path, the driver circuit D2 is controlled to an effective state, and data is derived using the driver circuit D2. At this time, the driver circuit D1 is not used, and its output is in a high impedance state.

That is, by providing the inverter 6, the driver circuit D1 and the driver circuit D2 are selectively controlled to be valid. Note that the driver circuit D
A well-known three-state buffer may be used for 1 and the driver circuit D2.

In the present invention, a scan path circuit is realized by connecting flip-flops configured as described above in series in a chain to realize a shift register. If the scan path circuit is provided in the integrated circuit in advance, the quality of the integrated circuit itself can be determined as described above. As described above, in the scan mode, by using a driver circuit with a small driving capability and a small power, switching noise is reduced and a stable test can be performed. That is, the data stored in the flip-flop does not change due to the through current caused by the simultaneous operation of the flip-flop, and the diagnosis result does not fail on the LSI tester. Since a low-power driver circuit is used, in the scan operation mode, the integrated circuit operates in the low-power mode, so that power consumption can be reduced.

By using a low power driver, the delay to the next scan interface is increased. Then, as a result, the margin of the hold time (hold time) in the shift operation increases.
Thereby, the skew of each flip-flop with respect to the clock (clock skew; clock skew)
The degree of freedom increases.

This will be described with reference to FIG. When the driving capability of the driver circuit is large, the operation of each flip-flop becomes faster. Then, as shown in the figure, the clock may penetrate. That is, when the flip-flops 11 to 14 are connected in series, when the clock C is input to the flip-flop 11 as shown by the arrow Y1 and the output of the flip-flop 11 is determined, the clock C is output at a timing later than the determined timing. C indicates a flip-flop 12 as indicated by an arrow Y2.
May be entered. Then, flip-flop 1
The output of 1 propagates to the output of the flip-flop 12 as shown by the arrow Y3. That is, the clock penetrates.

On the other hand, when the driving capability of the driver circuit is small, the operation of each flip-flop becomes slow, and the propagation delay to the next-stage flip-flop increases. Then, the phenomenon that the clock penetrates as shown in the figure does not occur. Therefore, a design margin for the hold time in the shift operation can be provided. This increases the degree of freedom in skew for the clock distributed to each flip-flop,
This gives you more time to design an integrated circuit.

Although the driver circuit at the output stage inside the flip-flop constituting the scan path has been described above, the present invention is not limited to this, and the present invention can be similarly applied to the driver circuit at the final output stage of the integrated circuit itself. . That is, the driver circuit of the final output stage of the integrated circuit itself is also provided with two types of driver circuits (not shown) corresponding to the two operation modes, and is driven in a scan path mode or the like in which internal circuits operate simultaneously. A driver circuit having a small capacity is used, and in a normal operation mode, a driver circuit having the same drive capacity as that of the related art is used. As a result, in the output terminal portion, the through current caused by the simultaneous operation of the internal circuits does not increase.

Regarding the description of the claims, the present invention can further adopt the following aspects.

(1) The integrated circuit according to any one of claims 1 to 5, wherein the first and second driver circuits are constituted by CMOS transistors.

(2) The flip-flop includes a master-side latch circuit and a slave-side latch circuit that receives an output of the latch circuit as an input, and the flip-flop includes one of the first driver circuit and the second driver circuit. 5. The integrated circuit according to claim 3, wherein an output of said slave-side latch circuit is led out to an outside by a driver circuit controlled to an effective state by said control circuit.

(3) The master-side latch circuit and the slave-side latch circuit are constituted by two inverters connected to each other so that one output is input. Integrated circuit.

[0034]

As described above, according to the present invention, the driving capability of the second driver circuit used for deriving data in the scan path operation mode is higher than the driving capability of the first driver circuit used for deriving data in the normal operation mode. In the design of the scan path, there is an effect that a low power mode is set during a scan operation, a through current due to a simultaneous change is reduced, and a stable test can be realized. In addition, an increase in the delay value of the flip-flop increases the degree of freedom of skew for clock distribution of the scan path circuit, and has an effect that a margin can be given in designing an integrated circuit.

Similarly, the driver circuit of the final output stage of the integrated circuit itself also corresponds to the two operation modes.
By providing driver circuits of different types, using a driver circuit with a small driving capability in a mode in which the internal circuits operate simultaneously, and using a driver circuit with the same driving capability as in the past in a normal operation mode, There is an effect that the through current generated by the simultaneous operation of the internal circuits does not increase.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a flip-flop used for an integrated circuit according to the present invention.

FIG. 2 is a block diagram illustrating an operation example of a scan path circuit configured using flip-flops.

FIG. 3 is a diagram showing a general configuration of an integrated circuit.

FIG. 4 is a block diagram illustrating a configuration example of a flip-flop used in a conventional integrated circuit.

FIG. 5 is a block diagram showing a configuration example of a main part of the flip-flop in FIG. 4;

[Explanation of symbols]

 1-6 Inverter 10-16 Flip-flop D1, D2 Driver circuit M Master side latch circuit S Slave side latch circuit SEL selector

Continued on the front page F term (reference) 2G032 AA00 AB01 AC10 AK14 AK15 AK16 AL00 5F038 AV06 DF06 DF16 DT02 DT06 DT15 EZ20 5J056 AA05 BB17 BB19 BB24 CC00 CC14 DD13 DD29 EE15 FF01 FF07 FF08 GG12

Claims (5)

[Claims] An integrated circuit that operates in one of a first operation mode in which a normal operation is performed and a second operation mode in which an internal circuit operates simultaneously, wherein data is stored in the first operation mode. A first driver circuit used for derivation; and a second driver circuit used for deriving data in the second operation mode, wherein the driving capability of the second driver circuit is higher than the driving capability of the first driver circuit. An integrated circuit characterized by having a small size. 2. The integrated circuit according to claim 1, further comprising a control circuit for selectively controlling the first driver circuit and the second driver circuit to be enabled. 3. The first driver circuit and the second driver circuit are provided in a data output stage of a scan path configured by connecting flip-flops in series. 3. The integrated circuit according to claim 1, wherein the integrated circuit is in a scan path operation mode for performing a test using the integrated circuit. 4. The test according to claim 1, wherein said circuit is operated while predetermined data is input to flip-flops constituting said scan path, and the operation result is derived by said scan path. Item 3. The integrated circuit according to Item 3. 5. The first driver circuit and the second driver circuit are provided in a final output stage of the own circuit, and in the second operation mode, the internal circuit operates simultaneously in synchronization with an internal clock. 3. The integrated circuit according to claim 1, wherein the integrated circuit is in a mode.