JP2001356141A - Electric power detecting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electric power detecting circuit having no error caused by the presence or absence of modulation and a modulation system. SOLUTION: When a signal Sin to be measured including a high-frequency component is inputted to the electric power detecting circuit 10, a level adjuster 20 amplifies and/or attenuates the signal Sin to be measured and outputs it as an adjusted signal Sadj based on a fed control signal Sg. A detector 22 detects the adjusted signal Sadj and outputs a detection voltage Vdet. A voltage comparator 24 acquires a reference voltage Vref having a fixed voltage and outputs a comparison signal Scomp indicating the potential difference of the detection voltage Vdet from the reference voltage Vref. The comparison signal Scomp is outputted to the outside of the electric power detecting circuit 10 as a detection signal and fed to the level adjuster 20 as the control signal Sg. The electric power Padj of the adjusted signal Sadj is adjusted to the reference detection electric power value Padj0 set in a range where a detector 22 has a prescribed linearity. The detection signal Sout outputted to the outside of the electric power detecting circuit 10 shows the high-frequency electric power value of the measured signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power detection circuit which outputs a detection signal representing a high-frequency power value of a signal under measurement when a signal under measurement including a high-frequency component is input.

[0002]

2. Description of the Related Art For example, in order to eliminate interference in CDMA communication of the DS (Direct Spreading) system, the power of a mobile station is controlled with high accuracy so that the strength of a signal reaching a base station is made uniform. It has become important to more accurately detect the power of a signal wave, such as minimizing the power. Examples of a circuit that detects high-frequency power of an electric signal include a power detection circuit that determines power based on a detection voltage obtained by detecting a signal to be measured, which is a target of power measurement, by a detector.

This circuit comprises, for example, a diode, a logarithmic amplifier, a root mean square (DC) converter (RMSto DC converter).
Is used as a detector to detect an input signal wave and use the detected voltage itself to know the high-frequency power of the signal wave.

[0004]

However, in the conventional power detection circuit, depending on the power level of the signal to be modulated, if the state of modulation, for example, the type of modulation and / or the degree of modulation is different, the detection characteristics of these detectors will be different. Do not match, and accurate power value measurement cannot be expected. In particular, CD
When the number of code multiplexes in the MA system, that is, the number of patterns of the spread code code-multiplexed to one carrier frequency is different, the difference in the detection characteristics increases rapidly as the power of the modulated signal exceeds a certain level. , The measurement error of the power value may increase.

[0005] Diode, logarithmic amplifier or root mean square
In a circuit using a DC converter, as the power of the signal wave increases, the error depending on the number of code multiplexes rapidly increases,
Further, in a circuit using a logarithmic amplifier, an error (absolute value) depending on the number of code multiplexes is always, for example, regardless of an increase in power.
About 0.7 [dB] is generated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-precision power detection circuit which overcomes the drawbacks of the prior art.

[0007]

In the power detection apparatus according to the present invention, when a signal to be measured including a high frequency component is input, the level adjusting means amplifies and / or amplifies the signal to be measured based on the supplied control signal. Attenuated and output as adjusted signal. The detection means detects the adjusted signal and outputs a detection voltage. The voltage comparison means acquires a reference voltage having a constant voltage, and outputs a comparison signal representing a potential difference between a detection voltage and the reference voltage. This comparison signal is output as a detection signal and supplied to the level adjustment means as a control signal. Thereby, the power of the adjusted signal is adjusted to the reference detection power value set in a range where the detection means has a predetermined linearity. The output detection signal indicates the high-frequency power value of the signal under measurement.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a power detection circuit according to the present invention will be described in detail with reference to the accompanying drawings. Referring to FIG. 1, an embodiment of a power detection circuit 10 according to the present invention includes a level adjuster 20, a detector 22, and a voltage comparator 24. enter the measurement signal S _in, by entering the reference signal S _ref to the reference input terminal 14, a circuit for outputting a signal S _out representing the high frequency power of the measured signal S _in to the external output terminal 16. The type of modulation of the signal under test S _in is, for example, direct spreading (Dire
ct Spread; DS method and frequency hopping (Freque
For example, spread spectrum modulation for CDMA (code division multiple access) communication such as ncy hopping (FH), and may be any of angle modulation, amplitude modulation, pulse modulation, and the like, or a combination thereof. Also, the signal under measurement S _in
May be an unmodulated signal. Signal under test S
frequency components _in may include frequency and / or lower frequencies, which is usually utilized for wireless communication. In each of the accompanying drawings, the operating power supply of each component is not shown in principle, in order to avoid complexity. In the following description, elements having the same configuration are denoted by the same reference numerals, and each signal is also indicated by the code of a connection line where the signal appears.

A signal source 18 to be measured is connected to an external input terminal 12 of the power detection circuit 10, and a reference signal _Sref is input to a reference input terminal 14. Signal source 18, such as the final stage circuit of the receiving antenna system or transmission device, a circuit for generating a signal as a signal under test S _in. Reference signal
It is preferable that S _ref has a known reference voltage V _ref , the voltage does not change regardless of the operation of the power detection circuit 10, and the ripple content is small. The signal from the signal source 18 may be used as a terminated power meter so that the entire signal is input into the power detection circuit 10, or only a part of the signal may be used as the power detection circuit 10.
It may be used as a pass-through power meter, preferably loosely coupled via a current divider, a voltage divider, a branch circuit or a directional coupler (none of which is shown). The power detection circuit 10 includes a filter (not shown) as necessary.
The signal under test _Sin may be input via this. This filter is a circuit that transmits a predetermined frequency component and blocks the other frequency components, and blocks an unintended frequency component by appropriately selecting a transmission band. Can be expected to be reduced.

[0010] Since the measured signal S _in may contain high frequency components, from the viewpoint of to prevent reflection and loss of the signal to obtain an accurate measurement, via the external input terminal 12 from the signal source 18 power It is preferable to match the output / input impedance of each connection and the characteristic impedance of the connection line up to each component that handles a high-frequency signal inside the detection circuit, that is, up to the detector 22. Further, each connection line and each component may be formed of a planar circuit or a three-dimensional circuit depending on the frequency component of a signal to be handled. External input terminal 12
Is connected to the input terminal of the level adjuster 20.

The level adjuster 20 is a circuit that adjusts the level of the input signal with a controllable power gain, that is, amplifies and / or attenuates the output. Level adjuster 20
Has a control input terminal to which a control signal S _g (described later) is input, in addition to an input terminal to which the signal under measurement S _in is input. Level adjuster 20 includes a control signal that power gain G _p varies based on the S _g, the power level of the power gain G _p in the measured signal S _in amplification and / or attenuated, having a power P _adj Outputs the adjusted signal _Sadj .

[0012] level controller 20, the state of the control signal S _g, the power gain G _p is determined according to the control voltage V _g for example, the voltage of the control signal S _g. That is, the value of the power gain G _p, the control voltage V _g at the corresponding relationship. In the level adjuster 20, the relationship between the power value of the input signal and the power value of the output signal depends on the degree of attenuation / amplification. Specifically, the power of the measured signal S _in, i.e. relationship between the measured power P _in, and the power P _adj of adjusted signal S _adj is determined by the power gain G _p of the level adjuster 20. The value of the power gain G _p may be known from the control voltage V _g, therefore, if the power P _adj of adjusted signal S _adj is known, the value of the control voltage V _g at that time, the measured power P You can ask for _in . The level adjuster 20 is preferably configured such that the value of the power gain G _p [dB] is as accurately as possible proportional to the control voltage V _g [V].

More specifically, the power gain (true numerical value) of the level adjuster 20 is an effective power value at the input side of the level adjuster 20, that is, when the signal source 18 is viewed from the level adjuster 20. (Exact value) and the available power value (exact value) on the output side of the level adjuster 20. Therefore, assuming that impedance matching is preferably performed as described above, the high-frequency power of the signal under measurement S _in is represented by P _in [dBm], and the high-frequency power of the adjusted signal S _adj is represented by P _adj [dBm]. The power gain G _p [dB] of the level adjuster 20 is

[0014]

G _p = P _adj -P _in ... (1) Note that [dBm] is a measure of milliwatt decibels, that is, a measure of power equal to ten times the common logarithm of the ratio of a given power to 0.001 [W]. That is, 1 [m
W] is represented by 0 [dBm].

The level adjuster 20, the control voltage V _g attenuation is increased with increases and decreases the power gain G _p, so that the power gain G _p is attenuation and the voltage V _g drops decreases increases It is good to configure. In this case, as described later, the subsequent circuit, the control voltage V _g and the regulated power P _adj rises is increased,
Adjusted power P _adj is lowered and the control voltage V _g is configured to descend. Further, the level adjuster 20, when a voltage V _g increases with increased power gain G _p, when the voltage V _g drops power gain
G _p may be configured to descend. In this case, as described later, the circuit in the subsequent stage, adjusted power P _adj increases the control voltage V _g is lowered, the control voltage V _g and the regulated power P _adj is lowered configured to rise. The state of the control signal S _g, instead of the control voltage V _g, for example the current value of the control signal S _g, i.e. may be used a control current I _g, the control signal S _g
Using a digital signal obtained by digitally encoding a control value representing the gain of the level adjuster 20 as a control signal _Ig or a digital signal, the power gain G _{p of the} level adjuster 20 is used.
May be configured to be controlled.

The power gain G _p [dB] of the level adjuster 20 attenuates the measurement signal S _in, i.e. 0 [dB] may be configured to vary the range, also the signal S _in to be measured May be configured to power-amplify, that is, to fluctuate in a range of 0 [dB] or more. Also, the power gain G _p [dB] may be varied in a continuous region including 0 [dB] by both attenuation and power amplification.

The aligned input and output level adjuster 20, regardless of fluctuations of the measured signal S _in, the signal source 18 and the level controller 20
If the input / output impedance is not changed between the input and the output, the power gain G _p [dB] is equal to the input-side high-frequency voltage, that is, the measured voltage V _in [V], which is the effective voltage of the measured signal S _in .
From the high-frequency voltage on the output side, that is, the adjusted voltage V _adj [V], which is the effective voltage of the adjusted signal S _adj , G _p = 20 log ₁₀
| V _adj / V _in | For example, if an attenuator or an amplifier is used in which the square of the voltage gain G _v [dB] is proportional to the control voltage V _g [V], the signal under test S _in
Rate waveform, i.e. regardless of the ratio between the average value and the effective value, the level adjuster 20 as power gain G _p is proportional to the control voltage V _g can be easily constituted.

[0018] As described below, the subsequent level adjuster 20, the power P _adj predetermined value of adjusted signal S _adj, that is, the control voltage V _g exceeds the reference detector input power P _ADJ0 increases, the reference If the detector input power is less than P _adj0 , the control voltage V _g
Is configured to descend. Therefore, the level adjuster 20, the output, i.e. the adjusted signal S _adj power P _adj
There always be kept at a reference detector input power P _ADJ0, it is controlled by a control signal S _g. Therefore, when the power detection circuit 10 operates stably and the control is performed sufficiently following the fluctuation of the power P _in of the signal under measurement S _in , it follows the fluctuation of the control voltage V _g. Power gain G _p of level adjuster 20
Is changed, and the power P _adj is constantly adjusted to a predetermined power value, that is, the reference detector input power P _adj0 . Therefore, even if the change in the measured power P _in, since the regulated power P _adj is fixed to the reference detector input power P _ADJ0, it is sufficient to determine the advance this value, also, power gain G at that time _p can be computed from the control voltage V _g at the time of detection. And
And the adjusted power P _adj, from this power gain G _p, can be determined to be measured power P _in the time of measurement. That is, to calculate the measured power P _in [dBm], the reference detector input power
It is _sufficient to subtract the power gain G _p (logarithmic value) from P _adj0 (logarithmic value), and by transforming equation (1),

[0019]

## EQU2 ## It can be calculated by P _in = P _adj -G _p . An output terminal of the level adjuster 20 is connected to an input terminal of the detector 22.

More specifically, referring to FIG. 2A, the level adjuster 20 includes a variable attenuator 26. The variable attenuator 26 is
A controllable attenuation, i.e. a power gain G _patt having a negative value in logarithmic representation, and
It is a circuit that attenuates by _patt and outputs, and may be constituted by any variable attenuator such as a resistance attenuator such as an H-type including a variable resistor or a flat plate-type variable attenuator inserted into a waveguide. It is preferable that the variable attenuator 26 has little waveform distortion and frequency dependency, does not have a change in attenuation or a change in input / output impedance due to a frequency of an input signal, and does not disturb the circuit state of other components. External input terminal 12
Is connected to the variable attenuator 26 via an input terminal of the level adjuster 20 by a connection line S _in . Variable attenuator 26
Attenuates the signal under test S _in , that is, amplifies the power with a power gain G _patt [dB] having a negative value, and outputs the adjusted signal S _adj from the output terminal.

Further, the control input terminal of the variable attenuator 26
The connection line _Sg is connected. The variable attenuator 26 controls the control signal
The state of S _g , for example its power gain G by the control voltage V _g
patt is determined. Therefore, the level adjuster 20, when the measurement signal S _in is input, the power P _in of the measured signal S _in is attenuated by attenuation determined by the control signal S _g, adjusted signal S
Output as _adj . That is, for the power P _in of the measured signal S _in, because will have a negative power gain G _patt [dB], the adjusted signal S _adj power P _adj [dBm] is the measured power P _in ( _Logarithmic value) and the power gain G _patt (logarithmic value). Therefore, the adjusted power _Padj is

[0022]

[Number 3] is given by _{P adj = P in + G patt} ... (3). Also, the level adjuster of this embodiment
Since the gain of 20 is equal to the gain of variable attenuator 26, G _p
= G _patt, and the power P _adj [dBm] of the adjusted signal S _adj output from the level adjuster 20 is given by Expression (3).
Substituting G _p = G _{patt gives}

[0023]

[Number 4] can be obtained by _{P adj = P in + G p} ... (4). Power gain of variable attenuator 26
G _patt may preferably be steplessly changeable according to the state of the input control signal S _g , for example, the control voltage V _g , the control current _Ig, or the numerical value of a code based on digital data. The possible changes steplessly, is intended to include the case where power gain G _p takes discrete values in sufficiently small steps.

For example, when the control voltage V _g increases, the attenuation increases and the power gain G _patt decreases. When the control voltage V _g decreases, the variable attenuator 26 decreases the attenuation and the power gain G _patt.
Is preferably increased. Also, when the control voltage V _g rises, the attenuation decreases and the power gain G _patt increases,
When the control voltage V _g decreases, the attenuation increases and the power gain G
It can also be configured to reduce _patt . Preferably, the power gain G _patt [dB] is preferably proportional to the control voltage V _g [V] as accurately as possible. Such a level adjuster 20 requires only a small number of parts and adjustment points, has a simple structure, and can avoid an error due to distortion of a waveform unique to an active element. The output terminal of the variable attenuator 26 is
The output terminal of the level adjuster 20 is connected to the detector 22.

Referring to FIG. 2B, the level adjuster 20 preferably includes an amplifier 28 in addition to the configuration shown in FIG. 2A. External input terminal 12, the connecting line S _in, via the input terminal of the level adjuster 20 is connected to an input terminal of the variable attenuator 26, an output terminal of the variable attenuator 26 is connected to the input terminal of the amplifier 28 ing. The amplifier 28 is a circuit that amplifies an input signal at a predetermined amplification factor, and amplifies a signal output from the variable attenuator 26 with a power gain G _pamp and outputs the signal. Therefore, the power gain G _p of the level adjuster 20 is the power gain G _patt [dB] of the variable attenuator 26 and the power gain G _p
pamp [dB], that is, G _p = G
given by _patt + G _pamp . Therefore, equation (2)
Substituting this into, the measured power P _in [dBm] is

[0026]

[Number 5] P _in = P _adj - can be calculated by _{(G patt + G pamp) ...} (5). Needless to say, in the embodiment without the amplifier 28, the power gain G
_{It is sufficient} to _{treat pamp} as 0 [dB].

The power detection circuit 10 of the present embodiment gives an accurate measured value within a range where the equation (5) is satisfied. That is, in the power detection circuit 10 of the present embodiment, the power input to the detector 22, that is, the value of the adjusted power P _adj is changed to a constant value, that is, the gain of the gain that can be amplified / attenuated to the reference detector input power P _adj0 . the variation range, is determined range measurable measured power P _in. In other words, the range of power measurable measured signal S _in by the power detection circuit 10 is equal to the variable range of the power gain G _p of the level adjuster 20. When the gain adjustment of the level adjuster 20 is performed only by the variable attenuator 26, the range _in which the measured power Pin is allowed is determined by the gain G of the variable attenuator 26.
Depends on the variable range of _patt . Therefore, in order to obtain a wide measurement range, it is preferable to use the variable attenuator 26 having a wide gain variation range. Or alternatively, an amplifier
As 28 may be a variable amplifier whose gain is varied by the control signal S _g. In this case, the connection line S _g is connected to the amplifier
Connect to 28.

It is particularly preferable that the amplifier 28 has good linearity and small nonlinear distortion, has other distortion characteristics and a good noise figure, and is flat _in the frequency band of the input signal, that is, the frequency band of the signal under test Sin. It is good to have a high degree of amplification. Like the variable attenuator 26, the amplifier 28 preferably has a preferable input / output characteristic without disturbing the circuit state. If the input level to the detector 22 is too low, the effect of noise may increase, but if the amplifier 28 is provided,
Can increase the output level of the level adjuster 20, even if the measured power P _in is low, the reference detector input power
P _adj0 can be set to an optimal level, lower power to be measured
Even S _in it is possible to perform the measurement with high accuracy. That is, the level adjuster 20, by including an amplifier 28, the power P _in of the measured signal S _in is, even when less than the reference detector input power P _ADJ0 a control target value of adjusted signal S _adj, adjusting The used power _Padj is amplified and maintained at the reference detector input power. Therefore, the lower limit of the measurable power range of the input signal is widened, it becomes possible to widen the range of the level of a measurable signal under test S _in.

Still further, the level adjuster 20 may include a plurality of variable attenuators and / or a plurality of amplifiers.
The configuration of this variable attenuator may be the same as that of the above-described variable attenuator 26, but a plurality of variable attenuators having different attenuable ranges may be used. The configuration of this amplifier may be the same as that of the amplifier 28 described above, but a plurality of amplifiers having different levels that can be amplified may be used. The plurality of variable attenuators and / or the plurality of amplifiers may be connected, for example, in series. Thereby, the power measurement range can be further expanded. Also, the plurality of variable attenuators and / or the plurality of amplifiers
For example, they may be connected in parallel. The output terminal of the amplifier 28 is connected to the detector 22 via the output terminal of the level adjuster 20 by a signal line _Sadj .

The detector 22 is a detection circuit that, when a signal is input, detects the signal and outputs a detection voltage. Detector 22 is input to the adjusted signal S _adj from the level adjuster 20, detects the signal, the detection signal S _det having a detection voltage V _det, and outputs to the signal line S _det. If necessary, a circuit such as an input / output transformer or a transmission band limiting filter may be added to the detector 22. The detection circuit is
Preferably, it has a fixed detection characteristic irrespective of the frequency, modulation type, modulation degree, amplitude, etc. of the input wave, and has a square detection characteristic in an input level as wide as possible. Detection element used in the detector 22 preferably has a cutoff frequency higher than the highest frequency of the frequency components of at least the measured signal S _in.

More specifically, the detector 22 is, for example, a diode detector, that is, a detector including one or more diodes as a detecting element, and further including a capacitor and other circuit elements. The detection element may be, for example, a detection diode having a small minority carrier accumulation effect and having a PN junction. Furthermore, not only the diode but also an element having a semiconductor PN junction can be generally used as a detection element. Detector 22 with diode detector
When the diode is operated at a small amplitude as a detecting element, the diode itself has a square characteristic, so that a simple circuit configuration is sufficient. For example, the diode is inexpensive compared with a case where a detecting integrated circuit is used. The detector 22 can be configured. Further, the detector 22 may be configured using, for example, a logarithmic amplifier. If the detector 22 is configured using a logarithmic amplifier, the logarithmic amplifier has a logarithmic amplification characteristic over a higher input level. Therefore, even if the power level of the input signal is higher, the detector 22 having a squared detection characteristic is used. Can be easily configured, and more accurate measurement can be expected. Further, the detector 22 may be configured using, for example, a root-mean-square-DC converter (RMS to DC converter). The root mean square-DC converter is a circuit that converts an effective voltage value of an input signal into a DC voltage. Therefore, it is possible to configure the detector 22 having a square detection characteristic at a wide input level. Since the square of the effective value of the voltage is proportional to the power value, the power detection circuit 10 can be easily configured. Both the logarithmic amplifier and the mean-square-DC detector may be constituted by discrete elements, but are preferably constituted by an integrated semiconductor chip. In this case, the circuit can be constituted more easily. it can.

FIG. 3 is a graph showing an example of the input / output characteristics of the detector 22. This graph shows the output voltage of this detector 22 on the vertical axis.
5 is a semi-logarithmic graph showing input / output characteristics of this detector for each input signal having a different number of code division multiplexes, wherein [mV] and input power [dBm] are displayed on the horizontal axis. 1 code indicates a case where the number of code division multiplexes is 1, and similarly, 2 code indicates a case where the number of code division multiplexes is 2. As the number of code division multiplexes increases, the difference in detection characteristics for each code division multiplex number gradually decreases, and the value of the detection voltage with respect to a certain input power value converges. When the code division multiplexing number is sufficiently large, for example, when the code division multiplexing number is 10 or more than 20, the code division multiplexing number is represented by N and is displayed as Ncode. The number of code division multiplexes is the number of multiplexes when performing multiple access by code spreading at the same carrier frequency, that is, the number of channels that can be accommodated. In the characteristic example of the detector 22, the detector 22 shows a substantially square characteristic. Also, the input power has a certain value,
That is, when the value is equal to or less than P1 shown in the graph, the detection characteristics almost match regardless of the number of code division multiplexing. However, when the input power exceeds this value, the difference in the detection characteristics for each number of code division multiplexes rapidly increases. Therefore, it can be seen that if the input power is equal to or less than P1, an error due to the code division multiplex number can be avoided. Referring to this graph, when the input power is P1, the output voltage is V1, and therefore, in order to substantially eliminate the error due to the detection characteristic, the measurement may be performed in a range where the output voltage is V1 or less. . On the other hand, in order to suppress the influence of noise, it is preferable that the input power is not too small. Therefore, in order to substantially eliminate the error due to the difference in the detection characteristics and reduce the influence of noise, the output voltage of the detector 22, that is, the detection voltage V _det is the output voltage value V1 in the graph shown in FIG. The input power, that is, the adjusted signal S, is set to be slightly smaller.
_The power measurement may be performed by adjusting the power P _adj of the _adj .

Referring to FIG. 4, this is a graph of an example of the characteristics of the detector 22 based on the same data as the graph shown in FIG. This graph is a log-logarithmic graph showing the input / output characteristics of the detector 22 for each input signal having a different number of code division multiplexing. The vertical axis represents the signal intensity display value based on the detection voltage [mV] of the detector 22. [dBm] and input power [dBm] are displayed on the horizontal axis. This graph also shows the input power [dBm] (horizontal axis)
The error [dB] (vertical axis) of the signal strength display value with respect to is also shown.

The conversion from the detection voltage [V] to the signal strength display value [dBm] may be obtained by using a conversion table described below. The conversion table is a table for converting the detection voltage value [V] into the input power value [dBm] to the detector 22.
It can be created by recording the output voltage [V] for each input power [dBm] while changing the power of the input signal in the detector 22 of this embodiment under predetermined conditions in advance. That is, in this conversion table, the input power value to the detector 22 and the detection voltage value have a one-to-one correspondence. In this measurement, the input power value may be measured with a power meter that does not use a detector or a rectifier in the high-frequency circuit so as not to depend on the detection characteristics. This power meter is preferably a power meter that converts an electric signal into heat to obtain a power value. Since the conversion table is made up of discrete values at intervals of 1 [dB] or 0.5 [dB], for example, an intermediate value may be obtained by linearly interpolating the values in this table.

Referring to a curve showing a change in the error from this graph, when the input power [dBm] is equal to or less than P1, the error (absolute value) is approximately 0.2 [dB] and is almost constant. As it exceeds, the error (absolute value) increases rapidly.
Therefore, in consideration of FIGS. 3 and 4, in the measurement by the power detection circuit 10 shown in FIG. 1, in order to substantially remove an error due to a difference in detection characteristics and to reduce the influence of noise, power of inputted signal, i.e. the power P _adj of adjusted signal S _adj is to be slightly smaller than P1 or the input power value in the graph of FIG. 3 and FIG. 4, the level adjuster 20 power gain G Power measurement may be performed by adjusting _p . Returning to FIG. 1, the output terminal of the detector 22 is connected to the input terminal of the voltage comparator 24 by a connection line S _det .

The voltage comparator 24 compares the voltage of one input signal with the voltage of the other input signal, and when the voltage of the other input signal rises and falls with respect to the voltage of one input signal, the voltage of the output signal This is a circuit whose value rises and falls. In the voltage detector 24, when the voltage of each input signal matches in the power detection circuit 10, the voltage value of the output signal becomes constant. The voltage comparator 24 includes, for example, a differential input stage and an operational amplifier (operational amplifier).
plifier) whose output is proportional to the potential difference between the two inputs. In the following description, a case where the difference between the input signal and the reference signal is represented by a voltage value in the output signal will be described. However, the difference may be represented by a current value or a digital signal by a digital signal. Is also good.

Specifically, the voltage comparator 24 has two input terminals and one output terminal. The output terminal of the detector 22 is connected to the measurement-side input terminal by a connection line S _det ,
The reference input terminal 14 is connected to the reference input terminal by a connection line _Sref . The reference input signal _Sref is input to the reference connection terminal via the reference input terminal 14. As described later, the power detection circuit 10 may connect a reference voltage circuit 30 that supplies the reference signal _Sref to the reference input terminal 14. Upon receiving the detection signal S _det from the detector 22, the voltage comparator 24 compares the voltage of the detection signal S _det , that is, the detection voltage V _det, with the voltage of the reference signal S _ref , that is, the reference voltage V _ref. Thus, the comparison signal S _comp having the comparison voltage V _comp that changes according to the level of the potential of the detection voltage V _det with respect to the reference voltage V _ref
Is output. The comparison voltage V _comp changes depending on which of the reference voltage V _ref and the detection voltage V _det has a higher potential. A comparison signal having a comparison voltage V _comp that compares the reference voltage V _ref and the detection voltage V _det and changes depending on which potential is higher
Output S _comp . Operational amplifiers may react sensitively, particularly when the output voltage reverses from positive to negative or from negative to positive, and may become unstable. From the viewpoint of stabilizing the output signal, a hysteresis width may be appropriately set by using the hysteresis in the voltage comparator 24 as long as the sensitivity is not affected. Thereby, malfunction and noise can be suppressed. The output terminal of the voltage comparator 24 is connected to the connection line S
_comp branches, one is connected to the external output terminal 16 by a connection line S _out , and the other is a level adjuster by a connection line S _g
Connected to 20.

With the configuration described above, the voltage comparator 24 calculates and outputs a potential difference between the detection voltage V _{det and} the reference voltage _Vref . Therefore, the detection voltage
When V _det rises, the comparison voltage V _comp rises and the detection voltage
When V _det falls, the comparison voltage V _comp falls. Depending on the configuration of the level adjuster 20, when the detection voltage V _det increases, the comparison voltage V _comp may decrease, and when the detection voltage V _det decreases, the comparison voltage V _comp may increase. By the connection described above, the comparison signal S _comp is branched,
One is output as a control signal _Sg to the level adjuster 20, and the other is output as an external output signal S _out from the power detection circuit 10 to an external device or the like.

In this embodiment, a case where the voltage drop of a signal due to branching can be ignored will be described. Therefore, the voltage V _g of the control signal S _g is the configuration described above, have the same value as the voltage V _comp of the comparison signal S _comp. If the voltage drop is not negligible, the voltage drop may be compensated for. In addition, the adjusted power P _adj is the reference detector input power P
_{The case} where the control voltage V _adj is 0 when stable at _adj0 will be described.
The control voltage S _adj when the adjusted power P _adj is likewise stable
May take a value other than 0.

[0040] Similar to the control voltage V _g, even external output voltage V _out is the voltage of the external output signal S _out, with the same value as the comparison voltage V _comp. Therefore, an external output voltage V _out, the control voltage V _g is equal, also regulated power P _adj is the reference detection power P
_adj0 , which is known, so that the input power P
measurement of _in, that is, to calculate the signal strength indication value.

Referring to FIG. 5, in input / output characteristics of a root-mean-square-DC converter which is an example of the detector 22, the input power
The characteristic of the signal strength display value (vertical axis) for each code division multiplexing number with respect to [dBm] (horizontal axis) increases as the input power [dBm] increases, and the difference with respect to the input power [dBm] ( The absolute value [dB] also rapidly increases when the input power exceeds a predetermined input power [dBm], for example, -15 [dBm] in this graph.

However, referring to FIG.
The characteristic of the signal strength display value (vertical axis) for each code division multiplex number with respect to the input power [dBm] (horizontal axis) in the tenth embodiment is as follows.
In this graph, the difference is small as the input power increases. Also, the error (absolute value) [d
B] is constant at about 0.2 [dB] in this graph, for example, and does not increase even when the input power increases.

For comparison with the power detection circuit 10 described above,
Referring to FIG. 7, the power detection circuit 34 is comprised of detector 22, and detects the measured signal S _in, the voltage V _out of the output signal S _out, that is, the signal strength indication from the detection voltage itself of the detector 22 This is a circuit for obtaining a value.

Referring to FIG. 8, in the power detection circuit 34, when the detector 22 using a diode as a detection circuit is applied, when the input power [dBm] (horizontal axis) increases, the difference in the number of code division multiplexing is increased. It can be seen that the error [dB] of the power measurement due to the increase sharply.

Referring to FIG. 9, in the power detection circuit 34, a detector 22 using a logarithmic amplifier as a detection circuit is used.
Is applied, for example, a constant error of about 0.7 [dB] is recognized in this graph regardless of the input power, and when the input power [dBm] (horizontal axis) increases, the difference due to the difference in the number of code division multiplexing. It can be seen that the error [dB] of the power measurement sharply increases.

Referring to FIG. 10, when the power detector 34 employs the detector 22 using a root-mean-square-DC converter as a detector, the input power [dBm] (horizontal axis) increases. Then, it can be seen that the error [dB] of the power measurement due to the difference in the number of code division multiplexes sharply increases.

Returning to FIG. 1, the power detection circuit 10 further includes
A reference voltage circuit 30 may be provided. The reference voltage circuit 30 _generates a reference signal S _ref having a predetermined voltage, that is, a reference voltage V _ref.
Is a circuit that outputs. The reference voltage circuit 30 may be shared with a power supply circuit (not shown) that supplies power to each element of the power detection circuit 10, or may adjust the output of this power supply circuit with a voltage regulator or the like. . Further, an AC power supply such as a commercial power supply may be rectified and used, or a predetermined battery may be connected and used. The reference voltage circuit 30, a reference voltage signal S _ref having a reference voltage V _ref via a reference input terminal 14, is supplied to the voltage comparator 24. Regardless of the state of the power supply (not shown) that supplies power to the reference voltage circuit, that is, the fluctuation of the power supply voltage, the state of the voltage comparator 24, that is, the load, and the temperature and other external factors, the reference voltage signal _Sref is It is preferable to have a stable output voltage and good output characteristics such as a low ripple rate. Furthermore, it is preferable to maintain good output characteristics even when the state of the load such as the voltage comparator 24, for example, the input impedance changes. The output terminal of the reference voltage circuit 30 is connected to the reference input terminal of the voltage comparator 24 via the reference input terminal 14 and the connection line _Sref .

The power detection circuit 10 may include an output unit 32. The output unit 32 is connected to the external output terminal 16, and when the external output signal S _out is input from the power detection circuit 10, the output unit 32 determines the state of the measured power P from the state of the external output signal S _out , for example, the voltage P _out thereof. a circuit for a more readily available detection value _in, the circuit itself using this detected value,
Alternatively, it is an interface circuit between the circuit to be used and the power detection circuit 10 of the present embodiment. By including the output unit 32, for example, a meter for performing power measurement by a visible display may be configured, or a device for automatically controlling the transmission power and the reception power level may be configured. Specifically, for example, the present invention is applied to a transmission unit, a reception unit, and other devices of a mobile phone base station or a mobile phone radio, and AGC, ALC, TSSI
(Transmitter Signal Strength Indicator) or RSSI (Receiver Signal Strength I)
ndicator; a received signal strength indicator). The output unit includes, for example, an element that converts and outputs the voltage _Vout of the external output signal _Sout into a voltage value or a current value by a predetermined coefficient, or a meter that can operate as a voltmeter, so that the measured unit can be measured in a logarithmic display. Power value P of signal S _in
in [dBm] should be obtained directly. Also, a microcomputer including a memory storing the above-described conversion table may be included, and the input voltage value may be converted into a power value based on the conversion table and output. Further, a display device may be included to visually display the digital data.

In the operating state, the reference voltage circuit 30
The reference signal _Sref has been input to the reference input terminal 14 of the power detection circuit 10 in advance. The signal source 18 is connected to the external input terminal 12 of the power detection circuit 10.

The signal under test _Sin is input from the signal source 18 to the level adjuster 20 via the external input terminal 12. Further, the level adjuster 20, the control signal S _g is inputted from the voltage comparator 24, the state of the control signal S _g, for example power gain G _g of the level adjuster 20 by a control voltage V _g is controlled. When the signal under test _Sin is input, the level adjuster 20
In _p, and outputs signal power amplification / attenuation signal to be measured S _in, i.e. the adjusted signal S _adj to detector 22.

The detector 22 detects the input adjusted signal _Sadj and outputs the detected signal, that is, the detected signal S _det to the voltage comparator 24.

The reference signal _Sref is input to the voltage comparator 24 via the reference input terminal 14 in advance. When the detection signal S _det is input, the voltage comparator 24
_The reference signal V _ref , ie, the reference voltage V _ref , is compared with the voltage of the detection signal S _det , ie, the detection voltage V _det, and the difference between the reference voltage V _ref and the detection voltage V _det is expressed by, for example, a comparison voltage V _comp. Output _comp .

The comparison signal S _comp is branched into two, and one is output to the level adjuster 20 as a control signal S _g . When the voltage V _g of the control signal S _g is increased, reduces the power gain G _p attenuation of the level adjuster 20 is increased, the value of the adjusted power P _adj is increased. When the voltage V _g of the control signal S _g is lowered, increasing the power gain G _p attenuation of the level adjuster 20 is reduced, the value of the adjusted power P _adj is increased. When the detection power P _det increases beyond the reference power _Pref , the control voltage _Vg increases and the detection voltage P
_{When det} decreases below the reference voltage _Pref , the control voltage _Vg decreases. For this reason, the detection power V _det is constantly controlled by raising and lowering the control voltage V _g so as to maintain the reference power value V _ref .

The other of the two split comparison signals S _comp is output to the external output terminal 16 as an external output signal S _out . Voltage V _out of the external output signal S _out is equal to the voltage V _comp of the comparison signal S _comp, level adjuster from the voltage V _out
It is possible to know the power gain G _p of 20, it is possible to determine the power gain G to be measured from the _p power P _in. External output signal S
_out, for example, is input to the output unit 32, the measured power P _in
Is used to indicate the signal strength.

Referring to FIG. 11, the power detection circuit 10 may further include a voltage switch 40. The voltage switch 40 is a voltage conversion circuit that converts the voltage of an input signal into another voltage and outputs the converted voltage. Specifically, the voltage switch 40 may be configured by, for example, a constant voltage regulator circuit. The voltage switch 40 is a connection line between the reference voltage circuit 30 and the voltage comparator 24 shown in FIG.
What is necessary is _just to insert in _Sref . Referring to FIG. 11, the output terminal of the reference voltage circuit 30 is connected to a voltage switch 40 by a connection line _Sref0 .
The output terminal of the voltage switch 40 is connected to the reference input terminal 14 of the power detection circuit 10 by a connection line _Sref1 .
It is connected to the. Upon _{receiving the} reference signal _Sref0 having the voltage _Vref0 , the voltage switch 40 receives another constant voltage Vref0.
and outputs the reference signal S _ref1 having _ref1, the voltage comparator 2
Supply to 4. For example, the voltage V _ref is changed to the lower voltage V _ref1
By lowering the, lower the level of the comparison signal S _comp, change the reference detector input power P _ADJ0 a lower level, even if the level of the measured power P _in is lower and can perform power detection it can. Also, the voltage V _ref is set to a higher voltage.
By increasing the V _ref1, even higher levels of the measured power P _in, it may be able to perform the power detection. Furthermore, Sonaere possible replace the voltage switch 40, by switching the reference voltage V _ref0 and V _ref1, it is possible to arbitrarily select the measurement range of the measured power P _in.

Still referring to FIG. 12, the power detection circuit 10 may include a voltage regulator 42 instead of the voltage switch 40 shown in FIG. The voltage regulator 42 is a voltage conversion circuit that continuously converts the voltage of the input signal according to the voltage control signal and outputs the converted voltage.Specifically, for example, if the voltage regulator 42 is configured by a voltage regulator circuit whose output voltage can be adjusted. Good. Voltage regulator 42 is connected as in the above-mentioned voltage switching circuit 40, the voltage control signal S _s is input to the further voltage control terminal. Upon _{receiving the} reference signal S _ref0 having the voltage V _ref0 , the voltage regulator 42 outputs the reference signal S _ref2 having the reference voltage V _ref2 according to the voltage control signal S _s and supplies the same to the voltage comparator 24. The voltage regulator 42 receives the voltage control signal S _s
Fluctuates, the reference voltage V _ref within the adjustment range
To a lower or higher voltage to provide an arbitrary reference voltage _Vref2 . Therefore, by supplying the lower / higher arbitrary reference voltage V _ref2 to the voltage comparator 24 changes comparison signal S _comp lowering the level of / raising, the reference detector input power P _ADJ0 to a lower / higher levels and, it is lower / higher levels of the measured power P _in, power can be detected. Therefore, even if a wide range of the measured power P _in, the reference detector input power P _adj arbitrarily selected, it is possible to perform accurate measurement.

Referring to FIG. 13, the power detection circuit 50 may include a voltage comparator 24A that performs a logical operation using a digital circuit, instead of the voltage comparator 24 that performs an analog operation using the linear element shown in FIG. . Voltage comparator 24A
Is a two-input subtraction circuit that calculates a potential difference between an input voltage and a reference voltage using a logic operation circuit. More specifically, referring to FIG. 14, the voltage comparator 24A includes AD (analog-digital) converters 52 and 54, a comparison operation circuit 56, a level converter 58, and a DA (digital-analog) converter 60.
And a control unit 62. The connection line S _det from the output terminal of the detector 22 is connected to the input terminal of the AD converter 52 via the input terminal of the voltage comparator 24A. The AD converter 52 is a conversion circuit that converts a voltage value of an input analog signal into a digital signal by, for example, encoding, and outputs the digital signal. Upon receiving the detection signal S _det , the AD converter 52 converts the value of the detection voltage V _det into a digital representation and outputs the digital representation.
The output terminal of the AD converter 52 is the input terminal of the comparison operation circuit 56.
Connected to (+).

Further, a connection line _Sref from the output terminal of the reference voltage circuit 30 is connected to the AD converter 54 via the reference input terminal 64 of the voltage comparator 24A. The AD converter 54
What is necessary is just to have the structure similar to AD converter 52. AD converter
Upon receiving the reference signal _Sref , the 54 converts the value of the reference voltage _Vref into a digital representation and outputs it. The output terminal of the AD converter 54 is connected to the input terminal (-) of the comparison operation circuit 56.

The comparison operation circuit 56 is a digital operation circuit which has two inputs and one output, and calculates and outputs the difference between one input value and the other input value. The comparison operation circuit 56 calculates the value input to the input terminal (−), that is, the reference voltage V _{det from} the value input to the input terminal (+), that is, the value of the detection voltage V _det.
The value of _ref is subtracted, and the subtracted value is output in digital representation. The subtraction value output from the comparison operation circuit 56 means the value of the comparison voltage V _comp . Comparison arithmetic circuit 56
Are connected to the level converter 58 and the DA converter 60.

The level conversion unit 58 is a conversion function unit that performs a predetermined operation on the input digital representation value and outputs the result.
The level converter 58 converts the output signal from the comparison operation circuit 56 into
The output unit 32 and the like may have a function of converting the data into a signal having a data format usable by an external device. Further, for example, it may have a DA (digital-analog) conversion function and may be configured to output as a voltage or a current. Preferably, it is preferable to include a memory for storing the processing program in a fixed or rewritable manner and an arithmetic processing circuit, to calculate the signal strength and to directly output the digital or analog signal.

The DA converter 60 is a conversion circuit that converts an input digital expression value into, for example, a voltage value using an analog signal and outputs the voltage value. The DA converter 60 converts the subtraction value in digital representation into a voltage and outputs it as a comparison signal S _comp . The output terminal of the DA converter 60 is connected to the voltage comparator 24
Connected to A output terminal.

The control section 62 is a control function section for integrally controlling the operation of the voltage comparator 24A. The control unit 62 preferably includes a memory that stores the processing program in a fixed or rewritable manner, and an arithmetic processing circuit. The input / output circuit of the control unit 62 is connected to each unit in the voltage comparator 24A.

The voltage comparator 24A having the above-described function may be constituted by a PIC (Programmable IC), that is, a programmable integrated circuit. The PIC may have a central processing function and include a memory area for storing processing programs and data in a read-only or rewritable manner, an input / output interface unit, a clock generator, and the like. For example, if a PIC in which the function of the voltage comparator 24A is integrated on one chip or one board is used, the voltage comparator 24A can be easily and compactly constructed.

Referring to FIG. 15, power detection circuit 70 is different from power detection circuit 10 shown in FIG.
And a plurality of level adjusters 20A and 20B. The input terminal of the amplifier 72 is connected to the external input terminal 12. Amplifier 72, an inputted signal, i.e. an amplification circuit that amplifies the measured signal S _in, the same structure as those of the aforementioned amplifier 28. Amplifier 72, and outputs the power-amplified signal to be measured S _in. The output terminal of the amplifier 72 is connected to the input terminal of the level adjuster 20A.

The level adjusters 20A and 20B may have the same configuration as that of the above-described level adjuster 20, but may be configured to optimally adjust the inputtable power value. Level adjuster 20A
, 20B is by respective connection lines S _g, the voltage comparator 24
Output terminal. Level adjusters 20A in accordance with the control signal S _g, amplifies / attenuates the output signal from the amplifier 72, and outputs. The output terminal of the level adjuster 20A is connected to the input terminal of the level adjuster 20B. Level adjuster 20B in accordance with a control signal S _g, amplifies / attenuates the output signal from the level adjuster 20A, and outputs. The output terminal of the level adjuster 20B is connected to the input terminal of the detector 22. If necessary, a level adjuster other than the level adjusters 20A and 20B may be connected in series. By providing the amplifier 72, even lower measured power P _in can perform power detection, also, by providing a plurality of level adjuster can be wider range of possible power detection .

Referring to FIG. 16, compared to the power detection circuit 10 shown in FIG. 1, the power detection circuit 80 further includes a temperature sensor.
82 and any one or more of the temperature compensators 84, 86, 88 and 90. The temperature sensor 82 includes a temperature-dependent element such as a thermistor or a varistor, and is a circuit or an element that detects an ambient temperature and changes an electrical characteristic according to the temperature. The temperature sensor 82 is connected to the temperature compensators 84, 86, 88, 90.

Each of the temperature compensators 84, 86, 88, and 90 is a compensation circuit in which circuit characteristics, for example, a resistance value and a degree of attenuation change in response to the temperature sensor 82. The temperature dependence of the temperature sensor 82 and the temperature compensators 84, 86, 88, 90 should be such that when the signal to be compensated has a positive temperature dependence, it has a negative temperature dependence and should be compensated. When the signal has a negative temperature dependency, the signal has a positive temperature dependency.
For more complete compensation, the temperature coefficient should have a non-linearity that is complementary to the input and output to be compensated in the normal operating temperature range. The temperature sensor 82 may be a passive circuit having a predetermined temperature-dependent resistance characteristic or impedance characteristic, or may be an active circuit having a predetermined temperature-dependent output voltage characteristic or output voltage characteristic.

The temperature compensator 84 may be inserted into a connection line _Sref between the output terminal of the reference voltage circuit 30 and the reference input terminal of the voltage comparator 24. The temperature compensator 84 compensates for a change in the reference voltage _Vref , which is the output of the reference voltage circuit 30, due to the temperature based on the temperature sensor 82, and outputs the result to the voltage comparator 24. Therefore, the temperature dependency of the reference voltage circuit 30, for example, the breakdown voltage of the semiconductor junction in the internal reference voltage section (not shown) or the temperature dependency of the output control element is compensated, and the temperature dependency is not affected by the ambient temperature. , More accurate measurement can be expected.

The temperature compensator 86 is preferably inserted into the connection line S _det between the output terminal of the detector 22 and the input terminal of the voltage comparator 24. The temperature compensator 86 compensates for a change in the output of the detector 22 due to the temperature based on the temperature sensor 82, and
Output to 24. For this reason, the temperature dependency of the detector, for example, the temperature dependency of the junction surface when using a semiconductor detecting element is compensated, and more accurate measurement can be expected regardless of the surrounding temperature.

[0070] Temperature compensator 88, after the output terminal of the voltage comparator 24, may be inserted before the branching portion of the signal line S _g. Further, the temperature compensator 90 is provided after the output terminal of the voltage comparator 24,
It may be inserted after the bifurcation of the signal line S _g. Temperature compensator 88
And 90, based on the temperature sensor 82, compensate for a change in the output of the voltage comparator 24 due to temperature and output the result to the voltage comparator 24. Temperature compensator 88, in combination with this compensating control signal S _g. For this reason, the temperature dependency of the detector, for example, the temperature dependency of the junction surface when using a semiconductor detecting element is compensated, and more accurate measurement can be expected regardless of the surrounding temperature.

Referring to FIG. 17, the aforementioned power detection circuit 10
May be combined to form the power detection device 100. The power detection device 100 includes a distributor 102 and a high power detection unit.
104, a low power detection unit 106 and a switch 108.

The distributor 102 is a circuit that has one input terminal 110 and two output terminals, divides an input signal equally, and outputs it to two output terminals. One output terminal of the distributor 102 is connected to an input terminal of the high power detection unit 104 by a connection line 112, and the other output terminal is connected to a connection line 114.
Is connected to the input terminal of the low power detection unit 106.

The high power detection section 104 includes the power detection circuit 10. Connection line 112 via input terminal of high power detection unit 104
Is connected to the input terminal 12 of the power detection circuit 10, and the output terminal 16 of the power detection circuit 10 is connected to the input terminal of the switch 108 via the output terminal of the high power detection unit 104 via the connection line 104. I have.

The low power detection section 106 includes the amplifier 72 and the power detection circuit 10. The connection line 116 via the input terminal of the low power detection unit 106 is connected to the input terminal of the amplifier 72. The output terminal of the amplifier 72 is the input terminal of the power detection circuit 10.
Connected to 12. The output terminal 16 of the power detection circuit 10
The connection line 118 is connected to the input terminal of the switch 108 via the output terminal of the low power detection unit 106.

The switch 108 is a switching circuit having two inputs and one output and switching between two inputs. Referring to FIG. 18, reference numeral 120 shown in the graph indicates the output of the low power detection unit 106,
Reference numeral 122 indicates the output of the high power detection unit 100, and dashed line 124 indicates the threshold value of the switch 108. As shown in the graph, when the detected power value is, for example, equal to or less than the threshold value of -20 [dBm], the low power detection unit 10
The output 120 of FIG. 6 is selected and switched, and when the output is also -20 [dBm] or more, the output 122 of the high power detection unit 104 is selected and switched. Therefore, even if the variation measured power P _in is large, it is possible to select the best ones output of the high power detector 104 or the low-power detection unit 106, while having a high detection accuracy, wider detection A range of power can be obtained.

Referring to FIG. 19, the power detection device may further include a plurality of low power detection units. Low power detector
Although only 104 and 132 are shown, a lower power detector may be further provided. The high power detection unit 104, the low power detection unit 106,
..., 132, may may the configuration of the above, the range of measurable measured power P _in is continuous and so that wide, constituting the measurable range of the power detector.

[0077]

As described above, according to the present invention, since the high-frequency power of the signal input to the detector is always controlled to have a predetermined power value, the detector generated by the magnitude of the power of the input signal is controlled. Can be suppressed, and accurate output of the power value can be expected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an outline of an embodiment of a power detection circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration example of a level adjuster in the embodiment shown in FIG.

FIG. 3 is an input / output characteristic diagram of a detector showing an output voltage with respect to input power in the detector in a semilogarithmic graph.

FIG. 4 is an input / output characteristic diagram showing an output voltage with respect to input power in a detector in a log-logarithmic graph.

FIG. 5 is an input / output characteristic diagram showing an output voltage with respect to input power in a root-mean-square-DC converter in a log-logarithmic graph.

FIG. 6 is an input / output characteristic diagram showing a signal strength display value with respect to input power in a power detection circuit according to the present invention in a log-log graph.

FIG. 7 is a block diagram showing an outline of power detection by a conventional power detection circuit.

FIG. 8 is an input / output characteristic diagram showing a signal strength display value with respect to input power and an error thereof in a logarithmic graph in a power detection circuit using a diode according to a conventional technique in a detection circuit.

FIG. 9 is an input / output characteristic diagram showing a signal intensity display value with respect to input power and an error thereof in a logarithmic graph in a power detection circuit using a logarithmic amplifier according to a conventional technique in a detection circuit.

FIG. 10 is an input / output characteristic diagram showing a signal strength display value with respect to input power and a log-logarithmic graph of an error in the power detection circuit using a root-mean-square-DC converter according to a conventional technique in a detection circuit.

FIG. 11 is a block diagram showing another embodiment of the power detection circuit according to the present invention.

FIG. 12 is a block diagram showing another embodiment of the power detection circuit according to the present invention.

FIG. 13 is a block diagram showing a modification of the power detection circuit according to the present invention.

FIG. 14 is a block diagram illustrating a configuration example of a voltage comparator including a logic circuit applied to the power detection circuit of the present invention.

FIG. 15 is a block diagram showing an outline of an embodiment of a power detection circuit according to the present invention to which a plurality of level adjusters are applied.

FIG. 16 is a block diagram showing an outline of an embodiment of a power detection circuit according to the present invention to which a temperature compensator is applied.

FIG. 17 is a block diagram illustrating a configuration example of a power detection device according to the present invention.

FIG. 18 is an operation characteristic diagram showing a graph of an operation example of the switch in the power detection device according to the present invention.

FIG. 19 is a block diagram illustrating a modified example of the power detection device according to the present invention to which a plurality of low power detection units are applied.

[Explanation of symbols]

 10, 50, 70 Power detection circuit 12 External input terminal 14 Reference input terminal 16 External output terminal 18 Signal source 20, 20A, 20B Level adjuster 22 Detector 24, 24A Voltage comparator 30 Reference voltage circuit 32 Output section 40 Voltage switching Sensor 42 Voltage regulator 82 Temperature sensor 84, 86, 88, 90 Temperature compensator 100, 130 Power detection device

Claims (15)

[Claims] 1. A power detection circuit for receiving a signal under measurement including a high-frequency component and outputting a detection signal indicating a high-frequency power value of the signal under measurement, wherein the circuit detects the signal based on a supplied control signal. Level adjusting means for adjusting the level of the measurement signal and outputting it as an adjusted signal; detecting means for detecting the adjusted signal and outputting a detection voltage; receiving a predetermined reference voltage, and detecting the detection signal with respect to the reference voltage Voltage comparison means for outputting a comparison signal representing a voltage potential difference as the detection signal; and feedback means for supplying the comparison signal as the control signal to the level adjustment means, wherein the reference voltage is detected by the detection means. A voltage having a detection voltage value when the error is within a predetermined range, whereby the power of the adjusted signal is set to a range where the detection means has a predetermined linearity. A power detection circuit that adjusts the reference detection power value. 2. The power detection circuit according to claim 1, further comprising a reference voltage means for supplying said reference voltage to said comparison means. 3. The power detection circuit according to claim 1, further comprising reference voltage switching means capable of increasing or decreasing the voltage of an input signal and outputting the same, and wherein said reference voltage switching means controls said voltage. A power detection circuit, wherein a voltage level of a reference voltage is switchable. 4. The power detection circuit according to claim 1, further comprising a reference voltage adjustment unit capable of adjusting a voltage of an input signal in a stepless manner and outputting the adjusted signal, and further comprising a reference voltage adjustment unit. A power detection circuit, wherein a voltage level of the reference voltage is adjustable. 5. The power detection circuit according to claim 1, wherein the comparison signal is a signal in which the high-frequency power value is expressed in a voltage state. 6. The power detection circuit according to claim 1, wherein said level adjustment means includes a variable attenuator capable of attenuating the power level of said signal under measurement in a stepless manner. 7. The power detection circuit according to claim 1, wherein the level adjustment means includes an amplification means capable of power-amplifying the signal under measurement. 8. The power detection circuit according to claim 1, wherein said detection means includes a diode detector. 9. The power detection circuit according to claim 1, wherein said detection means includes a logarithmic amplifier as a detection element. 10. The power detection circuit according to claim 1, wherein said detection means includes a root-mean-square (DC) converter. 11. The power detection circuit according to claim 1, wherein the voltage comparison means includes an operational amplifier that outputs a voltage proportional to a difference between the detection voltage and the reference voltage. . 12. The power detection circuit according to claim 1, wherein the voltage comparison means includes: an analog-digital conversion means for converting the value of the detection voltage into a digital code; A power detection circuit, comprising: comparison operation means for calculating and outputting a potential difference with respect to the reference voltage; and digital-to-analog conversion means for outputting the comparison signal based on an output of the comparison operation means. 13. The power detection circuit according to claim 12, wherein said voltage comparison means is constituted by an integrated circuit capable of storing and executing a processing program. 14. The power detection circuit according to claim 1, wherein the circuit further comprises a temperature detection means for detecting a temperature in the circuit, and an output from the detection means based on the temperature detection means. A first temperature compensating circuit for supplying the voltage comparing means, a second temperature compensating circuit for compensating the output from the voltage comparing means based on the temperature detecting means and supplying the output to the level adjusting means; A third temperature compensating circuit for compensating an output from the voltage comparing means and supplying it to the outside of the power detecting circuit and to the level adjusting means, and compensating for an output from the voltage comparing means based on the temperature detecting means, and A power detection circuit, comprising: at least one of a fourth temperature compensation circuit supplied to the outside of the detection circuit. 15. A power detection apparatus for receiving a signal under measurement including a high-frequency component and outputting a detection signal representing a high-frequency power value of the signal under measurement. And means for receiving an output from said distributing means.
Power detection circuit, comprising: at least two power detection circuits according to any one of the above, and switching means for switching an output from the power detection circuit in accordance with the power of the signal under measurement and outputting the detected signal. apparatus.