JP2001345824A - Tag-converting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a tag converting device, with which the loss of cells does not occur, when switching from an active system to a reserve system. SOLUTION: A first packet synthesizing means 1 and a second packet synthesizing means 2 generate first and second packets by synthesizing inputted cells. When switching of the active system and the reserve system is requested, a selection information generating means 3 generates selection information showing which of first and second packets is to be selected. A first packet disassembling means 4 and a second packet disassembling means 5 generate the first and second cells by disassembling the first and second packets. A first cell storage means 6 and a second cell storage means 7 store the first and second cells separately for each class of these cells. A first cell read means 8 and a second cell read means 9 successively read out the first and second cells stored in the first and second cell storage means for each class, and when the selection information is generated by the selection information generating means 3, the timing for reading out the cells is controlled according to the control of a timing control means 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tag conversion apparatus, and more particularly to a method for generating a packet by synthesizing an input cell, converting a tag of the generated packet as necessary, and then reassembling the packet into cells. The present invention relates to a tag conversion device for outputting data.

[0002]

2. Description of the Related Art For example, a LAN (Local Area Network)
In recent years, in the backbone of networks such as the Internet, there has been a growing demand for higher communication speeds.
ATM-LAN using a TM (Asynchronous Transfer Mode) switch has been spotlighted.

In an ATM-LAN, a virtual channel (V
C: Virtual Channel) is set for communication. Here, a virtual channel transfers (through cuts) data without executing a process that causes a transmission delay such as checking a destination address of data as performed by a router. High-speed transmission becomes possible.

[0004]

SUMMARY OF THE INVENTION Such an ATM-L
In the AN, a packet transmitted on a LAN is decomposed into cells having a short data length and transmitted. Therefore, at the time of routing, the cells are combined into a packet, and after the routing process, the tag exchange device is decomposed again and converted into a cell. Must be used.

[0005] By the way, ATM exchanges are sometimes duplicated in order to improve the reliability of the system. However, conventionally, the tag exchange device was not designed in such a case, so that system switching was performed. Is performed, there is a problem that packet loss and cell order inversion in the same connection may occur.

[0006] Further, when connection merge is performed in which the input-output relationship is a plural-to-single relationship, cells having different transmission destinations coexist, and the system switching operation may not operate reliably. There was a problem.

The present invention has been made in view of the above points, and has as its object to provide a tag conversion apparatus which does not cause cell loss or order reversal even when system switching is performed. .

Another object of the present invention is to provide a tag conversion device which operates reliably even when the system is switched while the connection merge is being performed.

[0009]

According to the present invention, in order to solve the above-mentioned problem, a packet is generated by combining input cells as shown in FIG. 1, and a tag of the generated packet is converted as necessary. After that, in a tag conversion device that decomposes the input cells again and outputs the cells, a first packet synthesizing unit 1 that synthesizes the input cells to generate the first packet, and a second packet that synthesizes the input cells and A second packet combining means 2 for generating the first packet and a selection information indicating which of the first and second packets is to be selected when switching between the active system and the standby system is requested. Selection information generating means 3, first packet decomposing means 4 for decomposing the first packet to generate a first cell, and second packet decomposing means 4 for decomposing the second packet to generate a second cell Packet decomposing means 5 and the first First and cell storage unit 6, a second cell storing means for storing separately the second cell for each type of the cell to separate storage cell for each type of the cells 7
A first cell reading means 8 for sequentially reading and outputting the first cells stored in the first cell storage means 6 for each type, and a first cell reading means 8 stored in the second cell storage means 7. A second cell reading means 9 for sequentially reading and outputting the second cells present for each type, and when the selection information is generated by the selection information generating means 3, the first cell reading means 9
And a timing adjusting means 10 for adjusting the read timing of the second cell reading means 8 and 9.

[0010] Here, the first packet combining means 1 combines the input cells to generate a first packet. The second packet combining means 2 combines the input cells to generate a second packet. The selection information generation means 3 generates selection information indicating which of the first and second packets is to be selected when switching between the active system and the standby system is requested. The first packet decomposer 4 decomposes the first packet to generate a first cell. The second packet decomposing means 5 decomposes the second packet to generate a second cell. The first cell storage means 6 stores the first cell separately for each cell type. Second cell storage means 7
Stores the second cell separately for each cell type.
The first cell reading means 8 sequentially reads and outputs the first cells stored in the first cell storage means 6 for each type. The second cell reading means 9 sequentially reads and outputs the second cells stored in the second cell storage means 7 for each type. The timing adjusting means 10
When the selection information is generated by the selection information generation means 3, the read timing of the first and second cell reading means 8, 9 is adjusted.

[0011] Further, in a tag conversion device for generating a packet by synthesizing input cells, converting the tags of the generated packets as necessary, reassembling the cells into cells and outputting the cells, A first packet combining means for combining the input cells to generate a first packet, a second packet combining means for combining input cells to generate a second packet, and switching between the active system and the standby system. When requested, selection information generating means for generating selection information indicating which one of the first and second packets to select, and storing the first packets separately for each packet type A first packet storage unit, a second packet storage unit for storing the second packet separately for each packet type, and a first packet stored in the first packet storage unit. First packet reading means for sequentially reading each type, second packet reading means for sequentially reading the second packets stored in the second packet storage means for each type, and selection by the information selection means. When the information is generated, a timing adjusting means for adjusting the read timing of the first and second packet reading means, and a second means for decomposing the first packet to generate and output a first cell. A tag conversion device comprising: one packet decomposing means; and a second packet decomposing means for decomposing the second packet to generate and output a second cell.

[0012] Here, the first packet combining means combines the input cells to generate a first packet. Second
Packet combining means synthesizes the input cells and
Generate a packet. The selection information generating means generates selection information indicating which of the first and second packets is to be selected when switching between the active system and the standby system is requested. The first packet storage means stores the first packet separately for each packet type. The second packet storage means stores the second packet separately for each type of the packet. The first packet reading means includes:
The first packets stored in the packet storage means are sequentially read out for each type. The second packet reading means sequentially reads the second packets stored in the second packet storage means for each type. The timing adjusting means adjusts the read timing of the first and second packet reading means when the selection information is generated by the information selecting means. The first packet decomposing means is
The first packet is disassembled to generate and output a first cell. The second packet decomposer decomposes the second packet to generate and output a second cell.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a principle diagram for explaining the operation principle of the present invention. In this figure, a first packet combining means 1 combines input cells to generate a first packet.

The second packet combining means 2 combines input cells to generate a second packet. When switching between the active system and the standby system is requested, the selection information generating unit 3 generates selection information indicating which of the first and second packets is to be selected, and the first packet combining unit 1 Then, the generated selection information is supplied to the second packet combining means 2.

The first packet decomposing means 4 decomposes the first packet output from the first packet synthesizing means 1 to generate a first cell. Second packet decomposing means 5
Decomposes the second packet output from the second packet combining means 2 to generate a second cell.

The first cell storing means 6 stores the first cells supplied from the first packet decomposing means 4 for each type. The second cell storage means 7 stores the second cells supplied from the second packet decomposing means 5 for each type.

The first cell reading means 8 sequentially reads out and outputs the first cells stored in the first cell storage means 6 for each type. Second cell reading means 9
Sequentially reads and outputs the second cells stored in the second cell storage means 7 for each type.

When the selection information is generated by the selection information generating means 3, the timing adjusting means 10 adjusts the read timing of the first cell reading means 8 and the second cell reading means 9.

In the following, the first packet combining means 1, the first packet decomposing means 4, the first cell storing means 6, and the first cell reading means 8 are referred to as system 0,
Further, the second packet combining means 2, the second packet decomposing means 5, the second cell storing means 7, and the second cell reading means 9 are referred to as a first system.

Next, the operation of the above principle diagram will be described. Now, for example, there are three types of packets, A, B, and C, each having the same IP address, and the cells constituting these packets are denoted as a1, a2, a3, b1, b2, b3, and c1, c2, c3. And And the first or second
C1, a1, b
Assume that cells are input in the order of 1, c2, b2, a2, a3, c3, and b3, and a request is made to switch from system 0 to system 1 in cell b1. It should be noted that when system switching is requested, predetermined bits added to the header of each cell change. Therefore, in the present example, b1
The bit changes in the subsequent cells.

The first packet synthesizing means 1 and the second packet synthesizing means 2 synthesize cells by referring to the header added to the input cells and packetize the cells. In the present example, the combined packets are output in the order of A, C, and B.

At this time, the selection information generating means 3 generates and adds the selection information for the packet by referring to the above-mentioned bit of the first cell constituting the packet. For example, in the present example, a request is made in the cell b1, which is the first cell of the packet B, so that information for selecting the system 1 is added to the packet B.

The first packet decomposing means 4 and the second packet decomposing means 5 receive the first and second packets, respectively, and decompose them into cells. At this time, if the selection information is added to the packet, the selection information is passed on to each cell after the decomposition. In the present example, the cells b1 and b output from the second packet
Selection information is added to 2 and b3.

The first cell storage means 6 and the second cell storage means 7 store the first and second cells output from the first packet decomposition means 4 and the third packet decomposition means 5 in their types. (E.g., the VC of the packet) and sequentially store them in separate areas. In the present example, a1, a
2, a3, b1, b2, b3 and c1, c2, c
3 are stored in different areas in this order.

The first cell reading means 8 and the second cell reading means 9 are composed of the first cell storing means 6 and the second cell reading means 9.
The cells stored in the cell storage means 7 for each type are sequentially read and output. At this time, if the state of addition of the selection information changes in comparison with the immediately preceding cell, the timing adjustment unit 10 suspends reading from the cell and suspends reading of the cell of another type and adds the selection information. The priority is given to the reading of cells whose status has not changed.

In the present example, first, cells a1, a2, a
3 is read out, and next, when the cell b1 is read, the selection information of the cell b1 is changed (added).
Therefore, the cells c1, c2, and c3 are read out with priority.

When the selection information has changed, the timing adjusting means 10 starts outputting the changed cell after a lapse of a predetermined time from the end of the output of the cell before the change. Therefore, in the present example, cells b1, b2, b3 are:
It is read out and output after a certain time has elapsed. As a result, even if the processing speeds of the system 0 and the system 1 do not match, it is possible to prevent cell loss.
That is, when the cells b1, b2, and b3 are read out without waiting for a certain time, and when the output of the cell of the system 1 is advanced from the system 0, the cell near the head immediately after the switching (for example, the cell Since it is assumed that b1) has already been output, such a situation can be avoided.

Next, an embodiment of the present invention will be described. FIG. 2 is a diagram showing an outline of an entire network system including the tag conversion device of the present invention. In this figure, terminal devices 20-1 to 20-3 and terminal device 21-
1 to 21-3 are configured by, for example, a personal computer or the like, and exchange information according to each user's operation.

The switches 22 and 23 are connected to the terminal device 20-1.
20-3 and 21-1 to 21-3 are grouped so that information can be exchanged between terminal devices belonging to the group. The switches 22 and 23 are
ATM converted from cells transmitted from each terminal device into cells
In addition to supplying the packet to the switch 24, the cell supplied from the ATM switch 24 is combined into a packet and supplied to the corresponding terminal device.

The ATM switch 24 includes switches 22 and 2
A process of selecting a corresponding switch with reference to the header added to the cell supplied from No. 3 is performed. It is assumed that the ATM switch 24 is duplicated to ensure reliability.

The tag conversion device 25 includes an ATM switch 24
Generates a packet by synthesizing the received cells, converts the tag of the obtained packet as necessary, and then converts the packet into a cell again and outputs it.

Next, referring to FIG.
A detailed configuration example will be described. FIG. 3 is a diagram illustrating a detailed configuration example of the tag conversion device 25. As shown in this figure, the tag conversion device 25 includes conversion units 40 and 41, and
The control unit 42 is configured. Switch 4
Reference numerals 3 and 44 are arranged on the ATM switch 24 side.
Since the conversion units 40 and 41 and the switches 43 and 44 have the same configuration, only the conversion unit 40 and the switch 43 will be described as an example.

The conversion unit 40 includes a selector 40a, an ACT adding unit 40b, a packetizing unit 40c, and an ACT adding unit 40.
d, a packet buffer 40e, an IP switch 40f, a cell unit 40g, an ACT adding unit 40h, and a cell buffer 40i.

Here, the selector 40a includes a switch 43
Alternatively, one of the cells supplied from the switch 44 is selected and input. The ACT adding unit 40b sets the ACT bit of the cell to “1” when the cell is the active system, and sets the ACT bit of the cell to “0” when the cell is the standby system.

The packetizing section 40c includes an ACT adding section 40
b) to generate a packet by combining the cells output from b.
The ACT adding unit 40d obtains the ACT bit of a predetermined cell constituting the packet, and obtains the AC bit of the packet itself.
It is added as a T bit.

The packet buffer 40e stores the packet to which the ACT bit has been added. IP switch 40f
Executes an IP switching process and a packet protocol conversion process.

The celling section 40g decomposes the packet supplied from the IP switch 40f to generate a cell. AC
The T adding unit 40h adds the ACT bit added to the packet to each cell included in the packet.

The cell buffer 40i includes an ACT adding unit 40
The cells input from h are stored separately for each cell type, read out in a certain order, and output. Switch 43
Is constituted by a selector 43a,
The cell output from any one of 0 and 41 is selected and output.

The control section 42 controls each section of the conversion sections 40 and 41. Next, the operation of the above embodiment will be described. In the following, description will be given while mainly supplementing the operation of the system 1 with the operation of the system 0 as the center.

The selector 40a selects a cell input from either the switch 43 or the switch 44 and supplies it to the ACT adding unit 40b. ACT adding unit 40b
Sets the ACT bit of the input cell under the control of the control unit 42. The ACT adding unit 40b and the ACT
The adding unit 41b adds conflicting ACT bits. That is, when one sets the ACT bit to "1", the other sets the ACT bit to "0".

For example, the cells Aa1, Aa2, Ba1,... Shown in FIGS.
b and the ACT adding unit 41b, respectively, and if the active system is switched from the converting unit 40 to the converting unit 41 in the cell Bb1, the ACT adding unit 40b sets the ACT bits of the cells Aa1 to Ab4 to "1". And
Subsequent cells are set to the state of “0”. AC
The T adding unit 41b sets the ACT bits of the cells Aa1 to Ab4 to “0”, and sets the subsequent cells to “1”. Here, the cell in which the ACT bit is “1” is surrounded by an ellipse, and the ACT bit is “0”.
Are surrounded by a rectangle. Further, the type of packet is determined by the IP address added to the packet.

The packetizer 40c combines the input cell with the packet by referring to the header. In the example of FIG. 4, the packet A is synthesized from the cells Aa1, Aa2, and Aa3, and the packet B is synthesized from the packets Ba1 and Ba2.

The ACT adding section 40d acquires an ACT bit added to a predetermined cell (for example, a head or end cell) constituting the combined packet and adds it as an ACT bit of the packet itself. Since different ACT bits are added to the same cell in conversion sections 40 and 41, different ACT bits are similarly added to the same packet.

The packet buffer 40e stores the packet to which the ACT bit is added, and reads out and supplies the packet at a predetermined timing in response to a request from the IP switch 40f.

In the packetizer 40c, for example,
Since the first cell performs the combining process from the packet that has arrived first, the packets stored in the packet buffer 40e are those whose ACT bit is “1” and “0” as shown in FIG. Some things are mixed.

The IP switch 40f executes an IP switching process and a packet protocol conversion process, and supplies the result to the cell unit 40g. The celling unit 40g decomposes the packet into cells again. That is, as shown in FIG. 4A, for example, the packet Aa is decomposed into cells Aa1, Aa2, and Aa3.

The ACT adding section 40h acquires the ACT bit added in packet units, and adds it to each cell constituting the packet. As a result, the ACT bits of all the cells constituting the packet whose ACT bit is "1" are set to "1".

The cell buffer 40i classifies input cells according to their types and stores the cells in the corresponding areas. For example, as shown in FIG. 5, the input cell is VC (Virtua
l Channel) and stored in different areas. Here, when the connection merge is not performed, since the IP address added to the packet and the VC match, the cells stored in the respective areas of the cell buffer 40i are the same as those of the packet having the same IP address. It is a generated cell.

The cells stored for each VC in this manner are read out and output in a fixed order. For example, in the example of FIG. 5, VC is a cell related to A (cells Aa1, Aa2).
) Is read first, and then the cells (cells Bb1, Bb2, etc.) related to VC B are read. Here, when the state of the ACT bit of the cell to be read has changed compared to the state of the cell immediately before it, reading of the cell is stopped and the cell related to the next VC is read. That is,
In the example of FIG. 5, since the ACT bit of the cell Ac1 next to the cell Aa6 has changed, the reading of that cell is stopped, and the cell Ba1 whose VC is B is read.

When all the cells before the ACT bit changes are read, the reading is stopped. Then, the cell buffer that has stopped reading notifies the control unit 42 of that fact. The control unit 42 controls the cell buffer 40i
If a predetermined time has passed since the notification of the read stop of both the cell buffers 41i and 41i, the cell reading is started simultaneously in both the cell buffers 40i and 41i.

It should be noted that after a certain period of time (time when reading of the cell buffer 40i and the cell buffer 41i is expected to be completed) has elapsed since the request for switching the active system is made, cell reading is restarted. You may.

Cell buffer 40i and cell buffer 4
1i is output to A by the selector 43a.
Only those for which the CT bit is "1" are selected and output.

FIG. 6 is a diagram showing an example of the operation of the selector 43a. As shown in this figure, the selector 43a
Among the cells input from the cell buffer 40i and the cell buffer 41i, the cell whose ACT bit is "1" is selected and output.

According to the above embodiment, the ACT adding section 40d performs ACT of a predetermined cell constituting a packet.
Since the bits are taken over as the ACT bits of the entire packet, the information added to the packet can be uniquely and easily determined.

Further, when reading out cells in the cell buffers 40i and 41i, after reading out all the cells before the ACT bit changes, the changed cells are read out after a certain time has passed. Thus, cell loss can be prevented. This situation is shown in FIG.
It will be described in detail with reference to FIG. As shown in FIGS. 7A and 7B,
When the switching of the ACT bit occurs, the cell buffer 4
All the cells before the ACT bit stored in 0i and 41i are changed are ejected, and the cell after the ACT bit is changed after a predetermined time has elapsed is read out. The switches 43 and 44 are, as shown in FIG.
Before the ACT bit changes, the cell from the old working system is selected, and after the discharge of the buffer is completed, both systems are deselected. When the output of a new cell is started, the new working system is switched to the new working system. Will choose.

In the above embodiment, the cell buffer 40i and the cell buffer 41i have the A
Although the discharging process is performed according to the change of the CT bit, the same process can be performed in the packet buffers 40e and 41e. The operation in such a case will be described with reference to FIGS.

The cell input from the selector 40a is A
The ACT bit is added in the CT adding unit 40b, and is supplied to the packetizing unit 40c. Packetizer 40c
Synthesizes a packet with reference to the header added to the cell.

The ACT adding unit 40 d
The ACT bit of a predetermined cell constituting the packet is obtained from the packet supplied from c, and this is added as the ACT bit of the packet itself.

The packet buffer 40e stores the packet
Classify for each C or PDP and store in the corresponding area.
FIG. 8 is a diagram illustrating an example of a packet stored in the packet buffer 40e. In the example of this figure, the packet is
Classified according to VC and stored.

The packets stored in the packet buffer 40e are read for each VC. If the ACT bit of the packet changes during the reading, the reading of the packet related to the VC is stopped and the reading of the packet related to the next VC is performed. And ACT
When the reading of all the packets before the bit change is completed in both the packet buffers 40e and 41e, the reading is stopped for a predetermined time τ, and then the reading of the next packet (the packet whose ACT bit is changed) is started. Resume reading.

In the example of FIG. 8, the reading of the packet AC is started after a predetermined time τ has elapsed since the reading of the packet Ba from the packet buffer 40e.
The time τ is determined in consideration of a delay expected to occur in processing after the IP switch 40f.
For example, when the delay occurring after the IP switch 40f is d, τ is set so that τ> d. By setting in this way, even if a subsequent process causes a delay of a cell (or a packet), it is possible to prevent a cell loss from occurring.

The IP switch 40f executes an IP switching process and a packet protocol conversion process, and outputs the processed packet. The cell-forming unit 40g includes:
The packet output from the IP switch 40f is decomposed to generate a cell. This is shown in FIG. That is, the packet input to the cell forming unit 40g is decomposed into cells constituting the packet and output.

The ACT adding unit 40h is configured to perform ACT on the packet.
The bit is obtained and added to each cell constituting the packet. The cell buffer 40i includes an ACT adding unit 40
h after the cells output from the switch 43 are stored once.
And 44.

The selector 43a of the switch 43 is the same as that shown in FIG.
As shown in (1), of the cells supplied from the conversion units 40 and 41, the one whose ACT bit is in the state of “1” is selected and output.

According to the above embodiment, similarly to the above-described case, the ACT adding section 40d takes over the ACT bits of the predetermined cells constituting the packet as the ACT bits of the entire packet. It is possible to uniquely and easily determine the information to be performed.

In the packet buffer 40e,
Read control is performed for each VC or packet queue, and after reading all the cells before the ACT bit has changed, the cells after the change have been read after a certain period of time, so that cell loss is prevented. Becomes possible.

Further, in the case where a so-called connection merge is performed in which the relationship between input and output to the device is plural-to-single, the same VC is assigned to packets to which different IP addresses are assigned. Become. In that case,
In the above-described embodiment, a cell whose ACT bit is “1” in the connection queue of the cell buffer and an ACT
In some cases, cells whose bits are "0" are alternately arranged. However, in the case of the above-described embodiment, such a situation can be avoided because the ejection process is performed by the ACT bit at the packet level.

Next, another embodiment of the present invention will be described. FIG. 11 is a diagram showing another configuration example of the system including the tag conversion device of the present invention. In this figure, FIG.
The same reference numerals are given to the portions corresponding to the case of the above, and the description thereof will be omitted.

In this embodiment, the locations where the tag converters 30 and 31 are inserted are different from those in FIG. Other configurations are the same as those in FIG.
FIG. 12 is a diagram showing a detailed configuration example of the tag conversion devices 30 and 31 shown in FIG. As shown in this figure, the tag conversion device includes conversion units 50 and 51, a control unit 52, a switch 5
3, 55. Switches 54, 56
Are included in the ATM switch 24 side.

Since the conversion unit 50 and the conversion unit 51 and the switches 53 and 54 and the switches 55 and 56 have the same configuration, the conversion unit 50 and the switch 5 will be described below.
3, 54 will be described as an example.

The conversion section 50 is composed of sections for uplink and downlink, and the section for uplink is composed of a selector 50a, an ACT addition section 50b, and a packetization section 50.
c, ACT adding unit 50d, packet buffer 50e, I
P switch 50f, celling unit 50g, ACT adding unit 50
h, and a cell buffer 50i. On the other hand, the portion for the downlink is provided by a selector 50j, AC
T adding section 50k, packetizing section 50m, ACT adding section 5
0n, packet buffer 50o, IP switch 50p,
It is composed of a cell unit 50q, an ACT adding unit 50r, and a cell buffer 50s. In addition, the configuration for the uplink and the downlink are the same, and the operation of each part is basically the same as the case of FIG. 3, so only the operation of the uplink part will be described below. Will be described briefly.

The selector 50a selects and outputs one of the uplink cells supplied via the switch 53 or the switch 55. The ACT adding unit 50b sets the ACT bit of the input cell under the control of the control unit 52. The ACT adding unit 50b and the ACT adding unit 51b
Sets the ACT bits so that they have opposite values.

The packetizer 50c generates a packet by combining cells with the ACT bit set. The ACT adding unit 50d acquires the ACT bit of a predetermined cell (for example, the first cell) constituting the packet, and sets this as the ACT bit of the packet itself.

After the packet buffer 50e temporarily stores the packet supplied from the ACT adding unit 50d,
Output. The IP switch 50f performs an IP switching process and a packet protocol conversion process on the packet.

The celling unit 50g decomposes the packet output from the IP switch 50f into cells. The ACT adding unit 50h acquires the ACT bit added to the packet and adds the ACT bit to each of the cells constituting the packet.

As shown in FIG. 5, the cell buffer 50i classifies cells for each VC, stores the cells in the corresponding areas, and sequentially reads and outputs the cells for each VC.
The selector 54a of the switch 54 includes a cell buffer 50i.
Alternatively, a cell output from one of the cell buffers 51i is selected and output.

The operation of the other parts is the same as in the above-described case, and the input cells are packetized, subjected to switching processing, and then re-cellularized and output.

According to the above-described embodiment, it is possible to prevent cell loss even when both the uplink and the downlink are duplicated and the active system and the standby system are switched. Become.

In the above embodiment, the ACT bit indicates the system to be selected. However, for example, a signal running in parallel with a cell or a packet is provided, and the signal to be selected is indicated by this signal. It may be.

Further, in the above-described embodiment, the IP packet has been described as an example, but this is merely an example, and it is needless to say that the present invention is not limited to only such a case.

Further, in the above embodiment, the ATM switch and the tag converter are configured differently. However, the embodiment can be implemented by adding an ATM switch to the tag converter.

[0082]

As described above, according to the present invention, a packet is generated by synthesizing input cells, the tag of the generated packet is converted as necessary, and the packet is again decomposed and output. In the tag translator, first packet combining means for combining input cells to generate a first packet, and second packet combining means for combining input cells to generate a second packet. When switching between the active system and the standby system is requested, selection information generating means for generating selection information indicating which of the first and second packets is to be selected; A first packet decomposing means for generating a first cell, a second packet decomposing means for decomposing a second packet to generate a second cell, and dividing the first cell for each cell type First cell storage means for storing A second cell storage means for storing the second cells separately for each cell type, and a second cell storage means for sequentially reading and outputting the first cells stored in the first cell storage means for each type. The first cell readout means, the second cell readout means for sequentially reading and outputting the second cells stored in the second cell storage means for each type, and the selection information generation means for generating selection information. In this case, there is provided a timing adjusting means for adjusting the read timing of the first and second cell reading means. Therefore, even when the active system and the standby system are switched, the cell loss and the order of the cells are changed. Reversal can be prevented.

In a tag conversion device that combines input cells to generate a packet, converts a tag of the generated packet as needed, and then decomposes and outputs the cells again, outputs the input cells. A first packet combining means for combining the input cells to generate a first packet, a second packet combining means for combining input cells to generate a second packet, and switching between the active system and the standby system. When requested, selection information generating means for generating selection information indicating which of the first and second packets is to be selected, and a first information for storing the first packet separately for each packet type Packet storage means, a second packet storage means for storing the second packet separately for each packet type, and a first packet storage means.
A first packet reading means for sequentially reading the first packets stored in the packet storage means for each type, and a second packet for sequentially reading the second packets stored in the second packet storage means for each type A second packet reading unit, a timing adjusting unit for adjusting read timings of the first and second packet reading units when the selection information is generated by the information selecting unit, and disassembling the first packet. The first packet decomposing means for generating and outputting the first cell and the second packet decomposing means for generating and outputting the second cell by decomposing the second packet are provided. In the case where connection merge is performed, cell loss and order reversal can be prevented even when switching between the active system and the standby system is performed.

[Brief description of the drawings]

FIG. 1 is a principle diagram for explaining the operation principle of the present invention.

FIG. 2 is a diagram illustrating an overview of a system including a tag conversion device according to the present invention.

FIG. 3 is a block diagram illustrating a detailed configuration example of the tag conversion device illustrated in FIG. 2;

FIG. 4 is a diagram for explaining operations of a packet buffer and a cell unit shown in FIG. 3;

FIG. 5 is a diagram for explaining an operation of the cell buffer shown in FIG. 3;

FIG. 6 is a diagram for explaining the operation of the selector shown in FIG. 3;

FIG. 7 is a diagram for explaining an outline of an operation of the embodiment shown in FIG. 3;

FIG. 8 is a diagram for explaining another operation of the packet buffer and the cell unit shown in FIG. 3;

FIG. 9 is a diagram for explaining another operation of the cell buffer shown in FIG. 3;

FIG. 10 is a diagram for explaining another operation of the selector shown in FIG. 3;

FIG. 11 is a diagram illustrating an outline of another system including the tag conversion device of the present invention.

12 is a block diagram showing a detailed configuration example of the tag conversion device shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st packet combining means 2 2nd packet combining means 3 Selection information generating means 4 1st packet combining means 5 2nd packet combining means 6 1st cell storing means 7 2nd cell storing means 8 1st 9 Cell readout means 9 Second cell readout means 10 Timing adjustment means 20-1 to 20-3 Terminal device 21-1 to 21-3 Terminal device 22, 23 switch 24 ATM switch 25, 30, 31 Tag conversion device 40, 41 tag conversion unit 40a, 41a selector 40b, 41b ACT addition unit 40c, 41c packetization unit 40d, 41d ACT addition unit 40e, 41e packet buffer 40f, 41f IP switch 40g, 41g cellization unit 40h, 41h ACT addition unit 40i, 41i Cell buffer 42 Control unit 43, 44 Switch 43a, 44 Selectors 50, 51 Tag converters 50a, 51a, 50j, 51j Selectors 50b, 51b, 50k, 51k ACT adders 50c, 51c, 50m, 51m Packetizers 50d, 51d, 50n, 51n ACT adders 50e, 51e, 50o , 51o Packet buffer 50f, 51f, 50p, 51p IP switch 50g, 51g, 50q, 51q Celling unit 50h, 51h, 50r, 51r ACT adding unit 50i, 51i, 50s, 51s Cell buffer 52 Control unit 53, 54, 55 , 56 switches 53a, 54a, 55a, 56a selector

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Satoshi Matsuo 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Masaaki Shigetani 2-3-3 Otemachi, Chiyoda-ku, Tokyo No. 1 Nippon Telegraph and Telephone Corporation (72) Inventor Takeshi Chimaru 2-3-1 Otemachi, Chiyoda-ku, Tokyo F-Term within Nippon Telegraph and Telephone Corporation 5K030 HA10 HB16 HC15 JA06 KA03 LA15 LE17 MD02 5K033 AA02 CB06 DB12 EB06

Claims (10)

[Claims] 1. A tag conversion device that combines input cells to generate a packet, converts a tag of the generated packet as needed, and then decomposes and outputs the cells again. Packet combining means for combining the input cells to generate a first packet, second packet combining means for combining input cells to generate a second packet, and switching between the active system and the standby system. When requested, selection information generating means for generating selection information indicating which of the first and second packets to select, and disassembly of the first packet to generate a first cell. A first packet decomposing unit, a second packet decomposing unit that decomposes the second packet to generate a second cell, and a first unit that stores the first cell separately for each cell type. Cell storage means; A second cell storage unit for storing cells of each type separately for each cell type, and a first cell for sequentially reading and outputting the first cells stored in the first cell storage unit for each type. Cell reading means, second cell reading means for sequentially reading and outputting the second cells stored in the second cell storage means for each type, and selection information is generated by the selection information generating means. And a timing adjusting means for adjusting the read timing of the first and second cell reading means. 2. The tag conversion device according to claim 1, wherein the timing adjustment unit suspends reading for a predetermined time when the selection information is generated by the selection information generation unit. 3. When the selection information is generated by the selection information generation means, the timing adjustment means determines whether a cell before the selection information has been generated in both the first and second cell storage means. 2. The tag conversion device according to claim 1, wherein reading of cells after the selection information is generated is started after all the cells are read. 4. The cell has a bit indicating that switching between the active system and the standby system has been requested, and the selection information generating means includes one or more of the cells included in the combined packet. With reference to the bits of the cell,
Selection information indicating which one of the first and second packets to select is generated and added to the first and second packets, respectively; and the timing adjustment means is added to the first and second packets. The tag conversion device according to claim 1, wherein the read timing of the first and second cell read means is adjusted with reference to the selected selection information. 5. The cell is transmitted in parallel with information indicating that switching between the active system and the standby system has been requested, and the selection information generating unit includes a cell included in the combined packet. With reference to the signals corresponding to two or more cells, transmitted in parallel with the first and second packets,
Generating selection information indicating which one of the first and second packets is to be selected, the timing adjusting means refers to the selection information transmitted in parallel with the first and second packets, The tag conversion device according to claim 1, wherein read timings of the first and second cell read means are adjusted. 6. A tag conversion device that combines input cells to generate a packet, converts a tag of the generated packet as needed, and then decomposes and outputs the cells again. Packet combining means for combining the input cells to generate a first packet, second packet combining means for combining input cells to generate a second packet, and switching between the active system and the standby system. When requested, selection information generating means for generating selection information indicating which of the first and second packets to select, and storing the first packets separately for each packet type A first packet storage unit, a second packet storage unit that stores the second packet separately for each packet type, and a first packet stored in the first packet storage unit. First packet reading means for sequentially reading each type, second packet reading means for sequentially reading second packets stored in the second packet storage means for each type, and selection by the information selection means. When the information is generated, a timing adjusting unit that adjusts the read timing of the first and second packet reading units; and a second unit that generates the first cell by decomposing the first packet and outputs the first cell. 1. A tag conversion device comprising: a first packet decomposer; and a second packet decomposer that decomposes the second packet to generate and output a second cell. 7. The tag conversion device according to claim 6, wherein the timing adjustment unit suspends reading for a predetermined time when the selection information is generated by the selection information generation unit. 8. The timing adjusting means, when the selection information is generated by the selection information generating means, a packet before the selection information is generated in both the first and second packet storage means. 7. The tag conversion device according to claim 6, wherein after reading all the data, a predetermined time elapses, and then reading of the packet after the selection information is generated is started. 9. The cell includes a bit indicating that switching between a working system and a standby system has been requested, and the selection information generating means includes one or more of the cells included in the combined packet. With reference to the bits of the cell,
Selection information indicating which one of the first and second packets to select is generated and added to the first and second packets, respectively; and the timing adjustment means is added to the first and second packets. The tag conversion apparatus according to claim 6, wherein read timings of the first and second packet reading means are adjusted with reference to the selected selection information. 10. The cell is transmitted in parallel with information indicating that switching between a working system and a standby system has been requested, and the selection information generating means includes a cell included in the combined packet. With reference to the signals corresponding to two or more cells, transmitted in parallel with the first and second packets,
Generating selection information indicating which one of the first and second packets is to be selected, the timing adjusting means refers to the selection information transmitted in parallel with the first and second packets, The tag conversion device according to claim 6, wherein read timings of the first and second packet read units are adjusted.