JP2001344988A - Method of test for connection system of semiconductor memory, device, and picture forming device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize simply a test for correct/error of electric connection between a connector incorporating a memory module and an electric circuit connected to it or an operation function, to reduce additional elements for it, and to simplify the operation of an operator for the test. SOLUTION: At least one side of connected address lines BA, RA and connected control lines RAS, CAS,... and a data line RD out of terminal groups of the connector of memory systems 40-42 comprising a data line RD for accessing to a SDRAM incorporated in a connector 4, address lines BA, RA, control lines RAS, CAS,..., memory access ASIC40, 43 are short-circuit-connected by a loop back test board 34tb, a connection test signal is given to the address lines, control lines BA, RA, RAS, CAS,..., and a signal of the data line RD is read out.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electric circuit for reading stored data from a semiconductor memory mounted on a connector.
The present invention relates to a method and an apparatus for inspecting whether an electrical connection to a connector or an operation function is correct, and an image forming apparatus equipped with the inspection apparatus.

[0002]

2. Description of the Related Art Japanese Unexamined Patent Publication No. Hei 10-186006 discloses a conventional method for assembling a printed circuit board on which a connector for a RAM module is mounted and testing the assembled circuit after mounting all the RAM modules and performing a typical operation to determine the quality. Although the entire printed circuit board is tested by performing a function test, it discloses a conventional problem that the pass / fail judgment is easy, but the test time is long and it is difficult to specify a defective portion. And RA to improve this
Connector for mounting M module and LS connected to it
A method for testing a printed circuit board mounting I for a connection failure or short circuit of a wiring network connected to the connector is presented. In the first mode, a resistor module having a terminating resistor is mounted on a connector in place of a RAM module, and a probe is brought into contact with a terminal of the connector to energize the terminating resistor. Then, the state of the wiring network is estimated from the current / voltage characteristics. In the second mode, when a test is performed, a folded card for connecting the two terminals of the connector is attached to the connector, and the two terminals are short-circuited. One of the plurality of LSIs connected to the connector and connected to each other by this short circuit is one of a boundary scan circuit on a test transmitting side that generates a test signal, and the other is a chip that receives a test signal and checks whether the wiring is correct or not. Receiving boundary scan circuits.

[0003]

However, the development of a measuring instrument or a circuit board equipped with a boundary scan circuit in each LSI requires enormous costs. Also, the first
In the embodiment, the operation of bringing the probe into contact with the terminal of the connector may damage the conductor or the solder at the contact point, and the test time is also increased.

SUMMARY OF THE INVENTION It is a first object of the present invention to easily realize an electrical connection between a connector to which a memory module is mounted and an electrical circuit connected to the connector, or a correct / incorrect operation function. The second and third objects are to reduce and simplify the additional elements for that purpose, and the fourth object is to simplify the operation of the operator for the inspection. A fifth object is to provide an image forming apparatus to be equipped.

[0005]

Means for Solving the Problems (1) Semiconductor memory (MM)
1, MM2), a data line (RD) connected to the connector, and an address line (B) for accessing the semiconductor memory mounted on the connector.
A, RA) and control lines (RAS, CAS, ...) and memory access means (40, 43).
42), when the semiconductor memory (MM1, MM2) is attached to the connector (44, 45), the address line (BA, RA) in the connector side terminal group that contacts the terminal of the memory is connected. Electrically connecting a first set including at least one of those connected to control lines (RAS, CAS,...) And a second set including one connected to a data line (RD); A line connected to the first set of terminals by means (40, 43)
(BA, RA / BA, RA, RAS, CAS,...) To read a signal of a line (RD) connected to a second set of terminals, and read a signal of a line (RD) connected to the second set of terminals. Inspection method.

[0006] To facilitate understanding, reference numerals or corresponding items of corresponding elements in the embodiment shown in the drawings and described later are added for reference in parentheses. The same applies to the following.

In the case of a semiconductor memory device, this inspection method uses an address data line (B) for accessing the semiconductor memory device.
A, RA) and control lines (RAS, CAS, ...) and read data lines (RD), which are connected to the connectors (44, 45), and the memory access means (40 , 43)
Pays attention to the point that the address data and the control signal are transmitted to the connector (memory device) and the memory data is obtained via the connector, and the memory access means (40, 43) transmits the inspection signal in the same manner as the memory read access. Then, similarly to the reading of the memory data, the inspection signal returned by the connector is read.

Therefore, for the connectors (44, 45) for mounting the semiconductor memory and the electrical circuits (40, 43) connected to the connectors, the electrical connection to the connectors or the inspection for correctness of the operation function is performed.
It can be easily realized. Additional elements for that are:
In the main hardware, for example, it is only necessary to add a loopback inspection board (34tb / 34tbV) for short-circuiting the terminals of the first and second sets of connectors.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (2) A first board-side terminal that contacts the first and second sets of terminals in a connector-side terminal group.
The connector (Ccr / CcrV) and a means (Pcr / PcrV) for electrically connecting the board-side first set of terminals and the board-side second set of terminals to the connector (Ccr / CcrV). Inspection board (34tb / 34tbV) that can be attached to and detached from 44, 45), the connector (44, 45)
To electrically connect the first and second sets of terminals on the connector side.

According to this, a test board (34tb / 34tbV) looping back is connected to the connector instead of the semiconductor memory.
(44, 45), and the quality of the circuit connection can be determined by the memory read access from the memory access means (40, 43), and the defective portion can be easily specified. Inspection board (34tb / 34tbV)
Is a board with only loopback wiring, so power on
It is inexpensive because there is no possibility of destruction even if the connector is inserted and removed inside.

(3) Connectors (44, 45) for mounting the semiconductor memories (MM1, MM2), data lines (RD) connected to the connectors for accessing the semiconductor memories mounted on the connectors, An address line (BA, RA) and a control line (RAS, CAS,...), A CPU (51) for instructing reading of the semiconductor memory (MM1, MM2), and A semiconductor memory connection system (5) including access means (40, 43) for providing data and control signals to address lines (BA, RA) and control lines (RAS, CAS, ...).
1, 40, 42), when the semiconductor memory (MM1, MM2) is mounted on the connector (44, 45), the address lines (BA, RA) in the connector-side terminal group with which the terminals of the memory contact are connected. A first set including at least one of a connected one and a connected control line (RAS, CAS,...) And a data line (RD)
The first and second sets of terminals (Ccr) on the board, which are in contact with the second set including the ones connected, are electrically connected to the first and second sets of terminals on the board. A test board (34tb) including a means for physically connecting (Pcr) and detachable from the connectors (44, 45); the CPU (51) for instructing the access means (40, 43) to perform a connection test; And, including a register for latching the read data of the semiconductor memory (MM1, MM2), in response to the instruction of the connection test,
The access means (40, 40), wherein a signal is supplied to a line connected to the first set of terminals, a signal of the line connected to the second set of terminals is latched in a register, and returned as read information to the CPU (51). 43) An inspection device for a semiconductor memory connection system comprising:

The CPU (51) performs access to the access means (4) in the same manner as in the exchange when reading the semiconductor memories (MM1, MM2).
(0,43) to instruct a connection test, and as read information,
Obtain a loopback test signal. The CPU (51) can check whether or not this matches the reference information specified in the connection test, and can determine whether the electrical connection to the connector or the operation function is correct.

(4) Connectors (44, 45) for mounting the semiconductor memories (MM1, MM2), and data lines (RD) connected to the connectors for accessing the semiconductor memories mounted on the connectors. An address line (BA, RA) and a control line (RAS, CAS,...), A CPU (51) for instructing reading of the semiconductor memory, and the address line in response to a read instruction of the CPU (51). (BA, RA) and access means (40, 43) for providing data and control signals to control lines (RAS, CAS, ...), and a semiconductor memory connection system (51, 40,
42), the semiconductor memory (MM) is connected to the connectors (44, 45).
1, MM2), the first set connected to the address lines (BA, RA) and the second set connected to the data lines (RD) in the connector side terminal group with which the terminals of the memory contact. , The first and second sets of terminals (C
crV) and means (PcrV) for electrically connecting the first set of terminals on the board side and the second set of terminals on the board side, and a test board (34tbV) detachable from the connector; The CPU (51) instructing a connection test to (40, 43);
And a register for latching read data of the semiconductor memory (MM1, MM2). In response to the connection test instruction, a signal is supplied to an address line (BA, RA) connected to the first set of terminals. The access means (40, 43) for holding the signal until the latch of the read data to the register is completed and returning the data latched to the register to the CPU (51) as read information. Inspection device for semiconductor memory connection system.

[0014] The CPU (51) performs access to the access means (4) in the same manner as in the exchange when reading out the semiconductor memories (MM1, MM2).
(0,43) to instruct a connection test, and as read information,
Obtain a loopback test signal. The CPU (51) can check whether or not this matches the reference information specified in the connection test, and can determine whether the electrical connection to the connector or the operation function is correct. Inspection signal is address line (BA, RA)
Since only the data is output to the access means (40, 43), the access means (40, 43) may read the data on the data line at the same timing based on the same control signal as when actually reading the data from the semiconductor memory, and the CPU (51) And access means
(40, 43) Adds less functions for connection test.

(5) The CPU (51) associates the read information returned by the access means (40, 43) with a combination of a first set of terminals and a given signal determined in the connection test. The inspection device according to (3) or (4), which generates alarm information when the reference information is violated (T3, TV3). The alarm information indicates that there is an abnormality in the connection or operation of the semiconductor memory connection system.

(6) A printer (PTR), an image processing apparatus for converting image data into output image data and providing the output image data to the printer
(70), a system controller (30) that expands print data provided by the host (Pca) into image data and provides the image data to the image processing device (70), and semiconductor memories (MM1, MM2) and the above (3), ( An image forming apparatus comprising: a main controller (50) that includes the inspection device (51, 40, 42) of (4) or (5) and controls connection between the printer and other devices (PTR, 70, 30).

According to this, the system controller (30)
Inspection of electrical connection up to the connector for mounting the semiconductor memory (MM1, MM2) built into the device or the correctness of the operation function can be easily realized, and additional elements for it are few and simple. Operator's work is simplified.

(7) Synchronous DRAM module (M
M1, MM2) as storage means and the CPU (51) as its read / write controller, and in the memory system (51, 40, 42) for reading and writing via the access means (40, 43), the CPU (51)
Access means by register access from (40,43)
However, the mode shifts to a mode in which the memory control lines (RAS, CAS,...) Become output ports.

According to this, it is possible to determine the connection to the connectors (44, 45) or the quality of the operation function only by the memory read access from the CPU (51), and to determine whether each control signal (RAS, C
AS,...) And the RAM address (BA, RA) are operated at High (high level H) / Low (low level L) to perform memory reading, so that a defective portion can be easily specified.

(8) Synchronous DRAM module (M
M1, MM2) as storage means and the CPU (51) as its read / write controller, and in the memory system (51, 40, 42) for reading and writing via the access means (40, 43), the CPU (51)
The memory address lines (BA,
RA) is shifted to a mode in which it becomes an output port.

According to this, the connection to the connectors (44, 45) or the quality of the operation function can be determined only by the memory read access from the CPU (51), and the RAM address (B
A, RA) Each data bit is High (high level H)
/ Low (low level L) operation and memory reading,
It is easy to identify defective parts.

(9) Synchronous DRAM module (M
M1, MM2) as storage means and the CPU (51) as its read / write controller, and in the memory system (51, 40, 42) for reading and writing via the access means (40, 43), the CPU (51)
Supplied to memory by register access from
A transition is made to a mode in which the K line becomes an output port. According to this, the connection to the connectors (44, 45) or the quality of the operation function can be determined only by the memory read access from the CPU (51).

(10) Synchronous DRAM module
(MM1, MM2) as storage means and the CPU (51) as its read / write controller, and in the memory system (51, 40, 42) for reading and writing via the access means (40, 43), the CPU (5
According to the register access from 1), the mode shifts to a mode in which the serial / parallel control lines (SDA, SCL) become output ports. According to this, the connection to the connectors (44, 45) or the quality of the operation function can be determined only by the memory read access from the CPU (51).

(11) In the system of (7) to (10) above, when shifting to the connection test mode, the output of the memory control line of the access means (40, 43) is high by register access from the CPU (51). / Low can be set.

(12) In the system of (7) to (11), the access means (40, 4)
3) A memory control device characterized by accepting only mode switching access, output port register access and memory read access from the CPU (51).

(13) In the system of (7) to (12) above, an inspection board (34tb / 34tbV) having a memory control line and an address line looped back to the data bus is inserted into the RAM module connectors (44, 45). It is characterized by doing.

According to this, the RAM modules (MM1, MM
Inspection board (34tb / 34)
tbV), the quality can be determined by memory read access from the CPU (51), and the defective portion can be easily specified.
The inspection board (34tb / 34tbV) is a board with only wiring, so there is no possibility of destruction even if it is removed and inserted while the power is on.
It is cheap.

(14) In the system of (7) to (13) above, the data of the memory data bus is latched by the access means (40, 43) by the memory read access from the CPU (51), and this is latched by the CPU. It is characterized in that it is returned as a read value to (51).

(15) Synchronous DRAM module
(MM1, MM2) as storage means and the CPU (51) as its read / write controller, and in the memory system (51, 40, 42) for reading and writing via the access means (40, 43), the CPU (5
Access means (40, 40) by memory read access from (1)
43) is characterized in that the address is held until the data is latched.

(16) In the above (15), the test board (34tb / 34tb) in which the address lines (BA, RA) are looped back to the data bus (RD) to the RAM module connectors (44, 45).
V) is inserted.

(17) In the above (15) or (16), the memory data bus is latched by the access means (40, 43) by the memory read access from the CPU (51),
This is returned to the CPU (51) as a read value.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

[0033]

Embodiment 1 First Embodiment FIG. 1A shows an outline of an embodiment of the present invention. Shown there is an image scanner 6 on the color printer PTR.
2, an ADF 63, a sorter 11, and other image processing-related devices shown in FIG. 2, and a host PCa such as a personal computer (hereinafter referred to as a PC).
When print data as image information is provided from PCb or PCc via a LAN or a parallel I / F, the system can be printed out (image output).
In addition, the image forming apparatus shown in FIG. 1 is a digital color copying machine having a composite function, and can itself generate a copy of a document. The copier is a private branch exchange PBX.
Is connected to the public telephone network through the public telephone network,
Can communicate with remote facsimile.

FIG. 1B shows an outline of the mechanism of a printer PTR forming a part of the digital color copying machine shown in FIG. The printer PTR of this embodiment is a laser scanning type color printer of an electrophotographic system, and includes a printer mechanism, a paper feeding device (bank), a double-sided paper feeding device, and a post-processing device (sorter) 11. ing. To the laser scanner 3 of the printer mechanism PTR, image data decomposed into each color component of Bk (black), Y (yellow), M (magenta) and C (cyan) is given in units of each color. . Each color unit is one image forming unit.

At the time of monochrome recording, image data of one of the above four colors is supplied to the laser scanner 3. Photoconductor 1
Is driven to rotate at a constant speed, charged by the main charger 2 and the charged potential is adjusted to an appropriate potential by the quenching lamp QL. Then, the laser scanner 3 scans and projects the laser modulated by the image data on the charged surface. Thus, an electrostatic latent image corresponding to the image data is formed on the photoconductor 1. This electrostatic latent image is developed by a developing device (Bk) having a developing toner of a color corresponding to a designated color for image formation (for example, Bk) of a developing device 4 of a rotary positioning system, and a visible image, that is, a toner
It becomes an image. The toner image is transferred to the transfer belt 6 by the transfer charger 5, and is transferred by the transfer separation charger 8.
The transfer paper, which is transferred to the transfer paper fed by the registration roller 7 and carries the toner image, is fixed by the transport belt 9 to the fixing device 10.
Sent to. The fixing device 10 fixes the toner image on the transfer paper to the transfer paper by heating and pressing. After the fixing, the transfer paper is discharged to a sorter 11. The photoreceptor surface on which the transfer of the toner image has been completed is cleaned by the cleaning device 12. The surface of the transfer belt 6 where the transfer has been completed is wiped with a cleaning blade 13. Reference numeral 14 denotes a reflection type optical sensor called a P sensor for detecting the toner density on the photoreceptor surface.
Reference numeral 5 denotes a reflection type optical sensor for detecting a mark indicating the reference position of the transfer belt 6, and reference numeral 16 denotes a temperature sensor for detecting the temperature of the fixing roller.

In the case of color overprinting of two or more colors (the most typical one is full color printing), the above-described photosensitive member 1 is used.
The formation of the toner image thereon and the transfer to the transfer belt 6 are repeated for each color, and the toner images of each color are transferred on the transfer belt 6 in a superimposed manner. Transferred to transfer paper.

FIG. 2 shows an outline of an electric system of the image forming apparatus shown in FIG. The main controller 50 includes, in addition to the printer controller 30, an operation unit 5 that performs display for an operator and input control of function setting from the operator.
8, scanner 62 and automatic document feeder (ADF) 6
3. an image processing unit (IPU) 70 for performing control for writing a document image to an internal or external image memory and controlling image formation from the image memory, and a printer P
The control unit 90 and the like of the TR are connected. Each device and the main controller 50 exchange machine status and operation commands as needed.

A common bus P consisting of parallel and serial data buses, address buses and control signal buses
b, the printer controller 30, the main controller 50, and the bus control 61 are connected, and the IPU 70 and the printer 90 (PTR) can be additionally connected and removed.
And a facsimile unit (FCU) 110 are connected to the common bus Pb via connectors.
A device or image memory similar to or equivalent to the image processing or output device of the IPU 70 or lower is further provided with a common bus P.
It is also possible to additionally connect to an empty connector connected to b. An ID is individually assigned to a port (connector) of the bus Pb for connecting each device, and which device is connected to the bus Pb (connection between devices via the bus)
Are controlled by the main controller 50 via the bus control 61.

The printer controller 30 analyzes print data, which is image information from the outside (host PCa-PCc), and a command for instructing printing, develops the bitmap into a state in which the print data can be printed as output image data, Is analyzed from the command to determine the operation. A LAN control 21 and a parallel control 22 are provided to receive and operate the print data and the command through the LAN and the parallel I / F. The host PCa-PCc stores print data, document read data, output image data obtained by processing these for output, and compressed data, which are held or generated in the apparatus via the printer controller 30, and compressed data thereof. Can be forwarded to

The document scanner 62 condenses the reflected light of the lamp irradiation on the surface of the document on a light receiving element by a mirror and a lens. The light receiving element (CCD in the present embodiment) is a sensor board unit (hereinafter simply referred to as S
The image signal converted to an electric signal in the CCD is converted to a digital signal, that is, read image data on the SBU, and then converted to a main controller 5.
The data is output from the SBU to the image processing apparatus (IPU) 70 via the I / O port 0 (57: FIG. 3) and the common bus Pb. Automatic Document Feeder A Mounted on Scanner 62
The DF supplies and discharges a document to and from the scanner 62.

The main controller 50 uses the bus controller 61 to control the printer controller 30 or the scanner 6.
2, each device 70, 90, 1 via the common bus Pb
Bus connection control relating to the transfer of print data, document read data to the printer 10 or output image data obtained by processing these data, or compressed data obtained by compressing them, and conversely, the common bus is transmitted from each device 70, 90, 110. Bus connection control relating to the transfer of the same data to the printer controller 30 via the Pb, and the respective devices 70, 90,
Bus connection control relating to data transfer between 110 is performed.

In the flow of the image data, the bus control 61 of the main controller 50 on the common bus Pb causes
Realizes the composite function of digital copier. The FAX transmission function, which is one of the composite functions, performs image processing on image data read by the scanner 62 by the IPU 70, and executes the common bus Pb
Via the FAX control unit FCU110. In each job, for example, a copy function, a facsimile transmission / reception function, and a printer output function,
70, printer 90 and common bus Pb to FCU 110
The allocation of the usage right is controlled by the system controller 31 and the main controller 50 via the bus control 61.

The operation unit 58 includes various keys such as a liquid crystal touch panel, a numeric keypad, a clear / stop key, a start key, a mode clear key, an initial setting key, and a test print key. A message indicating the number of copies and the state of the image forming apparatus is displayed. The test print key is a key for printing only one copy regardless of the set number of prints and confirming a print result. In addition, "copy" function, "scanner"
There is a display for selecting a function, a “print” function, a “facsimile” function, a “storage” function, an “edit” function, and other functions and indicating that the function is being executed. When the initial setting key is operated, a menu for selecting an "initial value setting" function for setting various initial values, an "ID setting" function, a "use record output" function and a "connection test" function is displayed. Is done.

The "copy" function is a function of copying an image read by the document scanner 62 on the transfer paper by the printer 90 (PTR) by an operation designated.

The "scanner" function operates in response to an instruction from the operation unit 58 or the host PCa-PCc.
The function is to read the image of the original in step 2 and display it on the display of the host PCc, or to transfer the read image data to the host PCa to PCc via the printer controller 30.

The "print" function is a function of transmitting data provided by the host PCa to PCc connected via a LAN and a parallel I / F to the printer 90 (PTR) in accordance with an instruction from the host or the operation unit 58. This is a function to output (print out).

The “facsimile” function is a function of reading an image of a document by the scanner 62 and transferring the image data to the FCU 110. Also, a function of transferring data provided by the hosts PCa to PCc connected to the LAN and the parallel I / F or the like to the FCU 110 in accordance with an instruction from the host is included.

The "accumulate" function is executed during the execution of the current job (for example, when the apparatus is performing an image forming operation using the "copy" or "print" function) from an image read by the scanner 62 of another job or from the host PCa-PCc. Is stored in the memory in the printer controller 30 and printed out after the execution of the preceding job is completed.

The "edit" function is provided by the printer controller 3
0 print data, document read data, or output image data obtained by processing these for output, is displayed on the display of the host PCc, and text and / or image editing is performed, and output is performed as necessary (input command). This function performs the processing “print” or “facsimile”.

The “connection test” function is performed by the CPU 51 (FIG. 3) in the main controller 50 by the connector 4 in the block of the SDRAM 42 which is a semiconductor memory device.
This is a function for automatically inspecting whether circuit connection and circuit element functions up to 4, 45 (FIG. 4) are appropriate (normal) or not (abnormal).

FIG. 3 shows the configuration of the main controller 50. The main controller 50 controls the flow of image data, and the system controller 31 controls the entire system and manages activation of each resource. Function selection of the digital multifunction copier is performed by selecting and inputting the data through the operation board 58 connected to the I / O port 57 or the host PCa-PCc, and selecting the copy function, the FAX function, and the printout function and the processing contents. Set. The scanner 62 and the ADF 63 are connected to the I / O port 57. I / O
The port 57 is connected to the common bus Pb.

The main controller 50 includes a ROM 54 and a RAM 56 for storing programs and data, an IC card 52 for externally supplying font data and programs,
The contents of the mode instruction from the operation unit 58 (panel devices 59 to 60), the contents of the settings, the information for managing the use of the image output device, the results of use of the image output device, and other settings for which long-term storage is desired NVRAM 53 which is a non-volatile storage device for storing information and management information;
OM 54 and IC card 52 program, operation unit 3
Mode instruction from 0 and printer controller 30
The controller 50 controls the entire controller 50 and the bus controller 61 in response to commands from the host PCa to PCc, and controls the input devices 30, 62 and the output devices 70, 90, 110,
A CPU 51 for controlling a bus connection between the devices, and
An ASIC (Application Specific IC) 40 is included.

The ASIC 40 has a CPU I / F (interface) function, a bus control function, an access signal control function, and the like, and decodes (decodes) a request (command) from the CPU 51 and executes the command on each device. Control signal.

FIG. 4 shows a portion from the CPU 51 to the SDRAM 42. RAM in SDRAM 42
SDRAM modules MM1 and MM2 are mounted on the module connectors 44 and 45, respectively. The ASIC 40 allocates registers to read / write registers for temporarily holding (latch) transmission (write) data and reception (read) data and decoder data for converting CPU commands into destination control signals (instruction signals). , A data register, a buffer amplifier, and the like. The ASIC 40 decodes the command of the CPU 51 and, if the command specifies the SDRAM 42, stores the contents of the command (normal mode / connection test mode switching, read access, write access, output) in the memory I / F ASIC 43. Port register access).

The memory I / F 43 is also an ASIC.
Read / write register for temporarily holding (latch) write data and read data to DRAM, CPU
, A decoder that decodes the command into a memory access control signal, a sequencer that generates a control signal for reading / writing SDRAM, a serial-in / parallel-out shift-register-type test signal register for outputting a connection test signal, and an SDRAM module. A multiplexer (selection switch) for selectively outputting a control signal of the sequencer and a connection test signal of the test signal register to the attached connectors 44 and 45, and a mode switching signal are latched, and the multiplexer is switched correspondingly. In the normal mode, the connectors 44 and 45
, A control signal of a sequencer, a signal in a connection test mode, and an output signal controller for supplying a signal of a test signal register, and a data register and a buffer amplifier for allocating a register to data.

In this embodiment, the ASIC 40 has the CPU 5
1, the IC card 52 shown in FIG.
NVRAM 53, program ROM 54, font RO
M55, SDRAM 42 and I / O port 57
Controls access to the device for what the command specifies, and provides a memory I / F ASIC in SDRAM 42
43 controls access to SDRAM modules MM1 and MM2.

RD [63: 0] shown in the block of the memory I / F ASIC 43 shown in FIG.
Read / write data lines, BA, RA,
RAS, CAS, WE, DQM, CLKE, CS, CL
K, SDA and SCL are memory control lines (lines). Among these memory control lines (lines), BA is a 2-bit bank address line (memory address line), RA is a 2-bit column address line (memory address line), RAS (1 bit), and CAS (1 bit). ), WE (1 bit), DQM (8 bits), CS
(2 bits) are control signal lines, CLK is a 1-bit clock pulse line (CLK line), and SDA is a serial / parallel control (designation signal) line (serial /
SCL is a 1-bit serial synchronous clock pulse line.

Each RAM module connector 4
4, 45 are signals required for control as shown in FIG.
A, BA, CS, DQM, RAS, CAS, WE, CL
It is connected to a line for transmitting KE, SCL, SDA, CLK and a line of the data bus RD.

FIG. 5A shows a loopback inspection board 34t used for a connection test after assembling a printed circuit board on which the RAM module connectors 44 and 45 are mounted.
b schematically shows the loopback connection in a plane development,
(B) shows the loopback specification in a table format. When the SDRAM modules MM1 and MM2 are mounted on the connectors 44 and 45, the inspection board 34tb is connected to the address lines BA and RA and the control lines CS, DQM, RAS, CA
S, WE, CLKE, SCL, SDA, CLK) connected to the first set and the second set connected to the data line RD, and the first and second sets of terminals Ccr on the board side, and the board And a printed conductor Pcr for electrically connecting the first set of terminals on the board side and the second set of terminals on the board side, and connectors 44 and 45 similar to the SDRAM module.
Can be attached to and detached from. FIG. 5A shows, for example, 13 connector-side terminals connected to the address line RA [12: 0] and 13 connectors connected to the data line RD [12: 0]. Although it is shown whether the side terminals are connected by one printed conductor, each terminal is actually connected by 13 printed conductors. The same applies to the other lines BA, CS, and DQM that show two or more as a group.

The SDRAM modules MM1 and MM2 are removed from the connectors 44 and 45, and the connectors 44 and 45 are removed.
The inspection board 34tb is mounted on one of the address lines RA. For example, the memory I
When the signal H is supplied from the / F ASIC 43, the memory I /
If the circuit connection from the FASIC 43 to the connectors 44 and 45 and the wiring of the inspection board 34tb are normal, H appears on all the loop-back destination data lines RD [12: 0]. If there is a disconnection, H does not appear on any of the lines. Address line RA [12:
If H is applied to only one of the data lines RD [12: 0], for example, RA [0], H appears only in RA [0] in the loop-back destination data line RD [12: 0]. . If H does not appear, it can be determined that the disconnection is abnormal. RD [1
2: 0], it can be determined that a short circuit has occurred when H also appears on the other lines. Other address and control signal lines,
The quality of the connection of the read data line can be similarly checked.

In the case of the memory access system shown in FIG. 4, the CPU 51 controls the SDR via the ASICs 40 and 43.
Since the AM modules MM1 and MM2 are accessed, the SDRAM modules MM1 and M
M2 is removed and the inspection board 34t is attached to one of the connectors.
b, and the CPU 51 specifies the address to set all or a part of RA [12: 0] to H.
Performs read access in the register mode using the SDRAM as a register for the CPU 51, so that the signal at the loopback destination is read data RD [12: 0], R
The data is read as D [44:32], and the H signal distribution (contents of the read data) is compared with the H signal distribution (contents of the designated address data) of the transmission address RA [12: 0]. Is good or bad. A program that performs such a “connection test”
Stored in the program ROM 54, the CPU 51
Has a "connection test" function to execute this program.

FIG. 6A shows the operation of the operator for realizing the "connection test" function, and FIG.
5 shows the “connection test” function of the PU 51. The operator
SDRAM modules MM1,
MM2 is removed, and the inspection board 34tb is attached to one of the connectors 44 and 45, for example, 44 (step O).
pr1). Then, by operating the initial setting key of the operation unit 58, a selection menu of the "connection test" function is displayed on the liquid crystal display 59, and "connection test" is designated (step Opr2). Then press the start key. That is, an execution instruction is input (Opr3).

Referring to FIG. 6B. "Connection test"
When the start key is pressed following the designation of
Reads the "connection test" program from the ROM 54, and first executes "test 0" (T1) accordingly. Here, the CPU 51 gives the memory I / F ASIC 43 via the ASIC 40 the mode switching to the connection test mode, the access to the output port register, and the connection test signal (in the test 0, the test signal register clear instruction).

The memory I / F ASIC 43 clears the test signal register therein, and provides a multiplexer, a parallel output of the test signal register, and address and control signals RA, BA, CS, DQM, RAS, CAS.
The test signal is output to the connectors 44 and 45 instead of WE, CLKE, SCL, SDA and CLK.
This state is the connection test mode, and when this mode is entered, the memory I / F ASIC 43 accepts only mode switching access, output port register access and memory read access from the CPU 51.

When switching to the test signal output as described above, the memory I / F ASIC 43 latches the data of the data line RD [63: 0] in the read register while maintaining this state. That is, the address data and control signals to the connectors 44 and 45 are all set to L, and this L
Latches the data of the data line RD [63: 0] into the read register after a time sufficient for the data line RD [63: 0] to be looped back from the test board 34tb to become L. Then, the latch data is transferred to the ASIC 40, and the ASIC 40 transfers the data to the CPU 51.

The CPU 51 inverts the signal level of each bit of the RD [63: 0] data obtained in this manner, ie, the read data, so that all bits assigned to “test 0” are referred to as “H”. The information RD0 [63: 0] is collated with the corresponding bit by logical AND. If the AND of each bit is all H, this means that all of RD [63: 0] are L
Means that the circuit connection from the CPU 51 to the inspection board 34tb mounted on the connector 44 is normal for the time being. If there is a bit whose logical product is L, the CPU 51
Indicates that bit NO. And information indicating a leak (short circuit) abnormality is displayed on the liquid crystal display 59 (T3).

If the result of "test 0" is normal, the CPU
51 executes “Test 1” (T4). here,
The CPU 51 executes the memory I / F AS via the ASIC 40
The output port register access and connection test signal (all bits of the test signal register: H in test 1) is supplied to the IC 43.

The memory I / F ASIC 43 sets all bits of the test signal register therein to H, and latches the data on the data lines RD [63: 0] to the read register while maintaining this state. That is, the address data and control signals to the connectors 44 and 45 are all set to H, and after a sufficient time for the H to loop back from the inspection board 34tb and the data line RD [63: 0] to become H, the data line The data of RD [63: 0] is latched in the read register. And latch data is A
The ASIC 40 transfers the data to the CPU 51
Transfer to

CPU 51 obtains RD [6
3: 0] of the data, the signal level of each bit is assigned to “test 1”, and all bits are reference information R of H
Collation is performed with the logical product of D0 [63: 0] and the corresponding bit. If the logical product of each bit is all H, this is RD
[63: 0] are all H, and the CPU 4
4 means that the circuit connection up to the test board 34tb mounted on the device 4 is normal. If there is a bit whose logical product is L, the CPU 51 determines that bit NO. And information indicating the disconnection abnormality is displayed on the liquid crystal display 59 (T
6).

If the result of "test 1" is normal, the CPU
51 executes “Test 2” (T7). In “Test 2”, the CPU 51 sends the output port register access and connection test signal (the i-th bit of the test signal register = H, the others are L, and the others are L. Give 1).

The memory I / F ASIC 43 sets H in the i-th bit of the test signal register and L in the other bits in the memory I / F ASIC 43. The data lines RD [63: 0] are maintained while maintaining this state. Is latched in the read register. That is, only one of the address data and the control signal i to the connectors 44 and 45 is set to H, and this H is the data line RD looped back from the inspection board 34tb.
After a sufficient time for [63: 0] to become H, the data on the data line RD [63: 0] is latched in the read register. Then, the latch data is transferred to the ASIC 40,
The SIC 40 transfers it to the CPU 51.

The CPU 51 obtains RD [6
3: 0], the signal level of each bit is assigned to the i-th bit (line i) of “test 2”. The data in which the line i loops back is H, and the others are L reference information RDiH. [63: 0] is collated with the signal level of the corresponding bit. If the signal levels of all the bits match, this means that there is no disconnection or leakage (short circuit) in line i. If there is a mismatch bit, C
PU 51 stores the bit NO. And information indicating a leak (short circuit) if the line is the line i and a leak (short circuit) if the line is not the line i on the liquid crystal display 59 (T9). CP
The U51 executes such processing by sequentially switching the bit (line) i corresponding to each line (one) of the addresses RA and RB and all the control signals CS to CLK.

If the result of "Test 2" is normal, the CPU
51 executes “Test 3” (T10). In “test 3”, the CPU 51 sends the output port register access and connection test signal to the memory I / F ASIC 43 via the ASIC 40 (in test 3, the i-th bit of the test signal register = L, the others are H. The first is i = 1).

The memory I / F ASIC 43 sets L in the i-th bit of the test signal register and H in the other bits of the memory I / F ASIC 43. The data lines RD [63: 0] are maintained while maintaining this state. Is latched in the read register. That is, only one of the address data and the control signal i to the connectors 44 and 45 is set to L, and this L is the data line RD looped back from the inspection board 34tb.
After a sufficient time for [63: 0] to become L, the data on the data line RD [63: 0] is latched in the read register. Then, the latch data is transferred to the ASIC 40,
The SIC 40 transfers it to the CPU 51.

CPU 51 obtains RD [6
3: 0] of data, the signal level of each bit is assigned to the i-th bit (line i) of “test 3”. The data in which line i loops back is L, and the others are H reference information RDiL. [63: 0] is collated with the signal level of the corresponding bit. If the signal levels of all the bits match, it means that there is no leak (short circuit) or disconnection in line i. If there is a mismatch bit, C
PU 51 stores the bit NO. And information indicating a leak (short circuit) if the line is the line i, and information indicating a disconnection if the line is not the line i, on the liquid crystal display 59 (T12). C
The PU 51 performs such processing by setting the line i to the address R
A, RB and all the control signals CS to CLK are sequentially switched to each line (one line) and executed.

If the result of "Test 3" is normal, C
The PU 51 cancels the test mode (T15). That is, via the ASIC 40, the memory I / F ASIC
43, a mode switching signal to a normal mode is given. In response to this, the memory I / FASIC 43 controls the internal multiplexer, the parallel output of the sequencer, and the read / write control signals RA, BA, CS, DQM, RA.
The output is switched to the normal output, which is output to the connectors 44 and 45 as S, CASWE, CLKE, SCL, SDA, and CLK. The operator can check the inspection board 34t from the connector 44.
When "b" is removed and attached to the connector 45, "connection test" is set by interactive input, and a start is input, the CPU 51 executes the "connection test" shown in FIG. . Thereby, the quality of the connection of each line from the CPU 51 to the inspection board of the connector 45 and the inspection of the correctness of the operation of each element are performed.

As described above, in the “connection test”, C
The PU 51 sets an internal register of the memory I / F ASIC 43 so as to shift to the test mode. The memory I / F ASIC 43 has a function equivalent to the output port control that outputs the value of each control line according to the register setting from the CPU 51. The CPU 51 sets H or L to each control line. Each control line is looped back to the data bus RD by the loopback inspection board 34tb inserted into the connector. Therefore, an 8-byte read access is performed by the CPU 51, and the memory I / F ASIC is used.
43 latches the data bus and returns the value to the CPU 51. The CPU 51 determines whether the value set for each control line matches the read value returned by the memory I / F ASIC 43. If they do not match, an error is displayed, indicating that the connection is defective. Further, it outputs information for specifying a defective portion. Since only one of the tests 0 to 3 is indeterminate due to a poor connection, it may be coincidentally determined to be normal, so that the tests 0 to 3 in a plurality of modes are preferably performed as described above.

Second Embodiment FIG. 7A shows RAM module connectors 44 and 4.
5 shows a loop-back connection of the test board 34tbV of the second embodiment used in a connection test after assembling the printed circuit board on which the printed circuit board 5 is mounted, and FIG. The inspection board 34tbV connects the SDRAM modules MM1, MM to the connectors 44, 45.
The first set on the board side contacts the first set to which the address lines BA and RA are connected and the second set to which the data line RD is connected, among the connector-side terminal groups with which the terminals contact when the second set is mounted. And the second set of terminals CcrV
And a printed conductor PcrV for electrically connecting the first set of terminals on the board side and the second set of terminals on the board side;
Like the RAM module, it can be attached to and detached from the connectors 44 and 45.

Inspection board 34tbV of the second embodiment
Are the SDRAM modules MM1 and MM of the CPU 51.
Only the address lines RA and BA are loop-back-connected to the data line RD so that the CPU 51 can obtain the loop-back of the inspection signal by the same read access as the read access to No. 2. Since the control signal line is floating on the inspection board 34 tbV, C
The PU 51 can provide the memory I / F ASIC 43 with exactly the same read access signal as in the case of the read access to the SDRAM modules MM1 and MM2, and read the loopback information.

This inspection board 34tbV is a memory shown in FIG. 4 of a multifunction color copying machine of a second embodiment (not shown) having the same hardware as the multifunction color copying machine of the first embodiment shown in FIGS. The present invention is applied to a memory system having the same hardware configuration as the system. The outline of the “connection test” function of the CPU 51 of the second embodiment is the same as that of the first embodiment, as shown in FIG. 8B, but the tests 0 to 3 (TV1, TV4, TV7 , TV1
The contents of 0) and the configuration and function of the memory I / F ASIC 43 are different in accordance with the difference of the inspection board 34tbV. The operation and input operation for the connection test by the operator are the same as those in the first embodiment, as shown in FIG.

Referring to FIG. 8B. "Connection test"
When the start key is pressed after the designation of the "connection test", the CPU 51 of the second embodiment stores the "connection test" program in the ROM 5.
4 and read "Test 0" accordingly.
(TV1) is executed. This is because the CPU 51
The memory I / F ASIC 43 is provided with the address data RA and BA in which each bit is all L via the memory 40 and a read command for reading (reading) the memory data of the address. The memory I / F ASIC 43 is
Each bit holds the output of address data RA, BA of L level, and the read access control signals CS, DQM, R
AS, CAS, WE, CLKE, SCL, SDA, CL
By outputting K, the data of the data line RD is latched in the data bus latch register in the ASIC 43. That is, all the address data bits to the connectors 44 and 45 are set to L, and after a time sufficient for the L to loop back from the test board 34tbV and the data line RD [63: 0] to become L, the data line RD [ 63: 0] is latched in the read register. Then, the latch data is transferred to the CPU 51 via the ASIC 40.

The CPU 51 inverts the signal level of each bit of the data of RD [63: 0] obtained in this manner, that is, read, so that all bits assigned to “test 0” are referred to as “H”. Information RD0V [63: 0];
Match by the logical product of the corresponding bits. If the logical product of each bit is all H, this means that all of RD [63: 0] are L, and the circuit connection of the address line and the data line from the CPU 51 to the test board 34 tbV mounted on the connector 44 is normal for the time being. Means that If there is a bit whose logical product is L, the CPU 51 determines that bit NO. And information indicating a leak (short circuit) abnormality is displayed on the liquid crystal display 59 (TV3).

If the result of "Test 0" is normal, the CPU
51 executes “test 1” (TV4). In “test 1”, the CPU 51 transmits the memory I via the ASIC 40
/ FAASIC 43 is provided with address data RA and BA in which each bit is all H and a read command for reading (reading) memory data at the address. The memory I / F ASIC 43 holds the output of the address data RA and BA in which each bit is all H, and reads the read access control signals CS, DQM, RAS, CAS, WE, C
Outputs LKE, SCL, SDA, CLK and ASIC
43, the data line RD is stored in the data bus latch register.
Latch data. That is, the connectors 44 and 45
All the data bits of the data line RD [63: 0] are set to H, and after this H is looped back from the inspection board 34tbV and the data line RD [63: 0] becomes H, the data of the data line RD [63: 0] Is latched in the read register. Then, the latch data is transferred to the CPU 51 via the ASIC 40.

The CPU 51 sets the signal level of each bit of the RD [63: 0] data thus obtained, ie, the read data, to the reference information RD0V [ 63: 0] and the corresponding bit. If the AND of each bit is all H, this means that all of RD [63: 0] are H and C
Inspection board 34t attached to connector 44 from PU51
It means that the circuit connection of the address line and the data line up to bV is normal. If the logical product is L
Is present, the CPU 51 determines that bit NO. Is displayed on the liquid crystal display 59 (TV6).

If the result of "Test 1" is normal, the CPU
51 executes “Test 2” (TV7). In “test 2”, the CPU 51 sets the address data RA and BA in the memory I / F ASIC 43 to the memory I / F ASIC 43 via the ASIC 40 by setting only one of the data bits i to H, and setting the other to L and the memory data of the address. Is given. Memory I / F ASIC4
3 holds the address data and outputs the read access control signals CS, DQM, RAS, CAS, WE, and CLK.
E, SCL, SDA, and CLK are output to the ASIC 43
The data of the data line RD is latched in the data bus latch register in the internal memory. Then, the latch data is transferred to the ASIC 40.
Is transferred to the CPU 51 via.

The CPU 51 sets the signal level of each bit of the RD [63: 0] data obtained in this manner, ie, the read data, to the i bit of the address data assigned to “test 2” and the The backed-up data line is H reference information RDiHV [63: 0].
And by matching the corresponding bits. When the corresponding bits match, it means that the circuit connection of the address line i and the data line loop-back connected thereto from the CPU 51 to the inspection board 34 tbV mounted on the connector 44 is normal. If there is a mismatch bit, the CPU 51 sets the bit number. Is displayed on the liquid crystal display 59 (TV).
9). If it is determined to be normal, the CPU 51 executes such processing by sequentially switching the line i to each line (one line) of the addresses RA and RB.

If the result of "Test 2" is normal, the CPU
51 executes “Test 3” (TV10). In “test 3”, the CPU 51 stores the address data RA, BA in the memory I / F ASIC 43 via the ASIC 40.
, Only one of the data bits i is set to L and the others are set to H, and a read command for reading the memory data of the address is given. Memory I / F ASIC
43 holds the address data and stores the read access control signals CS, DQM, RAS, CAS, WE, and CLK.
E, SCL, SDA, and CLK are output to the ASIC 43
The data of the data line RD is latched in the data bus latch register in the internal memory. Then, the latch data is transferred to the ASIC 40.
Is transferred to the CPU 51 via.

The CPU 51 sets the signal level of each bit of the RD [63: 0] data obtained in this way, ie, the read data, to the i bit of the address data assigned to “test 3” and the The backed-up data line is L reference information RD3iLV [63: 0]
And by matching the corresponding bits. When the corresponding bits match, it means that the circuit connection of the address line i and the data line loop-back connected thereto from the CPU 51 to the inspection board 34 tbV mounted on the connector 44 is normal. If there is a mismatch bit, the CPU 51 sets the bit number. Is displayed on the liquid crystal display 59 (TV).
12). The CPU 51 performs such a process on the line i,
The processing is performed by sequentially switching to each line (one line) of the addresses RA and RB.

If the result of this "test 3" is normal, C
The PU 51 cancels the test mode (TV 15). When the operator removes the inspection board 34tbV from the connector 44, mounts it on the connector 45, and sets a “connection test” by interactive input and inputs a start, the CPU 51 similarly to FIG. Perform the "connection test" shown. As a result, the quality of the connection of each line from the CPU 51 to the inspection board of the connector 45 is determined.
A check of the correctness of the operation of each element is performed.

FIG. 9 shows the memory read access timing. When the memory read access (read access) from the CPU 51 starts, the memory I / F ASIC 43
Issues an active command in R2, issues a read command in R4, and latches data in R7. BA (bank address) and RA (column address)
Continue to be held until R7, respectively.

In the "connection test" TpcV31 shown in FIG.
An 8-byte read access is made to 4, 45, and memory I
The / F ASIC 43 latches the data bus and the CPU 5
Return that value to 1. The value is R7 as shown in FIG.
Bank address BA and column address R held until
A. The CPU 51 determines whether the accessed bank address BA and column address RA match the read values. If they do not match, an error is displayed, indicating that the connection is defective. Further, it outputs information for specifying a defective portion. If only one of the tests 0 to 3 is a connection test, it may be indeterminate due to poor connection and may match by chance. Therefore, it is preferable to execute a plurality of tests 0 to 3 as described above.

[Brief description of the drawings]

FIG. 1A is a perspective view showing the appearance of a multifunction color copying machine which embodies the present invention in one embodiment, and FIG. 1B is a block diagram showing an outline of the mechanism of the color printer PTR shown in FIG.

FIG. 2 is a block diagram showing an outline of an electric system of the copying machine shown in FIG.

FIG. 3 is a block diagram showing a configuration of a main controller 50 shown in FIG.

FIG. 4 is a block diagram showing a configuration of an SDRAM 42 shown in FIG.

5A is a plan view schematically showing loopback wiring of an inspection board 34tb used in the first embodiment mounted on the connectors 44 and 45 shown in FIG. 4, and FIG. 5B is a plan view of a wiring specification table. FIG.

6A is a flowchart showing a work flow of an operator for performing a “connection test”, and FIG.
9 is a flowchart showing an outline of a “connection test” of the CPU 51 of the first embodiment shown in FIG.

7A is a plan view schematically showing loopback wiring of an inspection board 34tbV used in a second embodiment mounted on the connectors 44 and 45 shown in FIG. 4, and FIG. 7B is a plan view of a wiring specification table. FIG.

FIG. 8A is a flowchart showing a work flow of an operator for performing a “connection test”, and FIG.
9 is a flowchart illustrating an outline of a “connection test” of the CPU 51 according to the embodiment.

FIG. 9 shows a connector 4 according to the CPU 51 of the second embodiment.
4 and 45, the connector 4
4 is a time chart showing a temporal change of a read control signal given to the read control signals 4 and 45.

[Explanation of symbols]

PCa to PCc: Personal computer PTR: Color printer PBX: Private branch exchange 1: Photoconductor 2: Main charger 3: Laser scanner 4: Developing device 5: Transfer charger 6: Transfer belt 7: Registration roller 8: Transfer separation charger 9: Conveying belt 10: Fixing device 11: Sorter 12: Cleaning device 13: Cleaning blade 14: Optical sensor 15: Optical sensor Pb: Common bus MM1, MM2: SDRA
M module Ccr, CcrV: Connection terminal Pcr, PcrV: Loopback printed conductor

Claims (6)

[Claims] 1. A semiconductor memory including a connector for mounting a semiconductor memory, a data line, an address line, a control line connected to the connector, and memory access means for accessing the semiconductor memory mounted on the connector. A first set of a connection system, including at least one of an address line connected and a control line connected, in a connector-side terminal group that contacts a terminal of the memory when the semiconductor memory is mounted on the connector; Electrically connecting a second set including those connected to the data lines, applying a signal to the line connected to the first set of terminals by the memory access means, and connecting the second set of terminals to the second set of terminals; A method for inspecting a connection system of a semiconductor memory, comprising: 2. A board-side first set and a second board-side set that contact the first and second sets of terminals in a connector-side terminal group.
A set of terminals and means for electrically connecting the first set of terminals on the board side and the second set of terminals on the board side, and by attaching an inspection board detachable to the connector to the connector. 2. The inspection method according to claim 1, wherein the first and second sets of terminals on the connector side are electrically connected. 3. A connector for mounting a semiconductor memory, a data line, an address line and a control line connected to the connector for accessing the semiconductor memory mounted on the connector, and instructing reading of the semiconductor memory. A semiconductor memory connection system including a CPU and access means for providing data and control signals to the address line and the control line in response to a read instruction from the CPU; a terminal of the memory when the semiconductor memory is mounted on the connector; A board that contacts a first set including at least one of an address line connected and a control line connected, and a second set including a data line connected, in a connector-side terminal group that contacts The first and second sets of terminals on the board side and the first set of terminals on the board And means for electrically connecting the de-side second set of terminals,
An inspection board detachable from the connector; the CPU for instructing the access means to perform a connection test; and a register for latching read data of the semiconductor memory; Apply a signal to the line connected to the first set of terminals,
An access unit for latching a signal of a line connected to a set of terminals in a register and returning the signal to the CPU as read information; 4. A connector for mounting a semiconductor memory, a data line, an address line, and a control line connected to the connector for accessing the semiconductor memory mounted on the connector, and instructing reading of the semiconductor memory. A semiconductor memory connection system including a CPU and access means for providing data and control signals to the address line and the control line in response to a read instruction from the CPU; a terminal of the memory when the semiconductor memory is mounted on the connector; Of the connector-side terminals in contact with the first set connected to the address line and the second set connected to the data line.
A connector, comprising: a first set of terminals on the board side and a second set of terminals in contact with each of the sets; and means for electrically connecting the first set of terminals on the board side and the second set of terminals on the board side; A CPU for instructing the access means to perform a connection test; and a register for latching read data of the semiconductor memory, wherein the first board is responsive to the connection test instruction. Said access means for applying a signal to an address line connected to a set of terminals, holding the signal until the latching of the read data to the register is completed, and returning the data latched in the register to the CPU as read information; Inspection apparatus for semiconductor memory connection system comprising: 5. The CPU according to claim 1, wherein said read information returned by said access means violates reference information associated with a combination of a first set of terminals and a given signal determined in said connection test. The inspection device according to claim 3, wherein the inspection device generates information. 6. A printer, an image processing apparatus that converts image data into output image data and supplies the output image data to the printer, a system controller that expands print data supplied by a host into image data and provides the image data to the image processing apparatus, and a semiconductor memory. An image forming apparatus comprising: a main controller including the inspection apparatus according to claim 3, wherein the main controller controls connection between the printer and another apparatus.