JP2001339312A - Variable length decoding circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable length decoding circuit that reduces the circuit scale and its layout area so as to decrease delay in a decoded output. SOLUTION: The variable length decoding circuit sequentially decodes a bit stream consisting of consecutive variable length code words and provides the output, and is provided with an interface section that obtains accurate values of the code lengths of the decoded variable length code words and extracts and outputs consecutive data in N-bit length depending on the accumulated value from consecutive data in 2N-bit length (N is the longest code length of the variable length code) in the bit stream and with a decoding section that receives the output of the interface section, decodes it by using a lookup table for a code word included in the output of the interface section received before the output of the interface section, outputs the decoded result and outputs the code length of the decoded code word to the interface section. Since the interface section uses the decoding section to extract required data from the data in 2N-bits, the circuit scale can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable length code decoding circuit.

[0002]

2. Description of the Related Art When a moving image is communicated or recorded, the image is compression-encoded in order to reduce the bandwidth of communication means and the capacity of a recording medium. H.264 is an international standard video coding method. 261, MPEG (moving p
icture experts group 1) and MPEG2.

[0003] These encoding methods include motion vector detection and motion compensation, and DCT (discrete cosine transfor- mation).
m), quantization, zigzag scan, variable length coding, and the like. Variable-length coding is a coding method that converts a quantized fixed-length codeword into a bitstream of variable-length codewords according to statistical properties to reduce the average code amount. In order to decode such a bit stream and reproduce a moving image, it is necessary to perform variable-length decoding for converting a variable-length codeword into original fixed-length data. In variable-length decoding, since the length of a codeword is not constant and the head position of each variable-length codeword in a bit stream cannot be specified, it is necessary to decode the code words in the order in the bit stream.

Various variable length decoding circuits have been proposed to realize the variable length decoding at high speed. An example of a conventional variable length decoding circuit is disclosed in US Pat.
Japanese Patent Publication No. 38 discloses an example. FIG. 11 is a block diagram of an example of such a conventional variable-length decoding circuit.
The variable length decoding circuit of FIG. 11 decodes a variable length code having a maximum code length of 16 bits.

The buffer 901 stores the input bit stream, and when the read signal RD is "1", in the next cycle, stores the stored bit stream in 16-bit units in the first barrel shifter 911.
And output to the first input register 912. Buffer 9
01 holds its output for one cycle.

The first input register 912 and the second input register 913 have a 16-bit configuration, and take in input data in the next cycle when the update signal is "1".

The first barrel shifter 911 includes an adder 91
4 is shifted by the shift amount (value: 1).
48-bit data obtained by concatenating the output of the second input register 913 as the upper 16 bits, the output of the first input register 912 as the middle 16 bits, and the output of the buffer 901 as the lower 16 bits. Among them, 16-bit data of the (shift amount + 1) th bit to (shift amount + 16) th bit from the most significant bit is output, and this is written to the first barrel shift register 922. Here, the most significant bit of the 48-bit data obtained by concatenation is the first bit.

The second barrel shifter 921 uses the output of the shift amount register 925 as the shift amount (value: 1 to 16), sets the output of the second barrel shifter register 923 to the upper 16 bits, and sets the first barrel shifter register 922
Of the 32-bit data obtained by concatenating the output of as the lower 16 bits, the (shift amount + 1) th bit to
The 16-bit data of the (shift amount + 16) th bit is output and written to the second barrel shifter register 923.

The look-up table 924 performs variable length decoding on the output of the second barrel shifter 921,
The decoding result DC and the code length CL (value: 1 to 16) are output, and the code length is written to the shift amount register 925.
The lookup table 924 is a table configured to output a decoding result and a code length corresponding to each variable-length codeword. In the look-up table 924, the first bit of the code word is input as the most significant bit.

The adder 914 has a shift amount register 925
(Values: 1 to 16) and the output of the accumulation register 915 (values: 0 to 15), and outputs an addition result SM. The adder 914 writes the carry signal CR which becomes 1 when the addition result SM is 16 to 31 into the hold register 916, and generates a remainder RM (value:
0 to 15) are written to the accumulation register 915. That is, of the 5-bit addition result SM obtained by adding the output of the 5-bit shift amount register 925 and the output of the 4-bit accumulation register 915, the most significant bit becomes the carry signal CR, and the remaining 4 bits Is 16 of the addition result SM
Modulo RM. The carry signal CR is used as an update signal for the first input register 912 and the second input register 913, and the read signal RD output from the hold register 916 is used as a read signal for the buffer 901.

FIG. 12 is an explanatory diagram showing an example of a data flow for each cycle in the variable length decoding circuit of FIG. For example, "a1-a8" is a1, a2, a3, a
It is assumed that it represents 8-bit data connected to 4, a5, a6, a7, and a8. In FIG. 12, for example, the buffer output in the 0th cycle is “a1-a8b1-b6c1-c2”.
Indicates 16-bit data in which a1-a8, b1-b6, and c1-c2 are consecutively arranged.

In FIG. 12, an update signal, a read signal, a shift amount of the first barrel shifter, and a shift amount of the second barrel shifter in the 0th to second cycles are used to set data as initial states in each register. , "1", "1", "16", and "16" are used, respectively. After the third cycle, the processing is repeated using the values of the carry signal, read signal, accumulation register, and shift amount register obtained as a result of the processing.

As described above, the output of the decoding result is obtained every cycle. At the start of decoding, the input buffer 901
In the second cycle, two cycles after the 0th cycle in which the first data is output, the first decoded output is obtained.

[0014]

However, the conventional variable length decoding circuit as shown in FIG. 11 requires two input registers, and requires a 48-bit input and 16-bit output circuit as the first barrel shifter. is there. For this reason, the circuit scale becomes large, and the circuit needs a large layout area when it is realized by an LSI or the like.

In the conventional variable length decoding circuit as shown in FIG. 11, at the start of decoding, a decoded output is obtained only two cycles after the data in the input buffer is output. When the bit stream includes a plurality of variable-length code streams, information other than the variable-length code such as a header is included between the respective variable-length code streams. In such a case, the streams of the variable length codes are not continuous, and the variable length decoding cannot be performed continuously. For this reason, if variable-length decoding cannot be performed continuously, a delay of two cycles occurs at the start of decoding of each variable-length code stream, and a large number of cycles is required to decode the entire bit stream. .

An object of the present invention is to solve such a problem, and it is an object of the present invention to reduce a circuit scale and a layout area in a variable length decoding circuit and to reduce a delay of a decoding output.

[0017]

Means for Solving the Problems To solve the above problems, a means according to the present invention is a variable length decoding circuit for sequentially decoding and outputting a bit stream in which code words of variable length codes are continuous. Where the accumulated value of the code lengths of the codewords of the decoded variable-length codes is calculated, and from the data having a continuous length of 2N or 2N-1 bits (N is the longest code length of the variable-length codes), An interface unit that extracts and outputs data of a continuous length of N bits according to the accumulated value, and an output of the interface unit as an input;
A decoding is performed on the codewords included in this and the output of the interface unit input before this using a look-up table, and a decoding result is output, and the code of the decoded codeword is output. A decoding unit for outputting the length to the interface unit.

According to the first aspect of the present invention, N bits of data required by the decoding unit are extracted from continuous data of 2N or 2N-1 bits of the bit stream, so that the circuit scale is reduced. be able to.

According to a second aspect of the present invention, in the variable length decoding circuit according to the first aspect, the interface unit includes an accumulation register for storing and outputting a remainder obtained according to the accumulated value. , The code length output by the decoding unit and the remainder output by the accumulation register are added to obtain an addition result corresponding to the accumulation value, and the quotient and remainder obtained by dividing the addition result by N are respectively represented by digits. An adder that outputs a carry signal and a new remainder, and an input register that stores and outputs data of a continuous length N or N−1 bits of the bit stream when the value of the carry signal is 1. , The output of the input register and the subsequent N-bit data of the bit stream are concatenated so that the order of each bit is the order in the bit stream, and the accumulation register outputs A barrel shifter that uses the remainder as the value of the shift input, takes out data of a continuous length of N bits from the bit corresponding to the value of the shift input, and outputs the data to the decoding unit, It is provided with.

According to the second aspect of the present invention, the carry signal is used to update the data stored in the input register, and the remainder of the addition result is written to the accumulation register. Used as For this reason, when the accumulated value of the code length exceeds the longest code length and it is necessary to shift by a shift amount exceeding the longest code length, the shift performed by the barrel shifter can be a small shift amount. This is because the shift of the shift amount equal to the longest code length is performed by updating the input register, and the shift of the remaining shift amount is realized by the barrel shifter in the next cycle. Therefore, the bit width of the barrel shifter can be reduced. Also, since only one input register is required, the number of cycles for the initial setting is one.

According to a third aspect of the present invention, in the variable length decoding circuit according to the second aspect, the barrel shifter comprises:
Counting from the first bit of the input data, (M +
2) It is characterized in that data of a continuous length of N bits are output from the (M is the value of the shift input) bit.

According to the third aspect of the present invention, the interface unit can select and output N-bit data required by the decoding unit according to the value of the shift input.

According to a fourth aspect of the present invention, in the variable length decoding circuit according to the first aspect, the decoding section includes a barrel shifter, a barrel shifter register, and a look-up table, and the barrel shifter includes The data output by the barrel shifter register and the data output by the interface unit are connected so that the order of each bit is the order in the bit stream, and the code length output by the lookup table is used as the value of the shift input. ,
Among the data obtained by concatenation, data of a continuous length of N bits is extracted and output from the bit corresponding to the value of the shift input, and the barrel shifter register stores an output of the barrel shifter, The lookup table outputs a decoding result corresponding to a code word included in the output of the barrel shifter register, and outputs a code length of the code word.

According to the fourth aspect of the present invention, the output of the interface section is directly connected to the barrel shifter of the decoding section, and the output of the barrel shifter is written to the barrel shifter register. Therefore, the number of barrel shifter registers can be reduced.

According to a fifth aspect of the present invention, in the variable length decoding circuit according to the fourth aspect, the barrel shifter comprises:
Counting from the first bit of the input data, (L +
It is characterized in that data of a continuous length of N bits is output from the 1) th bit (L is the value of the shift input).

According to the invention of claim 5, N-bit data starting with the code word to be decoded next can be input to the lookup table.

According to a sixth aspect of the present invention, in the variable length decoding circuit according to the fourth aspect, the decoding section further includes a code length conversion circuit for subtracting 1 from the code length and outputting the result. The barrel shifter uses an output of the code length conversion circuit as a value of the shift input instead of the code length,
Counting from the first bit of the input data, (L +
2) It is characterized in that data having a length of N bits continuous from the bit is output.

According to the invention of claim 6, the value of the shift input to the barrel shifter becomes small. In particular, the longest code length is 2
In this case, the number of bits for representing the value of the shift input decreases, and the bit width of the shift input to the barrel shifter can be reduced.

According to a seventh aspect of the present invention, in the variable length decoding circuit according to the first aspect, the decoding section includes a barrel shifter, first and second barrel shifter registers,
A lookup table and a shift amount register,
The barrel shifter concatenates the data output from the first and second barrel shifter registers so that the order of each bit is the order in the bit stream, and changes the value corresponding to the output of the shift amount register to the value of the shift input. And outputs data of a continuous length of N bits from the bit corresponding to the value of the shift input out of the data obtained by concatenation, and the first barrel shifter register comprises: Store the output of the
The second barrel shifter register stores and outputs an output of the barrel shifter, and the lookup table outputs a decoding result corresponding to a codeword included in the output of the barrel shifter. And outputs the code length of the codeword.
The shift amount register stores and outputs a value corresponding to the code length.

According to the seventh aspect of the present invention, N-bit data including a variable-length code word to be decoded can be extracted from the data output by the interface unit and sequentially decoded.

In the invention according to claim 8, in the variable length decoding circuit according to claim 7, the shift amount register stores and outputs the code length, and the barrel shifter stores the code length. Using the output of the quantity register as the value of the shift input and counting from the first bit of the input data, (L + 1) th (L is the value of the shift input)
, And outputs data of a continuous length of N bits starting from the first bit.

According to the eighth aspect of the invention, N-bit data starting with the code word to be decoded next can be input to the look-up table.

According to a ninth aspect of the present invention, in the variable length decoding circuit according to the seventh aspect, the decoding unit further includes a code length conversion circuit that outputs a value obtained by subtracting 1 from the code length. The barrel shifter uses, as the value of the shift input, the code length obtained by subtracting 1 input through the code length conversion circuit and the shift amount register, counting from the first bit of the input data, and (L + 2) ) It outputs N-bit data continuous from the (th) bit.

According to the ninth aspect, the value of the shift input to the barrel shifter is reduced. In particular, the longest code length is 2
In this case, the number of bits for representing the value of the shift input decreases, and the bit width of the shift input to the barrel shifter can be reduced.

According to a tenth aspect of the present invention, there is provided the variable length decoding circuit according to the first aspect, further comprising an interface unit according to the second aspect and a decoding unit according to the fourth aspect. is there.

According to the tenth aspect of the present invention, the output of the barrel shifter of the interface section is directly connected to the barrel shifter of the decoding section, and the output of the barrel shifter of the decoding section is written into the barrel shifter register. Therefore, the number of barrel shift registers can be reduced. it can.

According to an eleventh aspect of the present invention, in the variable length decoding circuit according to the first aspect, the interface unit according to the second aspect and the decoding unit according to the seventh aspect are provided. is there.

According to the eleventh aspect, N-bit data including a code word of a variable length code to be decoded can be extracted from the data output by the barrel shifter of the interface unit, and can be sequentially decoded.

According to a twelfth aspect of the present invention, in the variable length decoding circuit according to the tenth or eleventh aspect, the adder includes a code length output by the decoding unit and a remainder output by the accumulation register. And a value obtained by adding 1 to the value obtained by adding the above is obtained as the addition result. The look-up table stores the code length as 1 from the code length of the code word.
Is output.

According to the twelfth aspect, the value of the shift input to the barrel shifter becomes small. In particular, when the longest code length is to be 2, the number of bits for representing the value of the shift input decreases, and the bit width of the shift input to the barrel shifter can be reduced. Further, there is no need to provide a circuit for converting the code length.

[0041]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 14 is a block diagram of a variable-length decoding circuit according to the embodiment. This variable length decoding circuit is described as decoding a variable length code having a maximum code length N of 16 bits.
The variable length decoding circuit of FIG.
And a decoding unit 120. The interface unit 110 includes a barrel shifter 111 and an input register 112
, An adder 114, and an accumulation register 115. The decoding unit 120 includes a barrel shifter 121, a barrel shifter register 122, and a lookup table (hereinafter, referred to as an LUT) 124.

FIG. 2 is an explanatory diagram showing an example of an input bit stream. Here, a1 and the like represent 1-bit data. For example, “a1-a8” is a1, a2, a3, a
It indicates that 8-bit data of 4, a5, a6, a7, and a8 are connected in this order. Also, 8-bit data “a1-a8”, 6-bit data “b1-b6”,
The 5-bit data “c1-c5” and the 15-bit data “d1-d15” are data “A”, “B”,
It is assumed that the codeword is a variable-length codeword corresponding to “C” and “D”. Similarly, 12-bit data “e1-e12”, 1
0-bit data “f1-f10”, 9-bit data “g”
1-g9 "and 16-bit data" h1-h16 "
It is assumed that these are variable-length codewords corresponding to data "E", "F", "G", and "H", respectively.

In the following, as shown in FIG.
A description will be given assuming that a bit stream in which variable-length code words having a maximum code length of 16 bits and corresponding to “H” are continuous is input. Also, for example, “a1-a8b1
-B6c1-c2 "means a1-a8, b1-
b6 and c1-c2 represent 16-bit data successively arranged.

In FIG. 1, a buffer 101 stores a bit stream and a carry signal C output from an adder 114.
R has been input. The input register 112 has a 16-bit configuration corresponding to the longest code length, and has a carry signal CR.
Is "1", the buffer 101 outputs 16
The input data of the bit is taken in the next cycle.

The buffer 101 stores the input bit stream, and when the carry signal CR is “1”,
In the next cycle, the stored bit stream is output to the barrel shifter 111 and the input register 112 in 16-bit units. Buffer 101 holds its output for one cycle.

The barrel shifter 111 has an accumulation register 1
The remainder RM (value: 0 to 15) output by 15 (indicating a possible value of the remainder RM, the same applies hereinafter) is input as a shift input value. The barrel shifter 111 adds a value obtained by adding 1 to the value of the shift input to the shift amount SH1 (value: 1 to 1).
6), and the output of the input register 112 is
Out of the 32-bit data obtained by concatenating the output of the buffer 101 as the lower 16 bits, (SH1 +
1) The 16-bit data of the (SH1 + 16) th bit is output to the barrel shifter 121. Here, the most significant bit of the 32-bit data obtained by concatenation is 1
It is a bit. Therefore, barrel shifter 111
Is a continuous bit length of 32 bits (2N
In this case, 16-bit (N-bit) data that is continuous from the (M + 2) -th bit is extracted and output from the (M) data in accordance with the value M of the shift input.

The barrel shifter register 122 can store 16-bit data corresponding to the longest code length, and outputs the stored data to the barrel shifter 121 and the LUT 124.

The LUT 124 is a barrel shifter register 1
22 is decoded, and the obtained decoding result D
C and outputs the code length C of the decoded codeword.
L (value: 1 to 16) is calculated by the barrel shifter 121 and the adder 1
14 is output. To the LUT 124, the first bit of the code word is input as the most significant bit. The LUT 124 is a table having a decoding result and a code length corresponding to each variable-length codeword. The input codeword and the codeword in the table are collated in order from the most significant bit, and there is a matching pattern. In this case, a decoding result DC and a code length CL corresponding to the code word are output. LU
T124 can be constituted by, for example, a ROM (read-only memory) or a logic circuit.

A code length CL (value: 1 to 16) output from the LUT 124 is input to the barrel shifter 121 as a shift input value. The barrel shifter 121 uses this shift input value as a shift amount SH2 (value: 1 to 16), and outputs 32-bit data obtained by concatenating the output of the barrel shifter register 122 as the upper 16 bits and the output of the barrel shifter 111 as the lower 16 bits. Of which, (SH2
16 from the (+1) th bit to the (SH2 + 16) th bit
Outputs bit data as a shift result. here,
The most significant bit of the 32-bit data obtained by concatenation is the first bit. Therefore, the barrel shifter 12
1 is a continuous bit length of 32 bits (2 bits
Of the (N bits) data, 16-bit (N bits) continuous data is extracted from the (L + 1) th bit and output according to the value L of the shift input. The barrel shifter 121 writes this shift result in the barrel shifter register 122.

The adder 114 adds the code length CL (value: 1 to 16) output from the LUT 124 and the remainder RM (value: 0 to 15) output from the accumulation register 115, and outputs an addition result SM. . The adder 114 outputs the carry signal CR of the addition result SM to the buffer 101 and the input register 112, and writes the remainder RM (value: 0 to 15) to the accumulation register 115.

The carry signal CR indicates that the addition result SM is 16 to
It is a signal that becomes 1 in the case of 31 (a quotient obtained by dividing the addition result SM by the longest code length of 16). The remainder RM is a remainder obtained by dividing the addition result SM by the longest code length 16 (the remainder obtained by modulating the longest code length 16 of the addition result SM). Therefore, the residual RM
Is equal to the remainder obtained by dividing the accumulated value of the code lengths of the decoded code words by the longest code length.

More specifically, a 5-bit addition result SM obtained by adding a code length CL represented by 5 bits and a remainder RM represented by 4 bits output from the accumulation register 115 is obtained. Of these, the most significant bit becomes the carry signal CR, and the remaining four bits become a new remainder RM modulo 16 of the addition result SM.

FIG. 3 is an explanatory diagram showing an example of a data flow for each cycle in the variable length decoding circuit of FIG. It is assumed that the input bit stream is continuous as shown in FIG.

In FIG. 3, in order to set data as an initial state in each register, initial conditions are set as follows. That is, the carry signal CR in the 0th to first cycles, the shift amount SH1 of the barrel shifter 111 in the 0th to 1st cycles, and the barrel shifter 12 in the 0th cycle.
The shift amount SH2 of “1” is “1” and “1”, respectively.
6 "and" 16 ". The buffer 101 performs the output in the 0th cycle, and the output of the accumulation register 115 is" 15 "in the 0th to 1st cycles. The data "x" indicates that it may be any data, and the data "x" will be described below with reference to FIG.
The operation of the variable length decoding circuit of FIG.

<0th cycle> The output of the buffer 101 is a1-a8b1-b6c1-c2 according to the initial condition. According to the value “16” of the shift amount SH1 of the barrel shifter 111 and the value “16” of the shift amount SH2 of the barrel shifter 121 in the initial condition, the output of the barrel shifter 111 is a1−
a8b1-b6c1-c2, and the barrel shifter 121
Are also a1-a8b1-b6c1-c2. The value of the carry signal CR is set to “1” from the initial condition.

<First Cycle> The input register 112 according to the value "1" of the carry signal CR in the 0th cycle.
Is the output a1-a8b1-b6c1-c of the buffer 101
2 and the output of the buffer 101 is c3-c5d1
−d13.

The barrel shifter register 122 outputs a1-a8b1-b6c1-c2 output from the barrel shifter 121.
Take in. According to the value “16” of the shift amount SH1 of the barrel shifter 111 which is the initial condition, the barrel shifter 111
Outputs c3-c5d1-d13. According to the output a1-a8b1-b6c1-c2 of the barrel shifter register 122, the decoding result of the LUT 124 becomes "A", and the LU
The code length CL output by T124 is "8". According to the value “8” of the code length CL, the barrel shifter 121 sets b1-
b6c1-c5d1-d5 are output.

According to the initial condition, the adder 114 has a code length C
The value “23” of the addition result SM of the value “8” of L and the output “15” of the accumulation register 115 is output. Carry signal CR
Is “1”, and the remainder RM is “7”.

<Second cycle> The input register 112 according to the value "1" of the carry signal CR in the first cycle.
Captures the output c3-c5d1-d13 of the buffer 101, and outputs d14-d15e1-e of the buffer 101.
12f1−f2.

The barrel shifter register 122 outputs b1-b6c1-c5d1-d5 output from the barrel shifter 121.
, And the accumulation register 115 captures the value “7” of the remainder RM. Shift amount SH of barrel shifter 111
According to the value “8” of 1, the barrel shifter 111 sets d6−d
15e1-e6 are output. Barrel shifter register 12
2 according to the output b1-b6c1-c5d1-d5.
The decoding result of the UT 124 is “B”, and the code length CL output by the LUT 124 is “6”. According to the value “6” of the code length CL, the barrel shifter 121 performs c1-c5d1
-D11 is output.

The adder 114 outputs a value “13” of the addition result SM between the value “6” of the code length CL and the output “7” of the accumulation register 115, the carry signal CR is “0”, and the remainder is RM
Becomes “13”.

<Third Cycle> In the third cycle, the second cycle
In accordance with the value “0” of the carry signal CR obtained in the cycle, the outputs of the input register 112 and the buffer 101 are not updated.

The barrel shifter register 122 takes in c1-c5d1-d11 output from the barrel shifter 121, and the accumulation register 115 takes in the value "13" of the remainder RM. The value “1” of the shift amount SH1 of the barrel shifter 111
According to 4 ", the barrel shifter 111 is d12-d15e.
1-e12 is output. According to the outputs c1-c5d1-d11 of the barrel shifter register 122, the decoding result of the LUT 124 is "C", and the code length CL output from the LUT 124 is "5".

According to the value “5” of the code length CL, the barrel shifter 121 outputs d1-d15e1. Adder 11
4 outputs a value "18" of the addition result SM of the value "5" of the code length CL and the output "13" of the accumulation register 115, the carry signal CR is "1", and the remainder is "2". Become.

In the next fourth cycle, the input register 112 sets d14-d15e1-e12f1-f2 according to the value "1" of the carry signal CR obtained in the third cycle.
And the output of the buffer 101 is f3-f10g1
−g8.

Thereafter, the variable length decoding circuit of FIG. 1 operates similarly to the second cycle and the third cycle. However, the buffer output and input registers are updated when the carry signal CR obtained in the previous cycle becomes “1”,
If it becomes "0", it is not updated.

As described above, after the first cycle, the result of variable length decoding can be output every cycle. In particular, at the start of decoding, the first decoded output is obtained in the first cycle one cycle after the 0th cycle in which the input buffer 101 outputs data first.

As described above, according to the first embodiment,
Compared with the conventional circuit of FIG. 11, the number of 16-bit input registers can be reduced from two to one, and a 48-bit input 16
32 bit input 1 instead of bit output barrel shifter
It is only necessary to provide a barrel shifter with a 6-bit output. Also, at the start of decoding, the number of cycles required from the time when the input buffer outputs data to the time when a decoded output is obtained is one cycle instead of two.

Although the conventional circuit of FIG. 11 requires two barrel shifter registers and a shift amount register, according to the first embodiment, if one barrel shifter register is provided instead of these registers. Often, the number of registers can be reduced.

(Modification of First Embodiment) FIG.
FIG. 21 is a block diagram of a variable-length decoding circuit according to a modification of the embodiment. The variable length decoding circuit in FIG. 4 includes a decoding unit 140 instead of the decoding unit 120 in the variable length decoding circuit in FIG. The decoding unit 140 includes the decoding unit 12
0, a barrel shifter 141 is provided instead of the barrel shifter 121. The decoding unit 140 receives the code length CL as an input, and outputs the converted value to the barrel shifter 141 instead of the code length CL.
46 is further provided. For other components,
The description is omitted because it is the same as that described with reference to FIG.

FIG. 5 is an explanatory diagram of the code length conversion circuit 146. The code length conversion circuit 146 includes the LUT 124
Is a code length CL represented by 5 bits (value: 1 to 1)
6) as an input and a value obtained by subtracting 1 from this (value: 0 to 1)
5). The code length conversion circuit 146
Specifically, it can be realized by a circuit for subtracting the value “1”, a ROM, or the like.

The barrel shifter 141 has a code length conversion circuit 1
A value (0 to 15) represented by 4 bits output from 46 is set as a shift input, a bit shift is performed with a value obtained by adding 1 to the value of the shift input as a shift amount, and a shift result is output. Accordingly, the barrel shifter 141 has a 16-bit (N-bit) continuous length starting from the (L + 2) -th bit in accordance with the value L of the shift input, out of the 32-bit (2N-bit) continuous data of the bit stream. Data will be fetched and output.

The barrel shifter 111 and the barrel shifter 141
Is a barrel shifter that can perform a 16-bit shift by using a 4-bit value as a shift input, and the same can be used. Therefore, FIG.
As compared with the circuit of the above, the regularity of the circuit is improved, and the circuit area can be reduced.

(Second Embodiment) FIG. 6 shows a second embodiment of the present invention.
FIG. 14 is a block diagram of a variable-length decoding circuit according to the embodiment. The variable length decoding circuit is described as decoding a variable length code having a maximum code length of 16 bits. The variable length decoding circuit of FIG.
A decoding unit 220. The decoding unit 220 includes a barrel shifter 221 and a first barrel shifter register 22.
2, the second barrel shifter register 223, and the LUT2
24, and a shift amount register 225. The buffer 101 and the interface unit 110 are the same as those described with reference to FIG.

The first barrel shift register 222 and the second barrel shift register 223 can store 16-bit data corresponding to the longest code length. The first barrel shifter register 222 stores 16-bit data output by the barrel shifter 111. The first barrel shifter register 222 and the second barrel shifter register 223 output the stored data to the barrel shifter 221.

The output (value: 1 to 16) of the shift amount register 225 is input to the barrel shifter 221 as a shift input value. The barrel shifter 221 uses the value of the shift input as the shift amount SH3 (value: 1 to 16), and outputs the output of the second barrel shifter register 223 to the upper one.
Of the 32-bit data obtained by concatenating the output of the first barrel shift register 222 as the lower 16 bits as 6 bits, (SH3 + 1) th to (SH3 + 16)
The 16-bit data up to the bit is output as a shift result. Here, the most significant bit of the 32-bit data obtained by concatenation is the first bit.

Therefore, the barrel shifter 221 has a continuous length of 32 bits (2N bits) of the bit stream.
(L + 1) in accordance with the value L of the shift input
16 bits (N bits) continuous from the first bit
Will be extracted and output. The barrel shifter 221 writes the shift result in the second barrel shifter register 223 and outputs the result to the LUT 224.

The LUT 224 decodes the output of the barrel shifter 221 and outputs the obtained decoding result DC. The code length CL of the decoded code word (value: 1 to 16)
Is written to the shift amount register 225 and output to the adder 114. The LUT 224 is a table having a decoding result and a code length corresponding to each variable-length code word. The LUT 224 is similar to the LUT 124 in FIG.

FIG. 7 is an explanatory diagram showing an example of a data flow for each cycle in the variable length decoding circuit of FIG. The input bit stream is the same as that described in the first embodiment, and is assumed to be continuous as shown in FIG.

In FIG. 7, initial conditions are set as follows in order to set data as an initial state in each register. That is, the carry signal CR of the 0th to 1st cycles, the shift amount SH1 of the barrel shifter 111 of the 0th to 1st cycles, and the barrel shifter 22 of the 1st cycle
The shift amount SH3 of “1” is “1” and “1”, respectively.
6 "and" 16 ". The buffer 101 performs the output in the 0th cycle, and the output of the accumulation register 115 in the 0th to 1st cycles is" 15 ". The operation of the variable length decoding circuit shown in FIG. 6 will be described.

<0th cycle> The output of the buffer 101 is a1-a8b1-b6c1-c2 according to the initial condition. The output of the barrel shifter 111 is a1 according to the value “16” of the shift amount SH1 of the barrel shifter 111 in the initial condition.
-A8b1-b6c1-c2. The value of the carry signal CR is set to “1” from the initial condition.

<First Cycle> According to the value "1" of the carry signal CR in the 0th cycle, the input register 112
Is the output a1-a8b1-b6c1-c of the buffer 101
2 and the output of the buffer 101 is c3-c5d1
−d13.

The first barrel shifter register 222 outputs a1-a8b1-b6c1 output from the barrel shifter 111.
-Import c2. Barrel shifter 111 as initial condition
The barrel shifter 111 outputs c3-c5d1-d13 according to the shift value SH1 of "16". The value “1” of the shift amount SH3 of the barrel shifter 221 which is the initial condition
6 ", the barrel shifter 221 has a1-a8 b1-
b6c1-c2 is output. According to the output a1-a8b1-b6c1-c2 of the barrel shifter 221, the LUT 22
4 is "A", and the code length CL output from the LUT 224 is "8".

According to the initial condition, the adder 114 has a code length C
The value “23” of the addition result SM of the value “8” of L and the output “15” of the accumulation register 115 is output. Carry signal CR
Is “1”, and the remainder RM is “7”.

<Second cycle> The input register 112 according to the value "1" of the carry signal CR in the first cycle
Captures the output c3-c5d1-d13 of the buffer 101, and outputs d14-d15e1-e of the buffer 101.
12f1−f2.

The first barrel shifter register 222 takes in c3-c5d1-d13 output from the barrel shifter 111, and the second barrel shifter register 223 outputs a1-a8b1-b6c1- output from the barrel shifter 221.
Capture c2. The shift amount register 225 has a code length CL
, And the accumulation register 115 stores the remainder RM
The value “7” is taken in.

According to the value “8” of the shift amount SH1 of the barrel shifter 111, the barrel shifter 111 sets d6−d15e.
1-e6 is output. According to the value “8” of the shift amount SH3 output from the shift amount register 225, the barrel shifter 2
21 outputs b1-b6c1-c5d1-d5. Outputs b1-b6c1-c5d1-d of barrel shifter 221
5, the decoding result of the LUT 224 becomes “B”,
The code length CL output from the LUT 224 is “6”.

The adder 114 outputs a value “13” of the addition result SM of the value “6” of the code length CL and the output “7” of the accumulation register 115, the carry signal CR is “0”, and the remainder is RM
Becomes “13”.

<Third cycle> In the third cycle, the second cycle
In accordance with the value “0” of the carry signal CR obtained in the cycle, the outputs of the input register 112 and the buffer 101 are not updated.

The first barrel shifter register 222 takes in d6-d15e1-e6 output from the barrel shifter 111, and the second barrel shifter register 223 outputs b1-b6c1-c5d1- output from the barrel shifter 221.
Capture d5. The shift amount register 225 has a code length CL
, And the accumulation register 115 stores the remainder RM
The value “13” is taken in.

In accordance with the value “14” of the shift amount SH1 of the barrel shifter 111, the barrel shifter 111 sets d12−d1.
5e1-e12 are output. According to the value “6” of the shift amount SH3 output from the shift amount register 225, the barrel shifter 221 outputs c1-c51-d11. According to the output c1-c5d1-d11 of the barrel shifter 221,
The decoding result of the LUT 224 is “C”, and the LUT 224
Is "5".

The adder 114 outputs a value “18” of the addition result SM between the value “5” of the code length CL and the output “13” of the accumulation register 115, the carry signal CR is “1”, and the remainder is R
M becomes "2".

In the next fourth cycle, the input register 112 sets d14-d15e1-e12f1-f2 according to the value "1" of the carry signal CR obtained in the third cycle.
And the output of the buffer 101 is f3-f10g1
−g8.

Thereafter, the variable length decoding circuit of FIG. 6 operates similarly to the second and third cycles. However, the buffer output and input registers are updated when the carry signal CR obtained in the previous cycle becomes “1”,
If it becomes "0", it is not updated.

Thus, after the first cycle, the result of variable length decoding can be output every cycle. In particular, at the start of decoding, the first decoded output is obtained in the first cycle one cycle after the 0th cycle in which the input buffer 101 outputs data first.

(Modification of Second Embodiment) FIG.
It is a block diagram of a variable length decoding circuit according to a modification of the embodiment. The variable length decoding circuit shown in FIG. 8 is different from the variable length decoding circuit shown in FIG.
40 is provided. The decoding unit 240
, A barrel shifter 241 is provided instead of the barrel shifter 221. The decoding unit 240 further includes a code length conversion circuit 146 that receives the code length CL and outputs a value obtained by converting the code length CL to the shift amount register 225 instead of the code length CL. The other components are the same as those described with reference to FIG. 6, and the code length conversion circuit 146 is the same as that described with reference to FIG.

The barrel shifter 241 has a code length conversion circuit 1
Reference numeral 46 designates a value (0 to 15) represented by 4 bits generated by converting the code length CL as a shift input, and performs a bit shift using a value obtained by adding 1 to the value of the shift input as a shift amount. Output the result. Therefore, the barrel shifter 241 has a continuous length of 16 bits (N bits) from the (L + 2) th bit in accordance with the value L of the shift input, out of the continuous length of 32 bits (2N bits) of the bit stream. Data will be fetched and output.

The barrel shifter 111 and the barrel shifter 241
Is a barrel shifter that can perform a 16-bit shift by using a 4-bit value as a shift input, and the same can be used. Therefore, FIG.
As compared with the circuit of the above, the regularity of the circuit is improved, and the circuit area can be reduced.

In the circuit of FIG. 8, the code length conversion circuit 1
Although the code length CL is output to 46 and the output of the code length conversion circuit 146 is given to the shift amount register 225, the code length conversion circuit 146 is provided between the shift amount register 225 and the barrel shifter 241. Is also good.

(Third Embodiment) FIG. 9 shows a third embodiment of the present invention.
FIG. 14 is a block diagram of a variable-length decoding circuit according to the embodiment. The variable length decoding circuit shown in FIG.
0 and a decoding unit 320. The interface unit 310 includes a barrel shifter 311 and an input register 31.
2, an adder 314, and an accumulation register 315. The decoding unit 320 includes a barrel shifter 321, a barrel shifter register 322, and an LUT 324.

The variable length decoding circuit shown in FIG. 9 differs from the variable length decoding circuit shown in FIG.
In this embodiment, an adder 314, a barrel shifter 321 and an LUT 324 are provided instead of the 1 and the LUT 124. The variable length decoding circuit in FIG. 9 calculates the actual code length (1 to 16) of the decoded code word by subtracting 1 from this (0 to 1).
There is a characteristic in that it is expressed in 5).

In FIG. 9, a buffer 101 stores a bit stream and a carry signal C output from an adder 314.
R has been input. The input register 312 has a 16-bit configuration corresponding to the longest code length, and has a carry signal CR.
Is "1", the buffer 101 outputs 16
The input data of the bit is taken in the next cycle.

The buffer 101 stores the input bit stream, and when the carry signal CR is “1”, in the next cycle, stores the stored bit stream in units of 16 bits in the barrel shifter 311 and the input register. 312. Buffer 101 holds its output for one cycle.

The barrel shifter 311 has an accumulation register 3
The remainder RM (values: 0 to 15) output by 15 is input as a shift input value. The barrel shifter 311 adds a value obtained by adding 1 to the value of the shift input to the shift amount SH4
(SH4 + 1) th to (SH4 + 16) bits of the 32-bit data obtained by concatenating the output of the input register 312 as the upper 16 bits and the output of the buffer 101 as the lower 16 bits. Is output to the barrel shifter 321. Here, the most significant bit of the 32-bit data obtained by concatenation is the first bit.

The barrel shifter register 322 can store 16-bit data corresponding to the longest code length, and outputs the stored data to the barrel shifter 321 and the LUT 324.

The LUT 324 is a barrel shifter register 3
22 is decoded, and the obtained decoding result D
In addition to outputting C, the number obtained by subtracting 1 from the actual code length of the decoded codeword is output to the barrel shifter 321 and the adder 314 as a code length CL (value: 0 to 15).
The LUT 324, for example, corresponds to each variable-length codeword.
It is a table having a number obtained by subtracting 1 from the decoding result and the code length. The LUT 324 differs from the LUT 124 of FIG. 1 in that it outputs a number obtained by subtracting 1 from the actual code length, and the other points are the same.

The code length CL (value: 0 to 15) output from the LUT 324 is input to the barrel shifter 321 as a shift input. The barrel shifter 321 adds a value obtained by adding 1 to the value of the shift input to the shift amount SH5 (value: 1 to 1).
6), the 16 bits of (SH5 + 1) th to (SH5 + 16) bits of the 32-bit data in which the output of the barrel shifter register 322 is linked to the upper 16 bits and the output of the barrel shifter 311 is linked to the lower 16 bits. Output data as shift result. Here, the most significant bit of the 32-bit data obtained by concatenation is the first bit. Barrel shifter 32
1 writes the shift result in the barrel shifter register 322.

The adder 314 adds the code length CL (value: 0 to 15) output from the LUT 324, the remainder RM (value: 0 to 15) output from the accumulation register 315, and a constant “1”. , And outputs the addition result SM. The adder 314 outputs the carry signal CR of the addition result SM to the buffer 101 and the input register 312, and outputs the remainder RM (value: 0 to 1).
5) is written to the accumulation register 315.

That is, the code length CL represented by 4 bits
And the remainder RM expressed by 4 bits, which is the output of the accumulation register 315, and 5 obtained by adding the constant "1"
Of the bit addition result SM, the most significant bit becomes the carry signal CR, and the remaining four bits become a new remainder RM modulo 16 of the addition result SM.

As described above, in the variable length decoding circuit of FIG. 9, the LUT 324 outputs a value obtained by subtracting 1 from the code length of the decoded code word as the code length. That is,
The code length C corresponding to the code words of code lengths “1” to “16”
The values of L are output as “0” to “15”, respectively. When a value (0 to 15) is input as the shift amount, the barrel shifter 321 adds 1 to this value (1 to 16).
Performs a shift of the number of bits of. Also, the adder 314
Adds the code length (0 to 15) output by the LUT 324, the output (0 to 15) of the accumulation register 315, and a constant “1”. Except for these points, the operation of the variable length decoding circuit in FIG. 9 is the same as that described with reference to FIG. 3 in the first embodiment, and a description thereof will not be repeated.

According to the variable length decoding circuit of FIG. 9 configured as described above, the barrel shifter 311 and the barrel shifter 3
Reference numeral 21 denotes a barrel shifter which can perform a 16-bit shift by using a 4-bit value (0 to 15) as a shift input, and the same can be used.
Therefore, the circuit area can be reduced by improving the regularity of the circuit. Also, unlike the circuit of FIG. 4, it is not necessary to provide the code length conversion circuit 146.

(Fourth Embodiment) FIG. 10 is a block diagram of a variable length decoding circuit according to a fourth embodiment of the present invention. The variable length decoding circuit shown in FIG.
10 and a decoding unit 420. Decoding section 42
0 is a barrel shifter 421, a first barrel shifter register 422, a second barrel shifter register 423,
An LUT 424 and a shift amount register 425 are provided. The buffer 101 and the interface unit 310 are the same as those described with reference to FIG.

The variable length decoding circuit shown in FIG. 10 is different from the variable length decoding circuit shown in FIG.
In this embodiment, an adder 314, a barrel shifter 421, and an LUT 424 are provided instead of the LUT 21 and the LUT 224.
The variable length decoding circuit shown in FIG. 10 is similar to the circuit shown in FIG. There is a feature.

The first barrel shift register 422 and the second barrel shift register 423 can store 16-bit data corresponding to the longest code length. The first barrel shifter register 422 stores 16-bit data output by the barrel shifter 311. The first barrel shifter register 422 and the second barrel shifter register 423 output the stored data to the barrel shifter 421.

The output (value: 0 to 15) of the shift amount register 425 is input to the barrel shifter 421 as a shift input value. The barrel shifter 421 adds a value obtained by adding 1 to the value of the shift input to the shift amount SH6 (value: 1 to 1).
32) in which the output of the second barrel shifter register 423 is connected as the upper 16 bits and the output of the first barrel shifter register 422 is connected as the lower 16 bits.
(SH6 + 1) th bit to (S
The 16-bit data up to the (H6 + 16) th bit is output as a shift result. Here, 32
The most significant bit of the bit data is the first bit. The barrel shifter 421 writes this shift result in the second barrel shifter register 423, and
424.

The LUT 424 decodes the output of the barrel shifter 421, outputs the obtained decoding result DC, and subtracts 1 from the actual code length of the decoded code word to obtain a code length CL ( The value is written to the shift amount register 425 as a value: 0 to 15) and output to the adder 314. The LUT 424 is similar to the LUT 324 in FIG.

As described above, in the variable length decoding circuit of FIG. 10, the LUT 424 outputs a value obtained by subtracting 1 from the code length of the decoded code word as the code length. That is,
The code length C corresponding to the code words of code lengths “1” to “16”
The values of L are output as “0” to “15”, respectively. When a value (0 to 15) is input as the shift amount, the barrel shifter 421 adds a value (1 to 1) to each value.
16) The number of bits is shifted. Adder 3
14 adds the code length (0 to 15) output from the LUT 424, the output (0 to 15) of the accumulation register 315, and a constant “1”. Except for these points, the operation of the variable length decoding circuit of FIG. 10 is the same as that described with reference to FIG. 7 in the second embodiment, and a description thereof will not be repeated.

According to the variable length decoding circuit of FIG. 10 configured as described above, each of the barrel shifter 311 and the barrel shifter 421 receives a 4-bit value (0 to 15) as a shift input, and performs 16 bit shifts. And the same thing can be used. Therefore, the circuit area can be reduced by improving the regularity of the circuit. Further, unlike the circuit of FIG. 8, it is not necessary to provide the code length conversion circuit 146.

In the first to fourth embodiments described above, each register width is assumed to be equal to the longest code length N for simplification of the description. However, the input register, as well as the second
Since the data output from the second barrel shifter register in the fourth embodiment is always shifted by one or more bits in the barrel shifter, the barrel shifter does not output the most significant bit of the data output from these registers. Therefore, these registers do not need the most significant bit, and the register width may be (N-1) bits. Then, the circuit scale can be further reduced, and the circuit area can be reduced. In this case, the barrel shifter
Data may be input to bits other than the most significant bit.

In the above embodiment, the longest code length is described as being 16. However, the longest code length may be another value. If the longest code length is not a power of 2, such as 16, a value of a power of 2 greater than or equal to the longest code length may be used as the temporary longest code length. At this time, the register widths of the input register and the barrel shift register need to correspond to the provisional maximum code length. Further, the adder may have a function of outputting a remainder with respect to the addition result modulo the longest code length. At this time, the register width of the accumulation register needs to be such that the remainder can be stored.

[0122]

As described above, according to the present invention,
In the variable length decoding circuit, the number of registers can be reduced, and the scale of the barrel shifter can be reduced. Therefore,
The size of the variable length decoding circuit can be reduced, and the layout area of the circuit can be reduced. Further, at the start of decoding, the number of cycles from when a bit stream is input to when a decoded output is first obtained can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a variable length decoding circuit according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram illustrating an example of an input bit stream.

FIG. 3 is an explanatory diagram showing an example of a data flow for each cycle in the variable length decoding circuit of FIG. 1;

FIG. 4 is a block diagram of a variable length decoding circuit according to a modification of the first embodiment.

FIG. 5 is an explanatory diagram of a code length conversion circuit.

FIG. 6 is a block diagram of a variable length decoding circuit according to a second embodiment of the present invention.

FIG. 7 is an explanatory diagram showing an example of a data flow for each cycle in the variable length decoding circuit of FIG. 6;

FIG. 8 is a block diagram of a variable length decoding circuit according to a modification of the second embodiment.

FIG. 9 is a block diagram of a variable length decoding circuit according to a third embodiment of the present invention.

FIG. 10 is a block diagram of a variable length decoding circuit according to a fourth embodiment of the present invention.

FIG. 11 is a block diagram of an example of a conventional variable length decoding circuit.

12 is an explanatory diagram showing an example of a data flow for each cycle in the variable length decoding circuit of FIG. 11;

[Explanation of symbols]

101 Buffer 110, 310 Interface unit 120, 140, 220, 240, 320, 420 Decoding unit 111, 121, 141, 221, 241, 311, 3
21,421 barrel shifter 112,312 input register 114,314 adder 115,315 accumulation register 122,322 barrel shifter register 124,224,324,424 look-up table (LUT) 146 code length conversion circuit 222,422 first barrel shifter Register 223, 423 Second barrel shifter register 225, 425 Shift amount register DC decoding result CL code length SM addition result CR carry signal RM remainder

Claims (12)

[Claims] 1. A variable length decoding circuit for sequentially decoding and outputting a bit stream in which variable length codewords are continuous, comprising: obtaining a cumulative value of the code lengths of the decoded codewords; An interface unit for extracting and outputting continuous N-bit data according to the cumulative value from data having a length of 2N or 2N-1 bits (where N is the longest code length of a variable-length code); , And decodes the codewords included in the input and the output of the interface unit input earlier than the input by using a look-up table, and outputs a decoding result. And a decoding unit that outputs the code length of the codeword obtained to the interface unit. 2. The variable length decoding circuit according to claim 1, wherein the interface unit stores and outputs a remainder obtained in accordance with the accumulated value, and an accumulation register for outputting the remainder. And the remainder output from the accumulation register to obtain an addition result corresponding to the accumulated value, and a quotient and remainder obtained by dividing the addition result by N as a carry signal and a new remainder, respectively. An adder that outputs, an input register that stores and outputs data of a continuous length N or N−1 bits of the bit stream when the value of the carry signal is 1, and an output of the input register. , And successive N bits of data of the bit stream are connected so that the order of each bit is the order in the bit stream, and the remainder output from the accumulation register is And a barrel shifter for extracting data of a continuous length of N bits from the bit corresponding to the value of the shift input out of the data obtained by concatenation, and outputting the data to the decoding unit. Variable length decoding circuit. 3. The variable length decoding circuit according to claim 2, wherein the barrel shifter counts (M +
2) A variable-length decoding circuit which outputs data having a continuous length of N bits from the bit (M is the value of the shift input). 4. The variable-length decoding circuit according to claim 1, wherein the decoding unit includes a barrel shifter, a barrel shifter register, and a look-up table, wherein the barrel shifter stores data output by the barrel shifter register. , And the data output by the interface unit are connected such that the order of each bit is the order in the bit stream, and the code length output by the look-up table is used as the value of the shift input, and the data is obtained by connection Among the data, N bits of continuous length data are extracted and output from bits corresponding to the value of the shift input, and the barrel shifter register stores and outputs the output of the barrel shifter. The look-up table corresponds to a codeword included in an output of the barrel shifter register Outputs the decoded result, the variable-length decoding circuit, characterized in that and outputs a code length of the code word. 5. The variable length decoding circuit according to claim 4, wherein the barrel shifter counts (L +
1) A variable length decoding circuit which outputs N-bit data having a continuous length from the first bit (L is the value of the shift input). 6. The variable length decoding circuit according to claim 4, wherein the decoding unit further includes a code length conversion circuit that subtracts 1 from the code length and outputs the result. Instead, using the output of the code length conversion circuit as the value of the shift input, counting from the first bit of the input data, (L +
2) A variable-length decoding circuit which outputs data having a length of N bits continuous from the first bit. 7. The variable length decoding circuit according to claim 1, wherein the decoding unit includes a barrel shifter, first and second barrel shifter registers, a look-up table, and a shift amount register, The barrel shifter connects the data output from the first and second barrel shifter registers so that the order of each bit is the order in the bit stream, and uses a value corresponding to the output of the shift amount register as a shift input value. Used for concatenating and extracting data of a continuous length of N bits from bits corresponding to the value of the shift input, and outputting the data. The first barrel shifter register includes: The second barrel shifter register stores the output of the barrel shifter and outputs the output. The look-up table outputs a decoding result corresponding to a codeword included in the output of the barrel shifter, and outputs a code length of the codeword. The shift amount register includes: A variable-length decoding circuit for storing and outputting a value corresponding to a code length. 8. The variable length decoding circuit according to claim 7, wherein the shift amount register stores and outputs the code length, and the barrel shifter shifts an output of the shift amount register. , And counting from the first bit of the input data, (L +
1) A variable length decoding circuit which outputs N-bit data having a continuous length from the first bit (L is the value of the shift input). 9. The variable length decoding circuit according to claim 7, wherein the decoding unit further includes a code length conversion circuit that subtracts 1 from the code length and outputs the code length, and wherein the barrel shifter includes the code length conversion. Using the code length obtained by subtracting 1 from the circuit and the shift amount register as the value of the shift input, counting from the first bit of the input data, (L +
2) A variable-length decoding circuit which outputs data having a length of N bits continuous from the first bit. 10. The variable length decoding circuit according to claim 1, wherein the interface unit stores and outputs a remainder obtained according to the accumulated value, and the decoding unit outputs And the remainder output from the accumulation register to obtain an addition result corresponding to the accumulated value, and a quotient and remainder obtained by dividing the addition result by N as a carry signal and a new remainder, respectively. An adder for outputting; an input register for storing and outputting data of a continuous length of N bits of the bit stream when the carry signal is 1; an output of the input register; Are connected so that the order of each bit is the order in the bit stream, and the remainder output from the accumulation register is used as the value of the shift input. And a barrel shifter for taking out data having a continuous length of N bits from the bit corresponding to the value of the shift input out of the data obtained by concatenation, and outputting the data to the decoding unit. The unit includes a barrel shifter, a barrel shifter register, and a look-up table. The barrel shifter of the decoding unit stores data output by the barrel shifter register and data output by the interface unit in each bit. Are connected in the order of the bit stream, the code length output from the look-up table is used as the value of the shift input, and the bits corresponding to the value of the shift input among the data obtained by the connection And outputs the data having a continuous length of N bits from the barrel shifter register. The lookup table stores and outputs the output of the barrel shifter of the decoding unit. A variable length decoding circuit for outputting. 11. The variable-length decoding circuit according to claim 1, wherein the interface unit stores and outputs a remainder obtained according to the accumulated value, and an output of the decoding unit. And the remainder output from the accumulation register to obtain an addition result corresponding to the accumulated value, and a quotient and remainder obtained by dividing the addition result by N as a carry signal and a new remainder, respectively. An adder for outputting; an input register for storing and outputting data of a continuous length of N bits of the bit stream when the carry signal is 1; an output of the input register; Are connected so that the order of each bit is the order in the bit stream, and the remainder output from the accumulation register is used as the value of the shift input. And a barrel shifter for taking out data having a continuous length of N bits from the bit corresponding to the value of the shift input out of the data obtained by concatenation and outputting the data to the decoding unit. The unit includes a barrel shifter, first and second barrel shifter registers, a look-up table, and a shift amount register. The barrel shifter of the decoding unit is configured such that the first and second barrel shifter registers are Data to be output is concatenated so that the order of each bit is the order in the bit stream, and a value corresponding to the output of the shift amount register is used as a value of the shift input. The first barrel shifter register for extracting and outputting continuous N-bit data from bits corresponding to the value of the shift input; Stores and outputs data output by the interface unit; the second barrel shifter register stores and outputs the output of the barrel shifter of the decoding unit; Outputting the decoding result corresponding to the code word included in the output of the barrel shifter of the decoding unit, and outputting the code length of the code word. The shift amount register has a value corresponding to the code length. And outputs the result. 12. The variable length decoding circuit according to claim 10, wherein the adder is configured to add 1 to a value obtained by adding a code length output by the decoding unit and a remainder output by the accumulation register. The lookup table outputs a value obtained by subtracting 1 from the code length of the code word, as the code length. Decoding circuit.