JP2001339052A - Method of simulating protective circuit against electrostatic destruction - Google Patents

Abstract

PROBLEM TO BE SOLVED: To replace a protective circuit against ESD with a more accurate equivalent circuit and also to analyze the entire resistance to ESD of a protective circuit against ESD quickly and accurately, concerning a simulation method for a protective circuit against electrostatic breakdown. SOLUTION: A protective circuit against electrostatic breakdown composed of an insulated gate field effect transistor is replaced with an equivalent circuit using a bipolar transistor, a current flowing at least from a collector to a substrate between a current flowing from the collector to the substrate and a current flowing from an emitter to a substrate is expressed by two current sources, and the protective resistance to electrostatic breakdown is simulated by circuit simulation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for simulating an electrostatic discharge protection circuit, and more particularly, to a method for electrostatic discharge (ES) of a semiconductor memory device or a semiconductor logic circuit device.
D: Electrostatic Discharge
The present invention relates to a method for simulating an electrostatic discharge protection circuit having an equivalent circuit configuration when simulating the ESD resistance of a protection circuit for protecting from e) using a circuit simulator.

[0002]

2. Description of the Related Art With the recent miniaturization of semiconductor devices constituting a semiconductor integrated circuit device, static electricity generated by external friction and the like cannot be ignored, and an electrostatic discharge protection element (ESD protection element). Area is reduced, and ES
Since it is becoming difficult to secure D resistance, higher performance of the ESD protection circuit is required.

However, even if the ESD protection circuit is designed, if the process conditions are changed, the procedure of measuring the ESD resistance and redesigning the ESD protection circuit is the time required for semiconductor integrated circuit device development (TAT: Turn A
Therefore, it is important to evaluate the ESD resistance by simulation in advance because a large loss is caused in the round time. Since it is known that such ESD resistance depends on wiring resistance and layout, E
To improve the SD tolerance, a layout change at the design stage is more realistic than a process change.

[0004] Destruction phenomena due to electrostatic discharge are classified into several models, and models such as a human body charging model (HBM), a mechanical model (MM), a device charging model (CDM), and a package charging model (CPM) are available. Yes, ESD
The response characteristics of a MOSFET (metal-insulator-semiconductor field effect transistor) constituting a protection element, that is, an IGFET (insulated gate type field effect transistor) is determined by a characteristic called snapback characteristic.

[0005] In this case, Yohi the ESD tolerance is largely dependent on the snapback characteristics, large inclination angle in the snapback characteristics, and, ESD tolerance is higher that about snapback voltage V _sb is low. This is because even if the same current flows through the ESD element due to the application of a surge, the power is reduced, and the amount of heat generated by the power is reduced, so that the thermal destruction resistance is increased. IEICE Technical Report, VLD98-95, ED98
−120, SDM98-156, ICD98-226,
pp. 67-72, 1998-10).

Conventionally, when simulating such ESD resistance, for example, an MO having a gate width of several hundred μm is used.
A part of the ESD protection circuit composed of SFET etc.
A device simulation is performed using a device simulator such as LAPS, or an equivalent circuit is created from structural data of a layout diagram and a sectional structure diagram of an ESD protection circuit, and the circuit is simulated, thereby obtaining stored energy to obtain ESD resistance. I was evaluating.

Among them, the former method using device simulation has a drawback that the number of transistors that can be analyzed is limited and that much time is required for calculation.

On the other hand, the latter method using circuit simulation has the merit that layout data can be incorporated and the calculation time is as short as several minutes. Also, the present calculation method can be directly applied to a bulk layout in which MOSFETs are regularly arranged. Note that an irregular layout or SOI (S
An equivalent circuit model needs to be considered for the case of an icon-on-insulator element.

Here, an example of a method of simulating an ESD protection element using a conventional circuit simulator SPICE will be described with reference to FIG.
vaka Duvury et. al. , IRPS,
pp. 318-326, 1996). FIG. 20A is a diagram showing an equivalent circuit of one MOSFET constituting a conventional ESD protection circuit. The entire ESD protection element includes a MOSFET, a lateral bipolar transistor, a substrate resistance R _sub , and a current. Replaced by power supply _Igen . The operation of the ESD protection element in this case is based on MOSFET
A voltage of 0 V is applied to the source S, and a voltage is applied to the gate G. When a voltage is applied to the drain D, an impact ionization current I _gen flows from the drain D to the substrate, and this impact ionization current I _gen is represented as a current power supply. . In the figure, I _ds is the current flowing under the gate, I _d is the drain current, I _S is the source current, I _sub is the substrate current,
_c is a collector current, _Ib is a base current, _Ie is an emitter current, and _Vb is a base voltage. Although not shown, the drain D is connected to a pad (pad), and this pad is a person or a machine. And so on.

Here, when an electrostatic voltage, that is, a drain voltage is applied, electrons flowing from the source S toward the drain D are ion-impacted by a strong electric field in a depletion layer extending to an interface between the drain D and the substrate. Avalanche occurs, and an impact ionization current _Igen flows from the drain D equivalently acting as a collector toward the substrate equivalently equivalently acting as a base. In addition,
When the bipolar transistor is not turned on, I _gen = I _sub .

As the drain voltage is increased, I _gen
(= I _sub) cause voltage drop V _b by the flows in the substrate resistance R _sub, a substrate made of an equivalently base by the voltage drop V _b, the source S to be equivalent to the emitter
Bipolar transistor turns on, electrons from the emitter are injected into the base part is a collector current I _c flowing into the collector by the junction between is forward biased with. In this case, the efficiency of the parasitic bipolar transistor depends on the emitter injection efficiency γ and the arrival rate α _T depending on the effective channel length L _eff of the MOSFET.

[0012] Figure 20 (b) see FIG. 20 (b), I _D -V _D of such ESD protection elements
Shows the characteristic, if the electrostatic voltage applied to the further drain D rises, although depending on the gate voltage V _g, the drain voltage V _D is decreased, the snapback characteristic in I _D -V _D characteristic It is shown to appear.

[0013]

However, Charva
In the conventional circuit simulation method by Ka et al., only the impact ionization current I _gen due to ion impact is considered as the current power source, so that the ESD withstand voltage is largely estimated, and the operation of the ESD element cannot be correctly represented. There's a problem.

That is, when a voltage is applied to the drain D,
The current flowing from the drain D to the substrate is the impact ionization current I due to the strong electric field in the depletion layer near the drain D.
_In addition to _gen, there is a current flowing by a thermally generated electron-hole pair in the depletion layer near the drain D,
In the conventional circuit simulation method by Charvaka et al., There is a problem that the current flowing due to the electron-hole pairs thermally generated in the depletion layer is not considered.

Further, in the above-described conventional circuit simulation method, since only the operation characteristics of the ESD protection element itself are simulated, there is also a problem that accurate analysis of the ESD resistance of the entire ESD protection circuit cannot be performed. is there.

Accordingly, an object of the present invention is to replace the ESD protection element with a more accurate equivalent circuit and to quickly and accurately analyze the ESD resistance of the entire ESD protection circuit.

[0017]

FIG. 1 is an explanatory view of the principle configuration of the present invention. Referring to FIG. 1, means for solving the problems in the present invention will be described. See FIG. 1 (1) In the present invention, in a method for simulating an electrostatic discharge protection circuit, an electrostatic discharge protection element constituted by an insulated gate field effect transistor is replaced with an equivalent circuit using a bipolar transistor, and a collector is replaced by a substrate. The current flowing from the emitter to the substrate and the current flowing from the collector to the substrate are represented by two current power sources, and the circuit is simulated for electrostatic breakdown protection resistance.

Since snapback characteristics are used to protect against electrostatic damage, an electrostatic discharge protection element (ESD protection element) composed of an insulated gate field effect transistor (IGFET) is replaced with a bipolar transistor. That is, the snapback characteristic can be reproduced by replacing the equivalent circuit using a parasitic lateral bipolar transistor. In particular, as a current power source, at least a current flowing from the collector to the substrate and a current flowing from the emitter to the substrate out of the current flowing from the collector to the substrate are two current power sources, that is, a current power source _Imc due to impact ionization current, and a depletion layer. By expressing the current power supply I _pnc based on a current based on thermally generated electron-hole pairs, the ESD resistance can be accurately evaluated without overestimating.

(2) Further, according to the present invention, in the method for simulating an electrostatic discharge protection circuit, an electrostatic discharge protection element constituted by an insulated gate type field effect transistor comprises a bipolar transistor and an insulated gate type field effect transistor. The circuit is simulated by expressing the current flowing from the drain to the substrate and the current flowing from the source to the substrate at least out of the current flowing from the drain to the substrate by using two current power supplies, replacing the equivalent circuit used. And

As described above, by replacing the electrostatic discharge protection element constituted by the insulated gate type field effect transistor with an equivalent circuit using the bipolar transistor and the insulated gate type field effect transistor, the equivalent circuit can be more accurately formed. This makes it possible to substitute, and it becomes possible to estimate more accurate ESD resistance.

(3) Further, according to the present invention, in the above (1) or (2), inputting layout data of the entire electrostatic discharge protection circuit from computer-aided design layout data to generate input data of a circuit simulator. Features.

As described above, when a simulation is performed using a circuit simulator such as HSPICE, the layout data of the entire ESD protection circuit can be directly fetched from computer-aided design (CAD) layout data. By taking in the CAD layout data as input data, it becomes possible to analyze the ESD resistance of the entire ESD protection circuit accurately and quickly.

(4) The invention according to any one of (1) to (3) above, wherein the current due to the impact ionization current of the two current power supplies representing the current flowing from the collector or drain of the equivalent circuit to the substrate. When the multiplication coefficient m for representing the power supply is extracted, the substrate voltage dependence of the current flowing from the substrate to the emitter or drain is taken into account.

As described above, when extracting the multiplication coefficient m for representing the current power supply _Imc based on the impact ionization current,
By incorporating the substrate voltage V _sub dependence of current I _h flowing from the substrate to the emitter or drain, low drain voltage V _d source voltage in the region V _s, i.e., increasing no physical contradiction does not depend on the emitter voltage V _e The multiplication factor m can be obtained.

(5) According to the present invention, in the above (4), when the multiplication coefficient m for representing the current power supply by the impact ionization current is extracted, the collector current or the drain when the impact ionization phenomenon is not taken in The current is represented by a difference between an emitter current or a source current and a current flowing from the substrate to the emitter or the drain.

As described above, when the impact ionization phenomenon is not taken, the collector current I _c , ie, I _d , is _{calculated by calculating} the difference between the emitter current I _e , ie, I _sii, and the current I _h flowing from the substrate to the emitter or drain. That is, by expressing by I _d = I _sii −I _h , the collector current I _c when the impact ionization phenomenon is not taken, that is, I _d can be replaced by using the actual measurement data I _sii , so that And accurate simulation is possible.

When extracting the multiplication coefficient m for representing the current power supply based on the impact ionization current, it is desirable to reflect the source voltage dependency. That is, in the drain voltage V _d is large to some extent region, multiplication factor m
Has a source voltage V _s dependency, so that a more accurate simulation can be performed by reflecting such a source voltage V _s dependency.

When generating the input data of the circuit simulator using the multiplication coefficient m reflecting the source voltage dependence, it is desirable to incorporate a weight function into the input data. By tabulating the multiplication coefficient m obtained by the device simulator and incorporating a weight function into the input data, the input data of the circuit simulator can be generated more accurately.

It is desirable that the base resistance of the equivalent circuit reflects a change in resistance due to majority carriers generated by minority carriers injected from the source or drain into the substrate. If the number of minority carriers injected from the source or the drain exceeds a certain number, the base resistance fluctuates due to the generation of majority carriers to maintain charge neutrality. Simulation becomes possible.

Further, the base resistance of the equivalent circuit includes a resistance component due to majority carriers generated by impurities determining conductivity type, a resistance component due to majority carriers generated due to minority carriers injected from a source to a substrate, and a resistance component due to a drain. It is desirable that the resistance component is represented by a parallel circuit of three resistance components of a resistance component due to majority carriers generated due to minority carriers injected into the substrate. When more than a small number of minority carriers are injected into the substrate, majority carriers are generated to maintain charge neutrality.Thus, by expressing such a parallel circuit of three resistance components, the fluctuation of the base resistance can be accurately determined. Can be reflected.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A simulation method according to a first embodiment of the present invention will now be described with reference to FIGS. FIG. 2 is a diagram showing an equivalent circuit on the protection element side in which the ESD protection element composed of a MOSFET is replaced with a lateral bipolar transistor, and an equivalent circuit on the external side such as a human body or a machine serving as a static electricity source. The equivalent circuit on the protection element side and the equivalent circuit on the external side are connected via a pad (Pad). In the figure, current power sources I _me and I _pne and a junction capacitance C _pne are provided on the emitter side in consideration of symmetry.

In this case, parameters such as I _pn , I _m , and C _pn are extracted by using a device simulator (FLAPS), and this state will be described with reference to FIG. FIG. 3 is a model structure diagram created by using a device simulator (FLAPS). An n-channel type MOSFET constituting an ESD protection element has an n-type source region 13 as an emitter, a p-type substrate 11 and a base. , An npn-type lateral bipolar transistor having the n-type drain region 12 as a collector and no gate electrode. In this case, the p-type substrate 11 corresponds to a p-type well region in the equivalent circuit of FIG.

The collector current I _pnc based on the electron-hole pair thermally generated in the depletion layer near the n-type drain region 12 is such that the emitter voltage V _e and the base voltage V _b are 0 V
And then, as the collector voltage V _c, represents the collector current obtained by applying a voltage of 0～8V, the collector current I _pnc is to input data circuit simulator (HSPICE) as a first current source.

On the other hand, the core based on the impact ionization current
Lector current I_mcIs the emitter voltage V _eTo -0.7V
And the base voltage V_bTo 0V and the collector voltage V_cage
And by applying a voltage of 0 to 8 V
Collector current I without pact ionization_cIn
The product multiplied by the multiplication factor m associated with pact ionization, that is, I_mc= I_c× m and the collector current I_mcAs the second current power supply
Input data of circuit simulator (HSPICE)
You. In this case, the multiplication coefficient m is the impact ion
The collector current when_{I c}Where m = I_{I c}/ I_cRepresented by -1.

Further, the junction capacitance C _pn with the source-drain region is determined using the voltage conditions at the time of seeking I _pn (I _pnc), with V _c is negative, and the value abruptly In the vicinity of the change, the capacitance value is set in the device simulator (FLAP
Since S) in not required, Vc <0.98 V below the junction capacitance C _pn uses extrapolated value.

Next, a circuit simulator (HSPICE)
In order to obtain the bipolar parameters used in the above, V _c = 2 V, using a device simulator (FLAPS)
Under the condition of V _e = 0V, and applying a voltage of 0 to-1.5V as V _b, determine the characteristic curve of V _b -I _c characteristic curve and V _b -I _b.

Next, a circuit simulator (HSPICE)
The bipolar parameters I _{be (eff)} and I _b / I _c = BF (amplification factor) are extracted using the DC model formula used in the above. By the way, when V _be = 0.7V,
Ibe _(eff) = 2.3e ^-1 A and BF = 0.9.

Also, since the n-type source region 13 and the n-type drain region 12 are usually symmetric, the equivalent emitter and collector are also symmetrical, so that I _{be (eff)} = I _{be (eff)} BF = BR = I _b / I _e , but in the device simulator (FLAPS) and the circuit simulator (HSPICE), the base voltage V
_{Since a} large difference occurs in the calculated value as _b becomes a large value, the base resistance _Rb is considered as in the equivalent circuit of FIG. Incidentally, V _be = 1.0 V, I _b = 2.1211
In the case of × 10 ⁻⁴ A, R _b = 98Ω.

Again referring to FIG. 2, the ESD resistance is calculated by a circuit simulator (HSPICE) using the above bipolar parameters.
Electrostatic breakdown model of an external circuit in this case is the HBM model similar to TI model, the power supply voltage V _cc = 4000V, capacitance C ₁ = 100 pF, resistor R ₁ = 1500 ohms, the inductance L ₁ = 7.5μH, capacitance C ₂ and C ₃ to 0 pF. At this time, the resistance values R _cm1 and R
_em2 is set to 0.3Ω, the well resistance R _well corresponding to the substrate resistance is set to 10,000Ω, and the base resistance R _well is set to 10,000Ω.
_b is 0.49Ω. The well resistance R _well
Depends greatly on the process and layout, but here, the depth W of the bipolar transistor is set to 200 μm.

FIG. 4 is a graph showing I _c -V _c characteristics obtained as a result of calculation by inputting the bipolar parameters extracted as described above to a circuit simulator (HSPICE). It is understood that the snapback characteristic is exhibited in FIG.

As described above, in the first embodiment of the present invention, a circuit simulator is used, and at least the collector-side current power supply is thermally connected to the current power supply _Imc by two impact ionization currents. Since the calculation is performed assuming two current power supplies, that is, a current power supply based on the current I _pnc (= I _gen ) based on the excited electron-hole pairs, it is necessary to accurately analyze the ESD resistance without overestimating it. Can be.

Since the circuit simulator is used for the analysis, the analysis can be performed in a short time, and the time required for designing and evaluating a new ESD protection circuit (TA
T) can be significantly reduced. Note that a device simulator is used for extracting bipolar parameters in advance.

Next, a simulation method according to the second embodiment of the present invention, in which a MOSFET is incorporated in an equivalent circuit, will be briefly described with reference to FIGS. FIG. 5 is a diagram showing an equivalent circuit on the protection element side in which an ESD protection element composed of a MOSFET is replaced with a lateral bipolar transistor and a MOSFET, and an equivalent circuit on the external side such as a human body or a machine serving as a static electricity source. And a MOSFET between the collector and the emitter of the lateral bipolar transistor in the first embodiment shown in FIG.
Is connected to the drain and source of the semiconductor device. In this case, too, the current power supplies I _me and I _me
pne and a junction capacitance C _pne are provided.

The simulation method in this case is based on the operating characteristics of the bipolar transistor and the normal MOSFET.
Are separately calculated, and the calculation results are superimposed to analyze the ESD resistance. The respective operating characteristics in this case are obtained by distributing the current flowing due to the electrostatic voltage applied from the pad to the collector current flowing through the bipolar transistor and the drain current flowing through the MOSFET. The characteristics are analyzed in the same manner as the operation characteristics of the bipolar transistor described in the first embodiment on the basis of the distributed collector current, while the operation characteristics of the MOSFET are distributed. The operation characteristics are analyzed based on the drain current.

FIG. 6 is an I _d -V _d characteristic diagram obtained as a result of calculation by incorporating a MOSFET into an equivalent circuit and inputting it to a circuit simulator (HSPICE) as described above. Thus, it is understood that a snapback characteristic similar to that of FIG. 4 is obtained. In this case, the drain current I
_d represents not the drain current of the MOSFET on the equivalent circuit, but the current obtained by adding the drain current of the MOSFET on the equivalent circuit and the collector current of the bipolar transistor on the equivalent circuit.

As described above, in the second embodiment of the present invention, since the MOSFET constituting the ESD protection element is analyzed by being incorporated in the equivalent circuit, the equivalent circuit reflecting the substance more accurately is analyzed. As a result, more accurate analysis of ESD resistance becomes possible.

Next, a simulation method according to a third embodiment of the present invention will be described with reference to FIGS. FIG. 7 is an equivalent circuit diagram in the case where 24 ESD protection circuits are arranged in 4 rows × 6 columns by 24 n-channel MOSFETs 21. Each ESD protection element is included in the ESD protection circuit. The MOSFET 21 can be replaced by a MOSFET 21 and a lateral bipolar transistor, which is a parasitic element 22, as in the second embodiment. Note that the layout data of the ESD protection circuit is obtained from CAD layout data, and the input data of the components on the external circuit side is the power supply voltage V _cc , as in the first embodiment. =
4000 V, capacitance C ₁ = 100 pF, resistance R ₁ = 150
0Ω, inductance L ₁ = 7.5 μH, capacitances C ₂ and C ₃ are 0 pF.

FIG. 8 shows an example of the layout of such an ESD protection circuit.
This is schematically shown, and six MOSFETs in one row
It is composed of 24 MOSFETs arranged in 4 rows.
The MOSFETs in the leftmost column are arranged in the
Tr_Three, Tr_Four, Tr_Five, Tr₆And the MOS in the next column
FET to Tr₇, Tr₈, Tr₉, Tr _TenAnd Tr₂₆
Up to.

In this case, for example, the adjacent gate length L _g
= 0.24 μm, the source region 33 and the drain region 34 arranged between the gate electrodes 31 have a length L = 4.96 μm.
m are shared, and each source / drain region 33, 34 has a length L _d = L / 2 =
A rectangular region (area = 48.7568 μm ² ) having a width of 2.48 μm and a width W _{g of} 19.66 μm is set. It should be noted that the source / drain regions 32 made of diffusion regions not shared on both the left and right sides.
Is 4.21 μm.

On the other hand, the sheet resistance of the gate electrode 31 and the sheet resistance of the wiring layer are 5 Ω / □ and 0.0, respectively.
Assuming 5Ω / □, the gate resistance R _g is determined by setting the gate length to L _g
(= 0.24 μm), R _g = 410 Ω / 20 μm by setting R _g = (5Ω / □) × (L _g / W _g ). The wiring resistance R is represented by R = (0.05Ω / □) × (W _g / L _w ) where the wiring layer width is L _w . Here, the dependence of the operating characteristics on the wiring resistance is shown. In order to check the resistance, two kinds of resistance values of 0.1Ω and 1.0Ω were used as input data.

FIG. 9A shows I _d when the wiring resistance R is 0.1Ω.
A -V _d characteristic diagram, FIG. 9 (b), the wiring resistance R
Which is the I _d -V _d characteristic diagram in the case of a 1.0 [Omega]. As is clear from the figure, there is a difference in the snapback characteristics, and it is understood that the peak voltage of the snapback increases as the wiring resistance R increases.

FIG. 10A is a diagram showing the correlation between the time t and the power consumption P when the wiring resistance R is 0.1 Ω.
(B) is a diagram showing the correlation between the time t and the power consumption P when the wiring resistance R is 1.0Ω. As is clear from the figure, it is understood that the power consumption P increases as the wiring resistance R increases, and the power consumption P increases as the distance from the pad decreases, that is, the left column in the layout of FIG. In the case of Tr, P (Tr ₃ )> P (T
It is understood that r ₄ )> P (Tr ₅ )> P (Tr ₆ ), and this tendency becomes remarkable as the wiring resistance R increases.

Therefore, by performing such an analysis, it is understood that the larger the wiring resistance R and the closer to the input pad, the higher the power consumption of the protection MOSFET, and thus the more easily the MOSFET is thermally damaged. By using this result, the layout can be optimized.

As described above, in the third embodiment of the present invention, the configuration of the entire ESD protection circuit is CA
Since the D layout data is incorporated into the netlist and simulated by a circuit simulator,
The ESD withstand voltage characteristics of the entire SD protection circuit can be quickly and accurately simulated.

The individual Es constituting the ESD protection circuit
Since differences in characteristics depending on the layout position of the SD protection element and differences in the resistance value of the wiring layers can be evaluated, not only the element structure of each ESD protection element but also the layout of the entire ESD protection circuit can be optimized. Become.

Next, the first embodiment or the second embodiment will be described.
A fourth embodiment related to the improvement of the fourth embodiment will be described. In the first embodiment, the current source I _mc flowing from the vicinity of the collector to the substrate due to the impact ionization phenomenon.
It is given a numerical value table as a relationship between the multiplication factor m and the collector voltage V _c caused by impact ionization.

The multiplication coefficient m in this case is as follows: when the collector current when there is impact ionization is I _ic and when the collector current when there is no impact ionization is I _c , m = (I _ic −I _c ) / I _c It is represented by _{C = I ic / I C -1} .

Here, the notation of current and voltage is expressed as I _ic → I
_dii , I _c → I _d , V _c → V _d, etc., but they are substantially equivalent. Thus, the expression relates to the multiplication coefficient of the m, m = is represented by _{(I dii -I d) / I} d, circuit simulator this relationship (HSPIC
FIG. 11 shows the result calculated in E).

Referring to FIG. 11, as is apparent from FIG. 11, in the case of an n-channel MOSFET having a gate width W of 1.0 μm, the source voltage V is set to −0.
When a 4V to-0.7 V, the source voltage V _s dependence was not observed in the multiplication factor m, substantially linear relation is obtained with respect to the drain voltage V _d.

In order to evaluate such a simulation result, it is necessary to compare with the experimental data. However, the drain current I _{d in the} case where the impact ionization phenomenon in the above-mentioned expression relating to the multiplication coefficient m is not taken in is taken as experimental data. It is impossible to determine, and therefore, the equation for the multiplication factor m cannot be immediately associated with experimental data. That, in fact, since the varying degrees occurs always impact ionization any, is because it is impossible to actually measure the drain current I _d in the case where there is no impact ionization.

Therefore, when the parameters of such a parasitic element are obtained, the source current I in the case where the impact ionization phenomenon obtained as experimental data has occurred is obtained.
The _sii used in place of the drain current I _d in the case where there is no impact ionization was determined _{m = (I dii -I sii)} / I relationship between multiplication coefficient m and the drain voltage V _d as _sii FIG. 12 shows the results.

[0062] As shown in Figure 12 reference figures, the multiplication factor m in this case, the source voltage V _s dependence appears even at a drain voltage V _d is lower region, the multiplication factor m is physically There is a problem of unreasonable parameters. That is, multiplication factor m by impact ionization, will depend on the drain voltage V _d because it depends on the electric field near the drain, the value of the current (≒ I _sii) reaching the vicinity of the drain in the constant independently and should there, the source voltage V _s even though only be reflected in the value of the current that reaches the vicinity of the drain, it becomes unreasonable multiplication factor m has a source voltage V _s dependence.

Therefore, in the case of an n-channel MOSFET, the actual source current, that is, the source current I _sii when the impact ionization phenomenon occurs, is equal to the electron current I _sii ′ flowing from the source region to the drain region and the substrate current. it consists of a hole current I _h flowing through the source region from, i.e., I _sii = I _sii '+ focuses on the fact is I _h, a result of intensive studies, the equation for the multiplication coefficient of the m m = (I _dii I _d in -I _d) / I _d is the I _sii rather was concluded that correspond to I _sii '.

[0064] Thus, equation relates the multiplication factor _{m, m = (I dii -I} sii ') / I sii' = (I dii -I sii + I h) / can be expressed by (I _sii -I _h) become. The hole current Ih flowing from the substrate to the source region in this equation is _calculated by the circuit simulator (HS
(PICE) using a bipolar model and fitting parameters.

FIG. 13 shows the substrate voltage V_subThat is, V_bTo V_b= 0V
And the drain voltage V _dThat is, the collector voltage V_c1
V or lower constant voltage, for example, V_c= 0.05V and saw
Voltage V_sThat is, the emitter voltage V_eFluctuating the substrate
Current I flowing from the source region to the source region_hThat is, the base
Style I_bWas evaluated.

The I obtained as described above_hAnd experimental data I_siiTo
Multiplication coefficient m and drain voltage V _dTwo dimensional relationship
Determined using a device simulator (Medici)
FIG. 14 shows the result. As shown in FIG. 14, the drain voltage V_DIn low areas
The source voltage V_sDependencies emerge
Without physical irrationality,
Moreover, the simulation result shown in FIG.
No results were obtained.

Therefore, in the calculation of the multiplication coefficient m accompanying impact ionization, I _d is obtained by considering the relationship of I _sii = I _sii ′ + I _h , that is, the hole current I _h flowing from the substrate to the source region. Since the actual measurement data I _sii can be used instead of being obtained by calculation, it is possible to more accurately and quickly simulate the ESD resistance.

As described above, the snapback characteristic is changed by the circuit simulator (HSPI) by the multiplication coefficient m having no source voltage dependency, that is, the multiplication coefficient m when V _s = 0 V.
CE), and will be described with reference to FIG. See FIG. 15. In FIG. 15, a curve shown by a broken line is a multiplication coefficient m (V _s =
0V). However, a difference is seen from the snapback characteristic curve obtained by using a device simulator (Medici) indicated only by a black circle in the figure.

This is because, as shown in FIG.
In the drain voltage V _d is large to some extent region, it is considered the result of ignoring the source voltage V _s dependence appears in the multiplication factor m. That is, when measuring the snapback characteristics, the source is grounded, but will be current driven, in particular, in a situation where the snap back occurs, the source potential V _s varies by the current not fixed in order to reproduce a more accurate snapback characteristic in the circuit simulator, it is necessary to drain voltage V _d is to reflect the source voltage V _s dependence of the multiplication factor m in the region somewhat large.

Therefore, a fifth embodiment related to the improvement of the fourth embodiment will be described. In this fifth embodiment, when simulating the snapback characteristic using a circuit simulator (HSPICE), the multiplication factor m for each predetermined source voltage V _s obtained by the two-dimensional device simulator (Medici) Numerical data is tabulated, and for the multiplication coefficient m at the source voltage V _s not simulated, the tabulated numerical data is weighted and used. The weighting depends on the system in the circuit simulator used, and the way of weighting is appropriately changed so as to accurately reflect the actual situation.

Referring again to FIG. 15, the solid line curve in FIG._dof
The source voltage V _sUse dependent multiplication factor m
And snatched by a circuit simulator (HSPICE)
It shows the result of simulating the
Yes, fitting each parameter appropriately
, Device simulator indicated only by black circles
Snapback characteristic music obtained using (Medici)
Good agreement was found between the lines.

As described above, in the fifth embodiment of the present invention, the circuit simulation is performed by reflecting the source voltage V _s dependence of the multiplication coefficient m in the high drain voltage V _d region. Snapback characteristics can be obtained.

In the first and second embodiments, as shown in FIG. 2 or FIG.
_b constitutes an equivalent circuit to be inserted between the base terminal and the base region.
_pne is represented by the capacitance between the emitter region and the base terminal.

However, _{despite the fact} that the junction capacitance C _pne depends only on the junction voltage between the emitter region and the base region and does not essentially depend on the base resistance _Rb , FIG. In the case of 5, the junction capacitance C _pne has a base resistance R _b dependency. Therefore, there is a problem that parameters such as the junction capacitance C _pne cannot be set independently at the time of fitting.

Referring to FIG. 16, as shown in FIG. 16, the connection position of the base resistor _Rb was changed to enable more accurate simulation. Therefore, the _{dependence of} the junction capacitances C _pnc , C _pne , the first current sources I _pnc , I _pne , and the second current sources I _mc , I _me on the base resistance R _b can be eliminated. Also in the first to fifth embodiments, a simulation with higher accuracy can be performed.

However, in general, the base resistance R _b varies with an increase in the number of holes according to the electrons injected into the base region, that is, the channel region on the substrate surface. Therefore, the base resistance R _b is given as a fixed value. When the simulation is performed by using the simulation, there is a problem that the result becomes inaccurate.

Therefore, such a base resistor R_bFluctuations
FIGS. 17 to 19 show a sixth embodiment of the present invention in consideration of FIGS.
This will be described with reference to FIG. Referring to FIG. 17, FIG._bEquivalent considering the fluctuation of
Circuit and the conventional R _bAnd R_wellAnd three series circuits
Resistance R_bs, R_bd, R_b0Parallel circuit and R_wellSeries times with
Road. In this case, the base resistor
Anti-R_bIs the resistance of the channel region and R_wellIs the channel
This is a resistance component from the region to the substrate terminal.

That is, as described above, when a voltage is applied to the drain, electrons flowing from the source cause an impact ionization phenomenon near the drain to generate an electron-hole pair, and a hole current is generated in the substrate. Flows. Next, when holes accumulate in the substrate, a forward bias is applied between the source and the substrate, and holes flow to the source. On the other hand, electrons are injected into the substrate, but a part of the electrons flow into the drain to cause impact ionization. This will further increase the drain current.

In this case, if the number of electrons injected from the source to the substrate increases and exceeds a certain number, the number of holes in the substrate increases to maintain charge neutrality, and the base resistance _Rb varies. Become.

That is, e is the elementary charge, μ is the hole mobility, p
If was the total hole concentration, R _b α1 / (eμp) next, p is the number of acceptors N _A, when the number of holes generated in order to maintain charge neutrality of the n, p = N _A + n Where n is generated due to electrons injected from the source in consideration of the case where the source and the drain are driven on the opposite side in circuit operation in consideration of the symmetry of the source and the drain. was the number of holes n _s, if the number of holes generated due to the electrons injected from the drain to the n _d, can be expressed by n = n _s + n _d.

[0081] In summary of the _{above, R b α1 / (eμp)} = 1 / [eμ (N _A + n)] = 1 / _{[eμ (N A + n s +} n d) ] _{= 1 / (eμN A + eμn} s + eμn _d ) = 1 / (1 / R _b0 + 1 / R _bs + 1 / R _bd ).

That is, as shown in FIG. 17, the base resistor R _b is represented by a parallel circuit of three resistors R _b0 , R _bs , and R _bd . In this case, since R _b0 is a resistance component due to the number of acceptors N _A in the channel region, R _b0 is expressed as a constant and does not consider holes generated due to injection of electrons from the source or the drain. The resistance of the channel region when the impact ionization phenomenon does not occur, that is, the resistance when the forward bias between the source (drain) and the substrate is low.

On the other hand, R _bs is a resistance component generated by the number of holes n _s generated by electrons injected from the source, and R _bd is generated by electrons injected from the drain. the resistance component that occurs due to the number of holes n _d generated Te, these resistance component, the modulated component of the base resistance R _b.

[0084] Figure 18 Referring FIG. 18, which was visually indicates the source voltage V _s dependence of the base resistance R _b, an acceptor number of the channel region N _A
The solid line resistance component by R _b0 is indicated by a constant value of the solid line, the resistance component R _bs caused by the number of holes n _s generated due to the electrons injected from the source, which decreases with the source voltage V _s Is shown as a curve. Note that when electrons injected from the drain side contributes replaces the R _bs in R _bd, may look as the drain voltage V _d dependence.

Accordingly, the base resistance R _b is represented by the reciprocal of the sum of the reciprocal of R _{b0 and} the reciprocal of R _bS. Therefore, in the region where the source voltage V _S is small, the resistance R _b0 is relatively small. , whereas, in the area source voltage V _s is greater represented by small R _bs relatively resistance in this region, it will be represented by a curve indicated by a broken line in the intermediate region.

Since R _well is a resistance value in a region which is not affected by electron injection, when simulating the snapback characteristic, four resistances of R _bs , R _bd , R _b0 , and R _well are used. Tabulate the values, among which R
Let _b0 and R _{well be} constant values.

Referring to FIG. 19, FIG. 19 shows the result of a simulation performed by a circuit simulator (HSPICE) in which the base resistor R _b is replaced by an equivalent circuit composed of a parallel circuit of three resistors R _b0 , R _bs , and R _bd. And good agreement with the simulation results by the device simulator (Medici) indicated by black circles.

As described above, according to the sixth embodiment of the present invention.
The base resistance R_bTo R_b0, R _bs, And R_bdThree
Replace with an equivalent circuit consisting of a parallel circuit of two resistors.
Of the number of holes generated by electrons injected into the tunnel region
Base resistance R due to increase_bIt reflects the fluctuation of
A more accurate simulation can be performed. FIG.
5 and FIG. 19 are substantially the same, and FIG.
The base resistance R_bSimulation to reflect fluctuations in
Ration.

The embodiments of the present invention have been described above. However, the present invention is not limited to the configurations and conditions described in each embodiment, and various changes can be made. For example, in each of the above embodiments, an n-channel MOSFET has been described as the ESD protection element, but a p-channel MOSFET may be used.

Although the above embodiments have been described on the premise that a Si integrated circuit device is used, the basic concept of the present invention is also applied to a compound semiconductor device such as a GaAs integrated circuit device. And in that case, the ESD
Since the protection circuit is usually formed of a MESFET or the like, the circuit simulation may be performed by replacing the MESFET with a bipolar transistor or an equivalent circuit of a bipolar transistor and a MESFET.

In the third embodiment, the ESD is controlled by MOSFETs arranged in 4 rows × 6 columns.
Although the protection circuit is configured, such a configuration is merely an example. The main feature of the third embodiment is that the configuration of the entire ESD protection circuit is obtained by incorporating CAD layout data into a netlist and performing circuit simulation. Therefore, the present invention is not limited to the above layout and circuit configuration.

[0092] In the fourth embodiment described above, when evaluating the current I _h flowing from the substrate to the source region, and the voltage V _b of the substrate and V _b = 0V, the collector voltage V
_{c is set} to a constant voltage of 1 V or less, for example, V _c = 0.05 V, and the current I _h flowing from the substrate to the source region by changing the emitter voltage V _e , that is, the base current I _b is evaluated. It is not limited to such an evaluation method.

For example, when the emitter voltage V _e is set to V _e = 0
V, and the collector voltage V _c is less than a constant voltage 1V, the substrate voltage V _sub, i.e., current is varied the base voltage V _b flowing from the substrate to the source region I _h, i.e., be evaluated base current I _b Good thing. However, in this case, the voltage applied between the substrate and the drain, that is, _Vbc fluctuates and the environment changes, so that some inaccuracy remains.

(Supplementary Note 1) The electrostatic discharge protection element constituted by the insulated gate field effect transistor is replaced with an equivalent circuit using a bipolar transistor, and the current flowing from the collector to the substrate and the current flowing from the emitter to the substrate are replaced by At least 2 currents flowing from the collector to the substrate
A method of simulating an electrostatic discharge protection circuit, wherein the circuit is simulated by expressing the resistance to electrostatic discharge protection by two current power supplies. (Supplementary Note 2) The electrostatic discharge protection element constituted by the insulated gate type field effect transistor is replaced with an equivalent circuit using a bipolar transistor and an insulated gate type field effect transistor. A method of simulating an electrostatic discharge protection circuit, wherein at least a current flowing from a drain to a substrate among the flowing currents is represented by two current power supplies, and a circuit simulation is performed on the resistance to electrostatic discharge protection. (Supplementary note 3) The electrostatic discharge protection circuit according to Supplementary note 1 or 2, wherein the layout data of the whole electrostatic discharge protection circuit is fetched from the computer-aided design layout data to generate input data of the circuit simulator. Simulation method. (Supplementary Note 4) When extracting a multiplication coefficient m for representing a current power supply due to an impact ionization current among two current power supplies representing a current flowing from the collector or the drain of the equivalent circuit to the substrate, an emitter or a drain from the substrate is extracted. 4. The method of simulating an electrostatic discharge protection circuit according to any one of appendices 1 to 3, wherein the dependence of a current flowing through the circuit on the substrate voltage is adopted. (Supplementary Note 5) When extracting the multiplication coefficient m for representing the current power supply based on the impact ionization current, the collector current or the drain current in the case where the impact ionization phenomenon is not taken in is extracted from the emitter current or the source current and the emitter or the source. 4. The method for simulating an electrostatic discharge protection circuit according to claim 4, wherein the method is represented by a difference from a current flowing through a drain. (Supplementary Note 6) The simulation method of the electrostatic discharge protection circuit according to Supplementary Note 5, wherein the source voltage dependency is reflected when the multiplication coefficient m for representing the current power supply by the impact ionization current is extracted. (Supplementary note 7) The electrostatic capacitance according to Supplementary note 6, wherein a weighting function is incorporated in the input data when generating the input data of the circuit simulator using the multiplication coefficient m reflecting the source voltage dependency. Simulation method of destruction protection circuit. (Supplementary note 8) Any one of supplementary notes 1 to 7, wherein the base resistance of the equivalent circuit reflects a change in resistance due to majority carriers generated due to minority carriers injected from the source or the drain into the substrate. 2. The method for simulating an electrostatic discharge protection circuit according to claim 1. (Supplementary Note 9) The base resistance of the equivalent circuit is defined as a resistance component due to majority carriers generated by the number of impurities, a resistance component due to majority carriers generated due to minority carriers injected from the source to the substrate, and a resistance component from the drain to the substrate. The method for simulating an electrostatic discharge protection circuit according to claim 8, wherein the circuit is represented by a parallel circuit of three resistance components of resistance components due to majority carriers generated due to the injected minority carriers.

[0095]

According to the present invention, when a circuit simulation is performed using a circuit simulator, the ESD protection elements constituting the ESD protection circuit are replaced with an equivalent circuit including at least a bipolar transistor, and at least the collector side of the bipolar transistor is used. two current source I _pnc in, since the simulation by setting the I _mc, without overestimate the ESD tolerance allows accurate simulation.

When evaluating the ESD resistance of the entire ESD protection circuit, the circuit configuration of the entire ESD protection circuit is simulated by incorporating the CAD layout data into the netlist, so that the simulation can be performed quickly. Since the layout position dependence of the power consumption of each ESD element can be analyzed, the layout can be optimized.

[0097] Also, two current source I _pnc the collector side, among the I _mc, when evaluating the multiplication factor m which represents the impact ionization ratio for representing a current source I _mc when incorporating impact ionization a source current I _sii the collector current I _c when no incorporating ion impact phenomenon, since it represents the difference between the current I _h flowing from the substrate to the source region, the source voltage dependence in the low drain voltage V _d region Multiplication factor m without
As a result, parameters can be extracted from the actually measured data, so that the simulation is simplified and more accurate simulation results can be obtained.

[0098] Also, two current source I _pnc the collector side, among the I _mc, when extracting the multiplication factor m which represents the impact ionization ratio for representing a current source I _mc when incorporating impact ionization , by reflecting the source voltage V _s dependence, it is possible to obtain a more accurate simulation results.

Further, the base resistor R _b constituting the equivalent circuit
However, a simulation result with higher accuracy can be obtained by reflecting a change in resistance due to an increase in holes generated due to electrons injected into the substrate.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an equivalent circuit diagram of the ESD protection circuit according to the first embodiment of the present invention.

FIG. 3 is a model structure diagram of a bipolar transistor forming an equivalent circuit according to the first embodiment of the present invention.

FIG. 4 is an I _c -V _c characteristic diagram according to the first embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram of an ESD protection circuit according to a second embodiment of the present invention.

FIG. 6 is an I _d -V _d characteristic diagram according to the second embodiment of the present invention.

FIG. 7 is an equivalent circuit diagram of an ESD protection circuit according to a third embodiment of the present invention.

FIG. 8 is a layout diagram of an ESD protection circuit according to a third embodiment of the present invention.

FIG. 9 is an explanatory diagram of the dependence of the I _d -V _d characteristics on the wiring resistance R according to the third embodiment of the present invention.

FIG. 10 shows power consumption P according to the third embodiment of the present invention.
FIG. 4 is an explanatory diagram of the wiring resistance R dependence and the layout position dependence of the present invention.

FIG. 11 shows a multiplication factor m according to the first embodiment of the present invention.
And is a diagram showing a simulation result of the correlation between the drain voltage V _d.

12 is a diagram showing a simulation result of the correlation between the multiplication factor m and the drain voltage V _d when the drain current I _d is replaced with the source current I _sii.

13 is a diagram showing a simulation result of the current I _h flowing from the substrate to the source.

14 is a diagram showing a simulation result of the correlation between the multiplication factor m and the drain voltage V _d in the case of considering the current I _h flowing from the substrate to the source.

FIG. 15 shows I _d −V _d according to the fifth embodiment of the present invention.
It is a characteristic diagram.

FIG. 16 is an equivalent circuit diagram accurately reflecting the contribution of the base resistance.

FIG. 17 is an equivalent circuit diagram of the sixth embodiment of the present invention in which a change in base resistance is taken into account.

FIG. 18 is a diagram showing the source voltage V _S dependence of a base resistor _Rb .

FIG. 19 shows I _d −V _d according to the sixth embodiment of the present invention.
It is a characteristic diagram.

FIG. 20 is an explanatory diagram of a conventional ESD protection circuit.

[Explanation of symbols]

 Reference Signs List 11 p-type substrate 12 n-type drain region 13 n-type source region 21 MOSFET 22 parasitic element 23 wiring resistance 31 gate electrode 32 drain region 33 source region 34 drain region

Claims (5)

[Claims] 1. An electrostatic discharge protection device comprising an insulated gate field effect transistor is replaced by an equivalent circuit using a bipolar transistor, and at least a collector current out of a current flowing from a collector to a substrate and a current flowing from an emitter to a substrate. Characterized in that a current flowing from the substrate to the substrate is represented by two current power supplies, and a circuit simulation is performed on the electrostatic breakdown protection resistance. 2. An electrostatic discharge protection device comprising an insulated gate type field effect transistor is replaced with an equivalent circuit using a bipolar transistor and an insulated gate type field effect transistor. And at least the current flowing from the drain to the substrate out of the current flowing through
A method for simulating an electrostatic discharge protection circuit, comprising: performing circuit simulation of resistance to electrostatic discharge protection. 3. The ESD protection circuit according to claim 1, wherein layout data of the entire ESD protection circuit is fetched from computer-aided design layout data to generate input data for a circuit simulator. Circuit simulation method. 4. A method for extracting a multiplication coefficient m for representing a current power supply by an impact ionization current from two current power supplies representing a current flowing from a collector or a drain of the equivalent circuit to a substrate. 4. The method for simulating an electrostatic discharge protection circuit according to claim 1, wherein the dependence of the current flowing through the drain on the substrate voltage is adopted. 5. When extracting a multiplication coefficient m for representing a current power supply based on the impact ionization current, a collector current or a drain current in a case where the impact ionization phenomenon is not taken in is extracted from an emitter current or a source current and an emitter from a substrate. 5. The method for simulating an electrostatic discharge protection circuit according to claim 4, wherein the difference is represented by a difference from a current flowing through the drain.