JP2001338994A - Semiconductor storage device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To contrive low voltage by enlarging a coupling ratio value without sacrificing the increase of a chip area and the operation characteristic of an element and without increasing any manufacturing process. SOLUTION: A control gate 16 is formed on a semiconductor board 11 through a gate insulation film 15. A floating gate 18 is formed on the area of the side of the drain area 12 of a channel area 14 on the semiconductor board 11 through the semiconductor board 11 and the gate insulation film 15 and through the side of the side of the drain area 12 of the control gate 16 and a capacity insulation film 17. The control gate 16 has a protrusion part 16a protruded in the direction where the drain area 12 and a source area 13 extend on an element separation area 19. The floating gate 18 is formed through the capacity insulation film 17 even on the side of the protrusion part 16a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to an electrically erasable nonvolatile semiconductor memory device and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, as a semiconductor nonvolatile memory device,
EPROM (Erasable and Programmable Read Only Me)
mory) device, EEPROM (Electrically Erasable an)
d Programmable Read Only Memory) device or FeRA
M (Ferro-electric Random Access Memory) devices and the like have attracted attention.

[0003] Of these, EPROM devices or EEPROMs
The device charges and discharges electric charges to and from the floating gate, and stores data by detecting a change in threshold voltage due to the presence or absence of electric charges in the floating gate by the control gate. Also, E
As the EPROM device, there is a flash EEPROM device capable of erasing data in a chip unit.

[0004] Memory cells (memory transistors) constituting a flash EEPROM device are roughly classified into a stack gate type and a split gate type.

A flash EEPROM device using a stack gate type memory cell does not have a function of selecting a cell itself for each memory cell. Therefore, if the charge is excessively extracted when extracting the charge from the floating gate at the time of data erasure, the so-called excessive erasure problem occurs in that the memory cell from which the charge has been excessively extracted becomes depleted and the unselected cells leak. .

In order to prevent this excessive erasure, it is necessary to devise an erasing procedure. It is necessary to control the erasing procedure by a peripheral circuit of the memory device or to control the erasing procedure by an external circuit of the memory device.

A split gate type memory cell has been developed in order to avoid this excessive erasure, and its configuration is disclosed in, for example, US Pat. No. 5,029,130.

A flash EEPROM device using a split gate type memory cell has a function of selecting a cell itself for each memory cell. Therefore, even if excessive erasure occurs, conduction or non-conduction of the memory cell is performed. Over-erasing is not a problem.

A conventional semiconductor nonvolatile memory (flash EEPROM) device using a stack gate type memory cell or a split gate type memory cell will be described below with reference to the drawings.

First, as shown in FIGS. 10A and 10B, a stack gate type memory cell has a drain region 102 and a source region 103 formed on a semiconductor substrate 101 made of silicon. Semiconductor substrate 10
A floating gate 106 is formed on a channel region 104 interposed between a drain region 102 and a source region 103 in FIG. 1 via a first dielectric film 105. A control gate 108 is provided on the floating gate 106 via a second dielectric film 107.
Are formed.

On the other hand, a split gate memory cell is
As shown in FIGS. 11A and 11B, a drain region 102 is formed on a semiconductor substrate 101 made of silicon.
And the source region 103 are formed.
01, a first dielectric film 105 made of silicon oxide having a relatively small thickness is formed on a channel region 104 sandwiched between the drain region 102 and the source region 103.
, A control gate 108 is formed.
On the drain region 102 side of the control gate 108, a floating gate 106 having a sidewall shape is formed via a second dielectric film 107. This floating gate 106 has a small overlap with both the drain region 102 and the floating gate 106,
It has a configuration with a very small gate length.

Incidentally, the capacitance (Cc) between the control gate 108 and the floating gate 106 is:
Floating gate 106 and channel region 104
(Or source region 103 or drain region 102)
Increasing the value of the ratio between the capacitance and the capacitance (Cf) between the control gate and the floating gate 106, in particular, increasing the value of the coupling ratio indicating the propagation of the potential from the control gate 108 to the floating gate 106 is a flash EEPROM device. This is an important factor for reducing the operating voltage of the device. Here, the coupling ratio is the total capacitance (Cc + Cf).
Of the capacitance (Cc) between the control gate 108 and the floating gate 106 with respect to (Cc / (C
c + Cf)).

[0013]

However, in the EEPROM device using the conventional stack type memory cell and split gate type memory cell, in order to increase the coupling ratio, the opposite of the floating gate 106 and the control gate 108 is required. Either increase the area and decrease the facing area between the floating gate 106 and the channel region 104 or the like, or change the value of the thickness ratio between the first dielectric film 105 and the second dielectric film 107 Is required.

In the former case, for example, if the gate width (W _FG ) of the floating gate 106 is increased in order to increase the opposing area between the floating gate 106 and the control gate 108, the element area increases and the integration is increased. It will be unsuitable. Further, for example, reducing the gate length (L _FG ) of the floating gate in order to reduce the facing area between the floating gate 106 and the channel region 104 is not effective only in the split gate type memory cell shown in FIG. However, it is difficult from the viewpoint of fine processing. Also, reducing the channel width of the channel region 14 reduces the cell current, which leads to a reduction in the reading speed for the memory cell.

On the other hand, in the latter case, the second dielectric film 10
It is difficult to reduce the film thickness of 7 from the viewpoint of reliability.

The present invention solves the above-mentioned conventional problems, without increasing the chip area or sacrificing the operating characteristics of the device.
It is another object of the present invention to reduce the voltage by increasing the value of the coupling ratio without increasing the number of manufacturing steps.

[0017]

In order to achieve the above object, according to the present invention, an overhanging portion is formed at a portion of a control gate located on an element isolation region, so that an opposing area between a floating gate and a control gate is formed. Is increased to increase the capacitance between the control gate and the floating gate.

More specifically, a first semiconductor memory device according to the present invention includes a plurality of element isolation regions formed on a semiconductor substrate and isolating a plurality of source / drain regions from each other, and a first isolation region formed on the semiconductor substrate. A control gate formed so as to straddle a plurality of source / drain regions and a plurality of element isolation regions via a dielectric film, and a second dielectric film on one side surface of the control gate on the semiconductor substrate; A floating gate formed, wherein the control gate has a projecting portion in which a portion located on the element isolation region projects in a direction in which the source / drain region extends, and the floating gate is provided with a second dielectric film interposed therebetween. It is also formed on the side of the overhang.

The first semiconductor memory device is a split gate type semiconductor memory device. According to the present memory device,
A portion of the control gate located on the element isolation region has an overhang extending in the direction in which the source / drain region extends, and a floating gate is also formed on the side surface of the overhang via the second dielectric film. As a result, the facing area between the floating gate and the control gate increases, so that the capacitance between the control gate and the floating gate increases, and the value of the coupling ratio increases. As a result, the voltage operation of the element can be reduced, so that the element isolation region or the charge pump circuit can be reduced, so that the chip size can be reduced.

In the first semiconductor memory device, the control gate is formed on the source / drain region in a direction substantially perpendicular to the direction in which the source / drain region extends, and the overhang portion forms the source / drain region between the element isolation regions. It is preferable that at least one of the opposing regions is formed so as to extend substantially parallel to the direction in which the source / drain region extends. With this configuration, the overhanging portion of the control gate and the floating gate on the side surface of the overhanging portion can be reliably formed by a normal process.

A second semiconductor memory device according to the present invention comprises: a plurality of element isolation regions formed on a semiconductor substrate for isolating a plurality of source / drain regions from each other;
A plurality of floating gates formed so as to straddle each source / drain region via a first dielectric film, and a portion above the floating gate on a semiconductor substrate via a second dielectric film; A control gate formed so as to straddle the source / drain region and the plurality of element isolation regions, and the control gate has an overhanging portion in which a portion located on the element isolation region extends in a direction in which the source / drain region extends. And the floating gate
It is also formed below the overhang via the second dielectric film.

The second semiconductor memory device is a stacked gate type semiconductor memory device. According to this memory device, a portion of the control gate located on the element isolation region projects in the direction in which the source / drain region extends. Since the floating gate has an overhang and the floating gate is also formed below the overhang via the second dielectric film, the facing area between the floating gate and the control gate becomes large. The capacitance with the control gate increases. As a result, the value of the coupling ratio becomes large, and the voltage operation of the element can be reduced, so that the element isolation region or the charge pump circuit can be reduced, so that the chip size can be reduced.

In the second semiconductor memory device, the floating gate and the control gate are formed on the source / drain region in a direction substantially perpendicular to the direction in which the source / drain region extends, and the overhang is formed between the source / drain region between the element isolation regions. It is preferable that at least one of the regions facing each other across the region is formed so as to extend substantially parallel to the direction in which the source / drain region extends.
In this case, the overhang of the control gate and the floating gate below the overhang can be reliably formed by a normal process.

In the second semiconductor memory device, it is preferable that the floating gate is formed such that the plane direction of the end face on the element isolation region intersects the direction in which the source / drain region extends. In this case, the area of the control gate and the floating gate formed for each element below the control gate are further increased, and the value of the coupling ratio is further increased, so that the memory cell is further reduced. It becomes possible.

A third semiconductor memory device according to the present invention comprises: a plurality of element isolation regions formed on a semiconductor substrate for isolating a plurality of source / drain regions from each other;
A floating gate formed so as to straddle each source / drain region via a first dielectric film, and a plurality of floating gates including a top surface of the floating gate on a semiconductor substrate via a second dielectric film A control gate formed so as to straddle the source / drain region and the plurality of element isolation regions, the control gate has a planar crank shape having a bent portion on the element isolation region adjacent to each other, and the floating gate includes It is also formed on a portion located on the element isolation region via the second dielectric film.

According to the third semiconductor memory device, the control gate has a planar crank shape having a bent portion on the element isolation region adjacent to each other, and the floating gate is formed on the element isolation region via the second dielectric film. , The area of opposition between the floating gate and the control gate increases, so that the value of the coupling ratio increases. In addition, since the ratio of the control gate and the floating gate to the chip area becomes smaller as compared with the configuration in which the wide portion is provided,
It is possible to further reduce the chip size.

According to the method of manufacturing a semiconductor memory device of the present invention, a plurality of element isolation regions for isolating a plurality of element regions from each other are formed on a semiconductor substrate, and a plurality of element isolation regions are formed on the semiconductor substrate. A step of depositing a control gate formation film over the entire surface including the support gate formation film, comprising: two support portions extending substantially parallel to the control gate formation film; and a plurality of crosspieces connected to the support portions at substantially equal intervals. Forming a ladder-shaped film from the control gate-formed film by performing patterning so as to form a flat ladder and each cross-section on an element isolation region; and forming a floating gate-formed film over the entire surface including the ladder-shaped film. Is deposited on the inner surface of the ladder-shaped film by performing etch-back on the deposited floating gate forming film. A step of forming a floating gate formed of a loading gate forming film, and a step of forming a source / drain region above the semiconductor substrate by performing impurity implantation on the semiconductor substrate using at least a ladder-shaped film as a mask; Forming a control gate made of a ladder-shaped film by selectively etching a central portion of each crosspiece in the shaped film and the floating gate to divide the pillar portions from each other.

A method of manufacturing a semiconductor memory device according to the present invention is a method of manufacturing a split gate type semiconductor memory device, comprising forming a ladder-shaped film having a cross section formed on an element isolation region from a control gate forming film. Then, after forming a floating gate composed of a floating gate forming film on the inner surface of the ladder-shaped film, etching is performed on the central portion of each cross section of the ladder-shaped film and the floating gate adjacent to the central portion. In order to form a control gate made of a ladder-shaped film by dividing the strut portions from each other, a control gate can be formed from the ladder-shaped film so that the cross section becomes an overhanging portion, and the inner surface of the ladder-shaped film can be formed. Since the floating gate can be divided for each element, the first semiconductor memory device of the present invention can be reliably obtained. Door can be.

[0029]

(First Embodiment) A first embodiment of the present invention.
An embodiment will be described with reference to the drawings.

FIGS. 1A and 1B show a first embodiment of the present invention.
1A shows a schematic plan configuration, and FIG. 1B shows an enlarged view taken along line Ib-Ib of FIG. 1A. FIG.

As shown in FIGS. 1A and 1B,
For example, a band-shaped drain region 12 and a source region 13 are formed on a semiconductor substrate 11 made of p-type silicon.
A control gate 16 made of polysilicon is formed on a channel region 14 sandwiched between the gate and source region 13 via a gate insulating film 15 as a first dielectric film. The region of the channel region 14 on the side of the drain region 12 on the semiconductor substrate 11
A floating gate 18 made of polysilicon is formed via a gate insulating film 15 and a side surface of the control gate 16 on the drain region 12 side via a capacitive insulating film 17 as a second dielectric film. .

The control gate 16 according to the present embodiment
Is a device isolation region 1 having a LOCOS film or a shallow trench isolation (STI) structure provided on a semiconductor substrate 11.
9 is characterized by having an overhang 16a projecting in the direction in which the drain region 12 and the source region 13 extend. In addition, the floating gate 18 is
Also formed on the side surface of “a” via the capacitance insulating film 17, it is divided between adjacent memory cells on the element isolation region 19.

Here, the charge injected into the floating gate 18 is formed in the capacitance insulating film 17 by the control gate 1.
A film thickness, material, or process that has a withstand voltage of such a degree that it cannot be pulled out may be used.

Hereinafter, the coupling ratio between the split gate semiconductor memory device according to the present embodiment and the conventional split gate semiconductor memory device will be compared.

FIGS. 2A and 2B show a semiconductor memory device for indicating the dimensions of the components necessary for calculating the value of the coupling ratio. FIG. 2A shows the first embodiment. FIG. 2B shows a schematic plan configuration of a split-gate semiconductor memory device according to an embodiment, and FIG. 2B shows a schematic plan configuration of the conventional split-gate semiconductor memory device shown in FIG. . Here, in FIGS. 2A and 2B, the same components as those shown in FIGS. 1A and 11B are denoted by the same reference numerals, and description thereof will be omitted.

First, a conventional nonvolatile semiconductor device shown in FIG.
In the conductor storage device, the height of the control gate 108 is high.
And the channel width W is 0.44 μm.
And the source / drain direction of the floating gate 106
Length L (= gate length direction) _FGTo 0.1 μm,
The driving gate 106 and the control gate 108
(Overlap) width W of_FGIs set to 0.92 μm,
Between the control gate 108 and the substrate 11 and
Between the roll gate 108 and the floating gate 106
Between the thickness of the first dielectric film (= gate oxide film) 105 and
And the same material, the conventional semiconductor memory device described above
Coupling ratio C_R0Can be approximated by the following equation (1)
You.

C _R0 = Cc / (Cc + Cf) = h · W _FG / (h · W _FG + L _FG · W) (1) By substituting the above dimensional values into equation (1), the coupling ratio C _R0 The value is about 0.81.

On the other hand, when the nonvolatile semiconductor memory device according to the present embodiment shown in FIG. 2A is applied to the memory cell 1 having the same area as the conventional memory cell 1, the element in the control gate 16 When the length P _CG of the protrusion 16a on the isolation region 19 and 0.25 [mu] m, the coupling ratio C _R1 can be approximated by the following equation (2).

C _R1 = Cc / (Cc + Cf) = h (W _FG + 2P _CG ) / {h (W _FG + 2P _CG ) + L _FG · W} (2) As shown in the equation (2), substantial floating The width of the gate 18 becomes W _FG + 2P _CG = 1.42 μm. In this case, the value of the coupling ratio C _R1 is 0.87, which is about 1.1 of the coupling ratio C _R0 of the conventional semiconductor memory device. Double.

As described above, since the control gate 16 can transmit a predetermined potential to the floating gate 18 so that the loss during propagation is reduced, the operation of injecting or discharging the charge into the floating gate 18 is performed at a low voltage. Therefore, the nonvolatile semiconductor memory device can be reliably operated even at a low voltage. Further, by reducing the operating voltage, the circuit scale of the charge pump circuit can be reduced.

Hereinafter, a method of manufacturing the semiconductor memory device configured as described above will be described with reference to the drawings.

FIGS. 3 (a) to 3 (c) and FIG. 4 (a)
FIG. 4B shows a cross-sectional configuration in a process order of the method for manufacturing the semiconductor memory device according to the first embodiment.

First, as shown in FIG. 3A, an element isolation region 19 having, for example, an STI structure is selectively formed on a semiconductor substrate 11. Subsequently, a gate oxide film 15 is formed over the entire surface including the element isolation region 19 on the semiconductor substrate 11 by using a thermal oxidation method or the like, and then, by a CVD method or the like.
A control gate forming film 16A made of polysilicon is deposited on the entire surface of the gate oxide film 15.

Next, as shown in FIG. 3B, a portion of the control gate formation film 16A located on the element isolation region 19 is formed by a lithography method. The control gate 16 is formed from the control gate formation film 16A by performing etching so as to have an overhang portion 16a that extends in the direction in which the region extends.

Next, as shown in FIG. 3C, a capacitive insulating film 17 is formed on the entire surface of the control gate 16 by using, for example, a thermal oxidation method. At this time, the film thickness of the capacitor insulating film 17 is set to a thickness such that a charge injected into a floating gate formed in a later step has a withstand voltage such that the charge is not extracted to the control gate 16.

Next, as shown in FIG. 4A, a floating gate forming film 18A made of polysilicon is formed over the entire surface including the element isolation region 19 and the control gate 16 on the semiconductor substrate 11 by using the CVD method or the like. Is deposited. Subsequently, by etching back the deposited floating gate forming film 18A, the floating gate forming film 18A is self-aligned into a sidewall shape on the side surface of the control gate 16 via the capacitor insulating film 17. I do. At this time, since the formed floating gate forming film 18A has a sidewall shape, the gate length L of the floating gate
_{Since FG} can be reduced, the coupling ratio C _R1 can be improved. Subsequently, by using the control gate 16 and the floating gate forming film 18A as a mask, n-type impurity ions are implanted into the upper portion of the semiconductor substrate 11 to form the drain region 12 and the source region.

Next, as shown in FIG. 4B, a resist pattern having an opening pattern 2 exposing at least an end of each overhang 16a is formed by lithography, and the formed resist pattern is used. Then, by etching the region on the side surface of the end of the overhang 16a in the floating gate forming film 18A, the floating gate 18 for each element is obtained from the floating gate forming film 18.

As described above, in the method for manufacturing the semiconductor memory device according to the first embodiment, the control gate 16 is formed to have the overhang 16a on the element isolation region 19, and the control gate 16 is formed on the side surface of the overhang 16a. Also form the floating gate 18. Therefore, except for the shapes of the control gate 16 and the floating gate 18, there is no need to change the manufacturing process of the conventional split gate type semiconductor nonvolatile memory device, that is, it is necessary to add a new process to the conventional manufacturing process. Therefore, the value of the coupling ratio can be increased as compared with the conventional case.

In the control gate forming step shown in FIG. 3C, relatively low concentration n-type impurity ions may be implanted into the upper portion of the semiconductor substrate 11 using the control gate 16 as a mask.

(Modification of Manufacturing Method) Hereinafter, a modification of the method of manufacturing the semiconductor memory device according to the first embodiment will be described with reference to the drawings.

After the control gate forming film depositing step shown in FIG. 3A, as shown in FIG. 5A, two pillar portions 16 extending substantially in parallel by using a lithography method.
b and a plurality of crosspieces 16c connected at substantially equal intervals to the support pillars 16b, and each of the crosspieces 1 has a flat ladder shape.
By patterning the control gate formation film 16A so that 6c is formed on the element isolation region 19, a ladder-shaped film 16B is formed from the control gate formation film 16A.

Thereafter, a floating gate forming film 18A is deposited over the entire surface including the element isolation region 19 and the control gate 16 on the semiconductor substrate 11, and the deposited floating gate forming film 18A is etched back. The floating gate forming film 18A is formed in a self-aligned sidewall shape on the inner surface of the ladder-shaped film 16B via the capacitive insulating film 17.

Subsequently, the drain region 12 and the source region 13 are formed by implanting n-type impurity ions into the upper portion of the semiconductor substrate 11 using the ladder-shaped film 16B and the floating gate forming film 18A as a mask.

Next, a resist pattern having a central portion of each crosspiece of the ladder-shaped film and an opening pattern 3 exposing a floating gate adjacent to the central portion is formed, and etching is performed using the formed resist pattern as a mask. , The two struts 1 of the ladder-shaped film 16B
6b are separated from each other to form a ladder-shaped film 1
The control gate 16 is formed from 6B.

In this manner, the floating gate 18 is connected to the overhang portion 16a of the control gate 16.
, The control gates 16 of the memory cells sharing the drain region 12 can be closer to each other, so that the size of the memory cells can be further reduced.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIGS. 6A and 6B show a second embodiment of the present invention.
6 (a) shows a schematic plan configuration, and FIG. 6 (b) is an enlarged view taken along the line VIb-VIb of FIG. 6 (a). FIG.

As shown in FIGS. 6A and 6B,
For example, a plurality of strip-shaped drain regions 22 and source regions 23 are formed on a semiconductor substrate 21 made of p-type silicon.
Is formed on the channel region 24 of the semiconductor substrate 21 interposed between the drain region 22 and the source region 23 via a gate insulating film 25 as a first dielectric film. Floating gate 26 is formed.

On the semiconductor substrate 22, the floating gate 2 is interposed via a capacitance insulating film 27 as a second dielectric film.
Control gate 2 including the upper part of the gate region 6 and extending over the plurality of drain regions 22 and source regions 23.
8 are formed.

As a feature of the second embodiment, the control gate 28 is provided by a LOCO provided on the semiconductor substrate 21.
On the element isolation region 29 having the S film or the STI structure, there is provided an overhang portion 28a which extends in the direction in which the drain region 22 and the source region 23 extend. Further, each floating gate 26 is provided with an overhang portion 28 of the control gate 28.
a is also formed below the capacitor insulating film 27 via the capacitor insulating film 27.
It is divided between adjacent memory cells on the element isolation region 29.

Hereinafter, the coupling ratio between the stack gate type semiconductor memory device according to the present embodiment and the conventional stack gate type semiconductor memory device will be compared.

FIGS. 7 (a) and 7 (b) show a semiconductor memory device for indicating the dimensions of the components required for calculating the value of the coupling ratio. FIG. 7 (a) shows the second embodiment. FIG. 7B shows a schematic plan configuration of the stacked gate semiconductor memory device according to the embodiment, and FIG. 7B shows a schematic plan configuration of the conventional split gate semiconductor memory device shown in FIG. . Here, in FIG. 7A and FIG. 7B, the same components as those shown in FIG. 6A and FIG.

First, in the conventional nonvolatile semiconductor memory device shown in FIG. 7B, the channel width W is set to 0.44 μm, the gate length L is set to 0.5 μm, and the opposition between the floating gate 106 and the control gate 108 ( overlap) the width W _FG and 0.84 .mu.m, and between control gate 1 and the control gate 108 and the substrate 11
If the thickness and material of the first dielectric film (= gate oxide film) 105 between the gate electrode 08 and the floating gate 106 are the same, the coupling ratio C of the conventional semiconductor memory device is
_R0 can be approximated by the following equation (3).

C _R0 = Cc / (Cc + Cf) = L · W _FG / (L · W _FG + L · W) (3) By substituting the above dimension values into equation (3), the value of the coupling ratio C _R0 is obtained. Is about 0.66.

On the other hand, when the nonvolatile semiconductor memory device according to the present embodiment shown in FIG. 7A is applied to the memory cell 1 having the same area as the conventional memory cell 1, the floating Width W of the lower side of the portion 28a
The _PFG and 0.25 [mu] m, when a 0.5μm length sum value P _CG of the projecting portion 28a on the element isolation region 29 in the control gate 28, approximated by coupling ratio C _R1 is the following formula (4) it can.

C _R1 = Cc / (Cc + Cf) = (L · W _FG + 2W _PFG · P _CG ) / (L · W _FG + 2W _PFG · P _CG + L · W) (4) When the value is substituted, the value of the coupling ratio C _R1 becomes 0.75, which is about 1.1 times the coupling ratio C _R0 of the conventional semiconductor memory device.

As described above, even in the case of a stacked gate type nonvolatile semiconductor memory device, since the loss when the control gate 28 transmits a predetermined potential to the floating gate 26 is further reduced, the charge to the floating gate 26 is reduced. Can be performed at a low voltage. As a result, low-voltage operation of the nonvolatile semiconductor memory device is enabled, and the circuit size of the charge pump circuit can be reduced by lowering the operating voltage.

(Modification of Second Embodiment) Hereinafter, a semiconductor memory device according to a modification of the second embodiment of the present invention will be described with reference to the drawings.

FIG. 8 shows a schematic plan configuration of a semiconductor memory device according to a modification of the second embodiment. 8, the same components as those shown in FIG. 6 (a) are denoted by the same reference numerals.

As shown in FIG. 8, both end surfaces of the floating gate 26A according to the present modification, which are located on the element isolation region 29 and below the overhang portion 28a of the control gate 28, have an end surface in the drain direction. It is characterized in that the region 22 and the source region 23 are formed so as to intersect with the extending direction.

As a result, the opposing area between the control gate 28 and the floating gate 26A formed for each element below the control gate 28 is further increased, so that the memory cell can be further reduced in size.

In the manufacturing method according to the present modification, the floating gate 26A need only be divided on the element isolation region 29 so as to intersect with the direction in which the drain region 22 and the source region 23 extend. There is no need to change the manufacturing process itself.

(Third Embodiment) Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 9 shows a schematic plan configuration of a stack gate type nonvolatile semiconductor memory device according to a third embodiment of the present invention.

As shown in FIG. 9, for example, a band-shaped drain region 32 and a source region 33 are formed on a semiconductor substrate 31 made of p-type silicon, and the drain region 32 and the source region 33 in the semiconductor substrate 31 are formed. A floating gate 36 made of polysilicon is formed on a channel region sandwiched between the floating gate 33 and a gate insulating film (not shown) as a first dielectric film.

On the semiconductor substrate 22, over the floating gate 36 and across the drain region 32 and the source region 23 via a capacitive insulating film (not shown) as a second dielectric film. The formed control gate 38 is formed. The control gate 38 according to the third embodiment has a flat crank shape having a bent portion on the element isolation region 39 adjacent to each other, and the floating gate 36 is formed on the element isolation region 39 via the capacitance insulating film. Is also formed in the portion located at.

As described above, according to the third embodiment, since the drain region 32 and the source region 33 in the memory cells 1A and 1B adjacent to each other are alternately arranged, the cell of each memory cell 1A and 1B Size can be reduced.

[0078]

According to the semiconductor memory device and the method of manufacturing the same according to the present invention, the cell current can be reduced or the insulating film can be formed regardless of whether the memory device is a split gate type semiconductor device or a stack gate type semiconductor memory device. The reliability of the device does not decrease due to the thinning of the device, and the capacitance between the control gate and the floating gate increases without changing the number of masks or the manufacturing process, thereby increasing the coupling ratio. Voltage can be reduced. As a result, the element isolation region or the charge pump circuit can be reduced, so that the chip size can be reduced.

[Brief description of the drawings]

FIGS. 1A and 1B show a split gate nonvolatile semiconductor memory device according to a first embodiment of the present invention, FIG. 1A is a schematic plan view, and FIG. It is a partial perspective view including the expanded section in Ib-Ib line of (a).

FIGS. 2 (a) and 2 (b) show a semiconductor memory device for representing dimensions of constituent members necessary for calculating a coupling ratio value, and FIG. 2 (a) relates to a first embodiment of the present invention. It is a schematic plan view showing a split gate type semiconductor memory device, and (b) is a schematic plan view showing a conventional split gate type semiconductor memory device.

3A to 3C are cross-sectional perspective views illustrating a method of manufacturing the semiconductor memory device according to the first embodiment of the present invention in the order of steps.

FIGS. 4A and 4B are cross-sectional perspective views illustrating a method of manufacturing the semiconductor memory device according to the first embodiment of the present invention in the order of steps.

FIGS. 5A and 5B are schematic plan views illustrating a modification of the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention in the order of steps.

FIGS. 6A and 6B show a stacked gate nonvolatile semiconductor memory device according to a second embodiment of the present invention, FIG. 6A is a schematic plan view, and FIG. (A)
FIG. 6 is a partial perspective view including an enlarged cross section taken along line VIb-VIb.

FIGS. 7 (a) and 7 (b) show a semiconductor memory device for representing dimensions of components required for calculating a value of a coupling ratio, and FIG. 7 (a) relates to a second embodiment of the present invention. 1 is a schematic plan view showing a stack gate type semiconductor memory device, and FIG. 1 (b) is a schematic plan view showing a conventional stack gate type semiconductor memory device.

FIG. 8 is a schematic plan view showing a semiconductor memory device according to a modification of the second embodiment of the present invention.

FIG. 9 is a schematic plan view showing a semiconductor memory device according to a third embodiment of the present invention.

FIGS. 10A and 10B show a conventional stack gate type memory cell, FIG. 10A is a sectional view showing the configuration of one cell, and FIG. 10B is a schematic plan view of a plurality of cells. is there.

11A and 11B show a conventional split gate type memory cell, FIG. 11A is a cross-sectional view of one cell, and FIG. 11B is a schematic plan view of a plurality of cells. is there.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory cell 1A Memory cell 1B Memory cell 2 Opening pattern 3 Opening pattern 11 Semiconductor substrate 12 Drain region 13 Source region 14 Channel insulating film 15 (gate dielectric film as first dielectric film) 16 Control gate 16a Overhang 16A Control Gate forming film 16B Ladder-shaped film 16b Support portion 16c Bar portion 17 Capacitive insulating film (second dielectric film) 18 Floating gate 18A Floating gate forming film 19 Element isolation region 21 Semiconductor substrate 22 Drain region 23 Source region 24 Channel region 25 Gate insulating film (first dielectric film) 26 Floating gate 26A Floating gate 27 Capacitive insulating film (second dielectric film) 28 Control gate 28a Overhang 29 Element isolation region 31 Semiconductor substrate 32 Rain region 33 source region 36 a floating gate 38 control gate 39 isolation region

 ──────────────────────────────────────────────────の Continuing on the front page (72) Kazuhiro Toki 1006 Kazuma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Akio Shimano 1006 Kazama Kadoma Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. (72) Inventor Makoto Kojima 1006 Kazuma Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. (72) Inventor Masaki Ogura 12590, New York, United States Wappingers Falls, Old Hopewell Road 140, Halo LSI Design and F-term in Device Technology Inc. (reference) 5F001 AA22 AA23 AA32 AB03 AB09 5F083 EP03 EP13 EP23 EP25 ER21 GA09 GA22 NA01 PR39 5F101 BA04 BA05 BA14 BB04 BB17

Claims (7)

[Claims] A plurality of element isolation regions formed on a semiconductor substrate for isolating a plurality of source / drain regions from each other; and a plurality of source / drain regions on the semiconductor substrate via a first dielectric film. A control gate formed so as to straddle a plurality of element isolation regions; and a floating gate formed on one side surface of the control gate on the semiconductor substrate via a second dielectric film. The control gate has a projecting portion in which a portion located on the element isolation region projects in a direction in which the source / drain region extends, and the floating gate has the projecting portion via the second dielectric film. A semiconductor memory device formed also on the side surface of the semiconductor memory device. 2. The control gate is formed on the source / drain region in a direction substantially perpendicular to a direction in which the source / drain region extends, and the overhang portion sandwiches the source / drain region between the element isolation regions. 2. The semiconductor memory device according to claim 1, wherein at least one of the regions facing each other is formed so as to extend substantially parallel to a direction in which the source / drain region extends. 3. A plurality of element isolation regions formed in a semiconductor substrate and separating a plurality of source / drain regions from each other; and a plurality of source / drain regions on the semiconductor substrate via a first dielectric film. A floating gate formed so as to straddle the semiconductor substrate, and a portion above the floating gate via the second dielectric film on the semiconductor substrate and straddling the plurality of source / drain regions and the plurality of element isolation regions. A control gate formed as described above, wherein the control gate has an overhanging portion in which a portion located on the element isolation region extends in a direction in which the source / drain region extends. 2. A semiconductor memory device, wherein the semiconductor memory device is also formed below the overhang portion via a second dielectric film. 4. The floating gate and the control gate are formed on the source / drain region in a direction substantially perpendicular to a direction in which the source / drain region extends, and the overhang portion is provided in the source / drain region between the element isolation regions. 4. The semiconductor memory device according to claim 3, wherein at least one of the regions facing each other across the region is formed so as to extend substantially parallel to a direction in which the source / drain region extends. 5. The floating gate according to claim 3, wherein the floating gate is formed such that a plane direction of an end face on the element isolation region intersects a direction in which the source / drain region extends. Semiconductor storage device. 6. A plurality of element isolation regions formed on a semiconductor substrate and separating a plurality of source / drain regions from each other; and a plurality of source / drain regions on the semiconductor substrate via a first dielectric film. A floating gate formed so as to straddle the semiconductor substrate, including a top surface of the floating gate on the semiconductor substrate via a second dielectric film, and straddling the plurality of source / drain regions and the plurality of element isolation regions. The control gate has a planar crank shape having a bent portion on the element isolation region adjacent to each other, and the floating gate is provided through the second dielectric film. A semiconductor memory device, wherein the semiconductor memory device is also formed in a portion located on the element isolation region. 7. A step of forming a plurality of element isolation regions on a semiconductor substrate for isolating a plurality of element regions from each other, and forming a control gate formation film over the entire surface including the plurality of element isolation regions on the semiconductor substrate. A step of depositing, and a flat ladder-shaped flat surface including two support portions extending substantially parallel to the control gate forming film and a plurality of crosspieces connected to the support portions at substantially equal intervals. Forming a ladder-shaped film from the control gate-forming film by patterning so that the crosspiece is formed on the element isolation region; and depositing a floating gate-forming film over the entire surface including the ladder-shaped film. By performing etch-back on the deposited floating gate forming film, the above-mentioned floating film is formed on the inner surface of the ladder-shaped film. Forming a floating gate formed of a rotating gate forming film; and forming a source / drain region on the semiconductor substrate by performing impurity implantation on the semiconductor substrate using at least the ladder-shaped film as a mask. And controlling the central part of the ladder-shaped film and the floating gate adjacent to the central part by selectively etching to divide the pillars from each other, thereby controlling the ladder-shaped film. Forming a gate.