JP2001338933A - Method of manufacturing semiconductor package - Google Patents
Method of manufacturing semiconductor packageInfo
- Publication number
- JP2001338933A JP2001338933A JP2000157549A JP2000157549A JP2001338933A JP 2001338933 A JP2001338933 A JP 2001338933A JP 2000157549 A JP2000157549 A JP 2000157549A JP 2000157549 A JP2000157549 A JP 2000157549A JP 2001338933 A JP2001338933 A JP 2001338933A
- Authority
- JP
- Japan
- Prior art keywords
- mark
- circuit board
- semiconductor package
- chip mounting
- defective
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、多数個取りする半
導体パッケージに係わり、更に詳しくは電気試験工程
（オープンショートチエック）を効率化した半導体パッ
ケージの製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package having a large number of semiconductor chips, and more particularly to a method of manufacturing a semiconductor package in which an electric test process (open short check) is performed efficiently.
【０００２】[0002]
【従来の技術】従来の一般的な半導体パッケージの製造
方法について説明する。図３において、図３（ａ）に示
す回路基板形成工程は、符号１は回路基板で、その両面
に銅箔を積層したガラスエポキシ樹脂等よりなる適当な
大きさに裁断された多数個取りする絶縁基板である。先
ず、スルーホール加工工程で回路基板１の所定のピッ
チ、所定の寸法に設定された複数個の図示しないスルー
ホールを切削ドリル等の加工手段により穴明けする。2. Description of the Related Art A conventional general method for manufacturing a semiconductor package will be described. In FIG. 3, in the circuit board forming step shown in FIG. 3A, reference numeral 1 denotes a circuit board, and a large number of pieces cut into appropriate sizes made of glass epoxy resin or the like having copper foil laminated on both surfaces thereof are taken. It is an insulating substrate. First, in a through hole processing step, a plurality of through holes (not shown) set at a predetermined pitch and a predetermined size of the circuit board 1 are formed by a processing means such as a cutting drill.
【０００３】前記スルーホールの壁面を含む回路基板１
を洗浄した後、全面に銅の無電解メッキ及び電解メッキ
を行い銅メッキ層の導電体膜を形成する。前記導電体膜
はスルーホール内まで形成される。続いて、フォトリソ
グラフィによりこの導電体膜をパターン化する。即ち、
回路基板１の表面及びスルーホール内にフォトレジスト
膜を電着法により塗布する。次に、回路基板１の両面に
フォトマスクを重ねた状態で露光を行い、フォトレジス
ト膜を現像することによってフォトマスクをパターン化
する。その後、導電体膜をエッチングし、フォトレジス
ト膜を剥離することによって、回路基板１の上面に図示
しないダイパターン及びリードパターンを形成して複数
のＩＣチップ実装領域を形成すると共に、スルーホール
の内面にスルーホール電極を形成する。尚、回路基板１
の裏面側にも、前記スルーホール電極から続く外部接続
用電極を露呈するように、マトリックス状に多数の同一
形状の半田付け可能な表面であるレジスト膜の開口部を
形成し、回路基板１が完成される。ここで、必要に応じ
てソルダーレジストインキ及び金メッキ等の処理を施し
ても良い。The circuit board 1 including the wall surface of the through hole
, And then electroless plating and electrolytic plating of copper are performed on the entire surface to form a conductor film of a copper plating layer. The conductor film is formed up to the inside of the through hole. Subsequently, the conductor film is patterned by photolithography. That is,
A photoresist film is applied on the surface of the circuit board 1 and in the through holes by an electrodeposition method. Next, exposure is performed in a state where a photomask is overlaid on both sides of the circuit board 1, and the photomask is patterned by developing the photoresist film. Thereafter, by etching the conductor film and removing the photoresist film, a die pattern and a lead pattern (not shown) are formed on the upper surface of the circuit board 1 to form a plurality of IC chip mounting areas and the inner surface of the through hole. Then, a through-hole electrode is formed. The circuit board 1
On the back side of the substrate, a large number of openings of a resist film, which are solderable surfaces of the same shape, are formed in a matrix so as to expose the external connection electrodes following the through-hole electrodes. Be completed. Here, if necessary, a treatment such as solder resist ink and gold plating may be performed.
【０００４】次に、前記回路基板１の検査工程におい
て、配線パターンの断線及び外観不良チエックを行い、
回路基板の不良箇所に対応して該当する回路基板のＩＣ
チップ実装領域面に油性インク等を用いて画像認識で識
別可能な第１の不良識別マーク（バッドマーク）２を付
ける。符号１Ａは第１の不良識別マーク２を付与した不
良回路基板である。Next, in the inspection process of the circuit board 1, disconnection of the wiring pattern and appearance defect check are performed.
Circuit board IC corresponding to the defective part of the circuit board
A first defect identification mark (bad mark) 2 that can be identified by image recognition is attached to the chip mounting area surface using oil-based ink or the like. Reference numeral 1A is a defective circuit board provided with the first defect identification mark 2.
【０００５】図３（ｂ）に示すＩＣチップ実装工程は、
前記回路基板１をキュアー後、回路基板１上に前記第１
の不良識別マーク２を付与した不良回路基板１Ａを除い
た箇所に複数個のＩＣチップ３をダイボンドし、ダイボ
ンドキュアー・ＵＶ洗浄後ＩＣチップ３の各電極と外部
接続用のリードパターンとをワイヤー４によりワイヤー
ボンドする。[0005] The IC chip mounting step shown in FIG.
After curing the circuit board 1, the first
A plurality of IC chips 3 are die-bonded to portions other than the defective circuit board 1A to which the defect identification mark 2 is attached, and after die bond curing and UV cleaning, each electrode of the IC chip 3 is connected to a lead pattern for external connection with a wire 4. Wire bonding.
【０００６】図３（ｃ）に示す樹脂封止工程は、前記ワ
イヤーボンド工程におけるワイヤー４をチエック後に前
記ＩＣチップ３及びワイヤー４を熱硬化性のエポキシ樹
脂等からなる封止樹脂５により一括してトランスファー
モールドすることにより、前記ＩＣチップ３の遮光と保
護を行う。In the resin sealing step shown in FIG. 3C, after the wires 4 in the wire bonding step are checked, the IC chips 3 and the wires 4 are collectively sealed with a sealing resin 5 made of a thermosetting epoxy resin or the like. By performing transfer molding, light shielding and protection of the IC chip 3 are performed.
【０００７】前記トランスファーモールドした封止樹脂
５の各パッケージに該当する表面にそれぞれ半導体パッ
ケージの仕様等を表示するマーキング６を施す。A marking 6 for indicating the specifications of the semiconductor package is provided on the surface of the transfer molding sealing resin 5 corresponding to each package.
【０００８】図３（ｄ）に示す突起電極形成工程は、前
記トランスファーモールドキュアー後に、前記回路基板
１の下面に形成した外部接続用電極の半田バンプ搭載面
に半田ボールを位置決めしリフローして突起電極７を形
成する。In the projection electrode forming step shown in FIG. 3D, after the transfer mold cure, the solder ball is positioned on the solder bump mounting surface of the external connection electrode formed on the lower surface of the circuit board 1 and reflowed. An electrode 7 is formed.
【０００９】前記樹脂封止した回路基板１を洗浄した
後、直交するカットラインＸ（Ｙは図示せず）に沿って
ダイシング又はスライシングにより単個の完成半導体パ
ッケージ８に分割する。After the resin-sealed circuit board 1 is washed, it is divided into single completed semiconductor packages 8 by dicing or slicing along orthogonal cut lines X (Y is not shown).
【００１０】前記分割された完成半導体パッケージ８の
外観をチエックした後、全数についてＯＳ（オープンシ
ョート）チエックを行い導通不良等の電気的不良品を排
除する。このＯＳチエックでは当然不良品である前述し
た第１の不良識別マーク２を付与しＩＣチップ３が搭載
されていない不良パッケージも検査される。ＯＳチエッ
クにより良品と判定された完成半導体パッケージ８のみ
を梱包し出荷することになる。After the appearance of the divided completed semiconductor package 8 is checked, an OS (open short) check is performed on all the completed semiconductor packages 8 to eliminate electrically defective products such as conduction failure. In this OS check, a defective package in which the above-described first defect identification mark 2 which is a defective product is attached and the IC chip 3 is not mounted is also inspected. Only the completed semiconductor package 8 determined to be non-defective by the OS check is packed and shipped.
【００１１】[0011]
【発明が解決しようとする課題】しかしながら、前述し
た半導体パッケージの製造方法には次のような問題点が
ある。即ち、回路基板の状態で不良識別マークを付与し
ＩＣチップが実装されていない半導体パッケージは樹脂
封止後は外観からは識別不可能なため、当然不良パッケ
ージであるにもかかわらずＯＳチエックに掛けなければ
ならない。ＯＳチエック工数がムダになりその分コスト
アップになる。従って、ＯＳチエックを効率化すること
が課題になる。However, the above-described method for manufacturing a semiconductor package has the following problems. That is, a semiconductor package on which a defect identification mark is provided in a state of a circuit board and on which an IC chip is not mounted cannot be visually identified after resin sealing. There must be. The OS check man-hour is wasted and the cost increases accordingly. Therefore, it is necessary to improve the efficiency of the OS check.
【００１２】本発明は上記従来の課題に鑑みなされたも
のであり、その目的は、ＯＳチエックを効率化し、信頼
性に優れた安価な半導体パッケージの製造方法を提供す
るものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and has as its object to provide a method of manufacturing an inexpensive semiconductor package with improved OS checking efficiency and excellent reliability.
【００１３】[0013]
【課題を解決するための手段】上記目的を達成するため
に、本発明における半導体パッケージの製造方法は、上
面には複数のＩＣチップ実装領域を形成するとともに、
下面には前記複数のＩＣチップ実装領域に対応する複数
の外部接続電極領域を形成した多数個取り用の回路基板
を形成する回路基板形成工程と、前記回路基板を検査
し、不良箇所に対応する前記ＩＣチップ実装領域に第１
の不良マークを付ける不良マーク付与工程と、前記第１
の不良マークが付与されていない前記ＩＣチップ実装領
域にのみＩＣチップを実装するＩＣチップ実装工程と、
前記ＩＣチップ実装領域を一括して樹脂封止する樹脂封
止工程と、樹脂封止した回路基板を個々のＩＣチップ実
装領域毎に切断分離して複数の半導体パッケージを形成
する切断分離工程とからなる半導体パッケージの製造方
法において、前記第１の不良マークが付与されたＩＣチ
ップ実装領域を有する半導体パッケージの表面には、前
記不良マーク付与工程から前記切断分離工程までの間
に、第２の不良マークを付与したことを特徴とするもの
である。In order to achieve the above object, a method of manufacturing a semiconductor package according to the present invention comprises forming a plurality of IC chip mounting areas on an upper surface,
A circuit board forming step of forming a circuit board for multi-cavity formation in which a plurality of external connection electrode areas corresponding to the plurality of IC chip mounting areas are formed on the lower surface, and inspecting the circuit board to deal with defective portions First in the IC chip mounting area
A bad mark providing step of providing a bad mark
An IC chip mounting step of mounting an IC chip only in the IC chip mounting area where no defect mark is given;
A resin sealing step of collectively sealing the IC chip mounting area with a resin, and a cutting and separating step of cutting and separating the resin-sealed circuit board into individual IC chip mounting areas to form a plurality of semiconductor packages. In the method of manufacturing a semiconductor package, a second defect is provided on the surface of the semiconductor package having the IC chip mounting area to which the first defect mark has been added, from the step of applying the defect mark to the step of cutting and separating. A mark is provided.
【００１４】また、前記第２の不良マークは、不良マー
ク付与工程の時に外部接続電極領域に付与されることを
特徴とするものである。Further, the second defective mark is provided to the external connection electrode region at the time of the defective mark providing step.
【００１５】また、前記第２の不良マークは、外部接続
電極領域に形成される突起電極に形状不良を発生させる
ように付与することを特徴とするものである。Further, the second defect mark is provided so as to cause a shape defect in the protruding electrode formed in the external connection electrode region.
【００１６】また、前記第２の不良マークは、樹脂封止
工程の後に樹脂封止部の表面に付与されることを特徴と
するものである。Further, the second defective mark is provided on the surface of the resin sealing portion after the resin sealing step.
【００１７】また、前記ＩＣチップ実装領域はＩＣチッ
プを電気的に接続するための配線パターンを有し、外部
接続電極領域はスルーホールを介して前記配線パターン
と接続して電極パターンを有しており、第２の不良マー
クは、前記電極パターン上に付与することを特徴とする
ものである。The IC chip mounting area has a wiring pattern for electrically connecting the IC chip, and the external connection electrode area has an electrode pattern connected to the wiring pattern via a through hole. The second defective mark is provided on the electrode pattern.
【００１８】また、前記第２の不良マークは、インクマ
ーキング、レーザーマーキング等の識別手段により識別
可能に付与されたことを特徴とするものである。Further, the second defective mark is provided so as to be identifiable by identification means such as ink marking and laser marking.
【００１９】[0019]
【発明の実施の形態】以下図面に基づいて本発明におけ
る半導体パッケージの製造方法について説明する。図１
は、本発明の第１の実施の形態に係わる半導体パッケー
ジの製造方法を説明するための要部断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor package according to the present invention will be described below with reference to the drawings. FIG.
FIG. 4 is a cross-sectional view of a main part for describing a method of manufacturing a semiconductor package according to the first embodiment of the present invention.
【００２０】従来技術と異なるところは、図１（ａ）に
示すように、前記第１の不良識別マーク２を付ける不良
識別マーク付与工程の時に、前記第１の不良識別マーク
２に対応する半導体パッケージの外部接続電極領域であ
る半田バンプ搭載面に第２の不良識別マーク１０を付与
することである。The difference from the prior art is that, as shown in FIG. 1A, a semiconductor device corresponding to the first defect identification mark 2 is provided at the time of the defect identification mark attaching step of attaching the first defect identification mark 2. The purpose is to provide the second defect identification mark 10 on the solder bump mounting surface, which is the external connection electrode area of the package.
【００２１】前記半田バンプ搭載面に付与された第２の
不良識別マーク１０は、半田と親和性の悪いインク（溶
液）をマーキングするか、又は、レーザーマーキングで
凹形状を形成することにより半田ボール付けで故意に形
状異常な突起電極７Ａ（図１ｄ参照）が発生する様にす
る。又は、半田ボール付け後に視認可能な識別インクを
塗布する。The second defect identification mark 10 provided on the solder bump mounting surface is formed by marking ink (solution) having low affinity with solder or by forming a concave shape by laser marking. The projection electrode 7A (see FIG. 1d) having an abnormal shape is intentionally generated. Alternatively, identification ink that can be visually recognized after solder ball attachment is applied.
【００２２】上記した構成により、第２の不良識別マー
ク１０を付与することにより、ダイシング工程後の外観
検査工程で半田ボール不良や視認可能な識別インクによ
り、容易に不良パッケージを排除することができるの
で、排除された個数分だけＯＳチエック個数が少なくな
る。With the above-described configuration, by providing the second defect identification mark 10, a defective package can be easily removed due to a solder ball defect or visible identification ink in the appearance inspection process after the dicing process. Therefore, the number of OS checks is reduced by the excluded number.
【００２３】図２は、本発明の第２の実施の形態に係わ
る半導体パッケージの製造方法を説明するための要部断
面図である。図２に示すように、前記樹脂封止工程の後
に封止樹脂５表面に第２の不良識別マーク２０を付与す
る。前記第２の不良識別マーク２０は、前記第１の不良
識別マーク２を付ける不良識別マーク付与工程の時に、
第１の不良識別マーク２に対応する半導体パッケージの
位置座標を記憶しておき、その不良半導体パッケージの
封止樹脂５表面に、インクマーキングにより識別インク
を塗布するか、又は、レーザーマーキングで凹形状を形
成する。更に、不良半導体パッケージの封止樹脂５表面
に、通常のマーキング（製品仕様等）を付けないで他の
半導体パッケージと区別する方法を採っても良い。FIG. 2 is a cross-sectional view of a main part for describing a method of manufacturing a semiconductor package according to a second embodiment of the present invention. As shown in FIG. 2, a second defect identification mark 20 is provided on the surface of the sealing resin 5 after the resin sealing step. The second defect identification mark 20 is provided at the time of the defect identification mark attaching step of attaching the first defect identification mark 2.
The position coordinates of the semiconductor package corresponding to the first defective identification mark 2 are stored, and the identification ink is applied to the surface of the sealing resin 5 of the defective semiconductor package by ink marking, or the concave shape is formed by laser marking. To form Furthermore, a method of distinguishing the defective semiconductor package from other semiconductor packages without attaching a normal marking (product specification or the like) to the surface of the sealing resin 5 may be adopted.
【００２４】以上した構成により、ダイシング工程後の
外観検査工程で封止樹脂５の表面に付与された視認可能
な識別インクや、レーザーマーキングによる凹形状及び
通常マーキング無しにより容易に判別することができ不
良品を排除することが可能である。従って、排除された
個数分だけＯＳチエック個数が少なくなる。With the above-described structure, it is possible to easily determine the identification ink applied to the surface of the sealing resin 5 in the appearance inspection process after the dicing process, the concave shape by laser marking, and the absence of normal marking. Defective products can be eliminated. Therefore, the number of OS checks is reduced by the excluded number.
【００２５】なお、本発明は上記実施形態に限定するも
のではなく、例えば回路基板は樹脂製の基板、セラミッ
ク基板、フレキシブル基板等いずれでも良い。また、樹
脂封止の方法はトランスファーモールド、ポッティング
等のいずれの方法でも良い。更に、外部接続電極には必
ずしも突起電極を形成する必要はなく、第２の不良マー
クは認識できる程度に付与すれば良い。突起電極を形成
する場合は、半田、金、銅、アルミ等いずれの突起電極
でも良い。The present invention is not limited to the above embodiment. For example, the circuit board may be any one of a resin substrate, a ceramic substrate, a flexible substrate and the like. Further, the resin sealing method may be any method such as transfer molding and potting. Furthermore, it is not always necessary to form a protruding electrode on the external connection electrode, and the second defective mark may be provided to an extent that it can be recognized. When forming the protruding electrodes, any protruding electrodes such as solder, gold, copper, and aluminum may be used.
【００２６】[0026]
【発明の効果】以上説明したように、従来は、集合回路
基板の検査工程で不良識別マークを付与しＩＣチップを
搭載しない不良半導体パッケージも含み全数についてダ
イシング工程後にＯＳチエックを行っていたが、この不
良半導体パッケージを外観検査で容易に排除することが
できるので、ＯＳチエック工数を低減することが可能に
なる。ＯＳチエックを効率化し、信頼性に優れた安価な
多数個取りする半導体パッケージの製造方法を提供する
ことができる。As described above, conventionally, the OS check is performed after the dicing process for all the semiconductor chips including the defective semiconductor package in which the defect identification mark is provided and the IC chip is not mounted in the inspection process of the collective circuit board. Since the defective semiconductor package can be easily removed by the appearance inspection, the number of OS check steps can be reduced. It is possible to provide a method of manufacturing an inexpensive multi-cavity semiconductor package with high reliability and excellent reliability.
【図１】本発明の第１実施の形態に係わる半導体パッケ
ージの製造方法を説明する要部断面図である。FIG. 1 is a fragmentary cross-sectional view for explaining a method for manufacturing a semiconductor package according to a first embodiment of the present invention.
【図２】本発明の第２実施の形態に係わる半導体パッケ
ージの製造方法を説明する要部断面図である。FIG. 2 is a fragmentary cross-sectional view for explaining a method for manufacturing a semiconductor package according to a second embodiment of the present invention.
【図３】従来の半導体パッケージの製造方法を説明する
要部断面図である。FIG. 3 is a fragmentary cross-sectional view for explaining the conventional method of manufacturing a semiconductor package.
１ 回路基板 １Ａ 不良回路基板 ２ 第１の不良識別マーク ３ ＩＣチップ ４ ワイヤー ５ 封止樹脂 ６ マーキング ７ 突起電極 ７Ａ 異常な突起電極 ８ 半導体パッケージ １０、２０ 第２の不良識別マーク DESCRIPTION OF SYMBOLS 1 Circuit board 1A Defective circuit board 2 First defect identification mark 3 IC chip 4 Wire 5 Sealing resin 6 Marking 7 Projection electrode 7A Abnormal projection electrode 8 Semiconductor package 10, 20 Second defect identification mark
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０５Ｋ 3/00 Ｈ０５Ｋ 3/00 Ｔ Ｈ０１Ｌ 23/12 Ｌ ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H05K 3/00 H05K 3/00 T H01L 23/12 L
Claims (6)
成するとともに、下面には前記複数のＩＣチップ実装領
域に対応する複数の外部接続電極領域を形成した多数個
取り用の回路基板を形成する回路基板形成工程と、前記
回路基板を検査し、不良箇所に対応する前記ＩＣチップ
実装領域に第１の不良マークを付ける不良マーク付与工
程と、前記第１の不良マークが付与されていない前記Ｉ
Ｃチップ実装領域にのみＩＣチップを実装するＩＣチッ
プ実装工程と、前記ＩＣチップ実装領域を一括して樹脂
封止する樹脂封止工程と、樹脂封止した回路基板を個々
のＩＣチップ実装領域毎に切断分離して複数の半導体パ
ッケージを形成する切断分離工程とからなる半導体パッ
ケージの製造方法において、前記第１の不良マークが付
与されたＩＣチップ実装領域を有する半導体パッケージ
の表面には、前記不良マーク付与工程から前記切断分離
工程までの間に、第２の不良マークを付与したことを特
徴とする半導体パッケージの製造方法。1. A circuit board for multi-cavity formation in which a plurality of IC chip mounting regions are formed on an upper surface and a plurality of external connection electrode regions corresponding to the plurality of IC chip mounting regions are formed on a lower surface. Forming a circuit board, inspecting the circuit board, and attaching a first defect mark to the IC chip mounting area corresponding to the defective portion; and providing the first defect mark without the first defect mark. I
An IC chip mounting step of mounting an IC chip only in the C chip mounting area, a resin sealing step of collectively sealing the IC chip mounting area with a resin, and a resin-sealed circuit board for each IC chip mounting area A semiconductor package having an IC chip mounting area provided with the first defect mark, wherein the defect is formed on the surface of the semiconductor package. A method of manufacturing a semiconductor package, wherein a second defective mark is provided between a mark providing step and the cutting / separating step.
与工程の時に外部接続電極領域に付与されることを特徴
とする請求項１記載の半導体パッケージの製造方法。2. The method of manufacturing a semiconductor package according to claim 1, wherein the second defective mark is provided to an external connection electrode region at a time of a defective mark providing step.
領域に形成される突起電極に形状不良を発生させるよう
に付与することを特徴とする請求項２記載の半導体パッ
ケージの製造方法。3. The method of manufacturing a semiconductor package according to claim 2, wherein the second defect mark is provided so as to cause a shape defect in a protruding electrode formed in an external connection electrode region.
の後に樹脂封止部の表面に付与されることを特徴とする
請求項１記載の半導体パッケージの製造方法。4. The method of manufacturing a semiconductor package according to claim 1, wherein said second defective mark is provided on a surface of a resin sealing portion after a resin sealing step.
電気的に接続するための配線パターンを有し、外部接続
電極領域はスルーホールを介して前記配線パターンと接
続して電極パターンを有しており、第２の不良マーク
は、前記電極パターン上に付与することを特徴とする請
求項１記載の半田バンプの製造方法。5. The IC chip mounting area has a wiring pattern for electrically connecting an IC chip, and the external connection electrode area has an electrode pattern connected to the wiring pattern via a through hole. 2. The method according to claim 1, wherein the second defective mark is provided on the electrode pattern.
ング、レーザーマーキング等の識別手段により識別可能
に付与されたことを特徴とする請求項１〜５のいずれか
記載の半導体パッケージの製造方法。6. The method of manufacturing a semiconductor package according to claim 1, wherein said second defective mark is identifiably provided by an identification means such as ink marking or laser marking.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000157549A JP2001338933A (en) | 2000-05-29 | 2000-05-29 | Method of manufacturing semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000157549A JP2001338933A (en) | 2000-05-29 | 2000-05-29 | Method of manufacturing semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001338933A true JP2001338933A (en) | 2001-12-07 |
| JP2001338933A5 JP2001338933A5 (en) | 2007-03-01 |
Family
ID=18662165
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000157549A Pending JP2001338933A (en) | 2000-05-29 | 2000-05-29 | Method of manufacturing semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001338933A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009164407A (en) * | 2008-01-08 | 2009-07-23 | Sumitomo Heavy Ind Ltd | Resin-encapsulated device and resin-encapsulation method |
| CN101483976B (en) * | 2008-01-11 | 2011-04-13 | 精工爱普生株式会社 | Method for manufacturing flexible substrate and flexible substrate punching device |
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| JPH0329331A (en) * | 1989-06-26 | 1991-02-07 | Mitsubishi Electric Corp | Manufacture of semiconductor |
| JPH04124848A (en) * | 1990-09-14 | 1992-04-24 | Toshiba Corp | Wire bonding inspecting device |
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| JPH10233468A (en) * | 1996-12-06 | 1998-09-02 | Anam Ind Co Inc | Printed circuit board strip for semiconductor package and indication of defective printed circuit board unit of this board strip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2009164407A (en) * | 2008-01-08 | 2009-07-23 | Sumitomo Heavy Ind Ltd | Resin-encapsulated device and resin-encapsulation method |
| CN101483976B (en) * | 2008-01-11 | 2011-04-13 | 精工爱普生株式会社 | Method for manufacturing flexible substrate and flexible substrate punching device |
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