JP2001332652A - Semiconductor package and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that a method to distribute a wiring in a simple layer is used in the design of a semiconductor package accompanying miniaturization of the package, lightening of the package and reduction in a TAT, but as a wiring layer can not be inserted between earth layers in this method, a low-loss transmission line can not be formed. SOLUTION: In a BGA package of a type which is encapsulated by coating a resin, a conducting layer is formed of a conductive sheet 13 or the like on the sealing surface of the package and the conducting layer is electrically connected with a metal substrate 1, which is used as an earth potential, through a connection terminal, such as a solder ball 12 for conductive sheet earth connection.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a "semiconductor package and a method of manufacturing the same", and more particularly to forming a low-loss transmission line using a semiconductor package in a package manufacturing process.

[0002]

2. Description of the Related Art Conventionally, this type of "semiconductor package and its manufacturing method" involves wiring in a single layer in package design along with miniaturization and weight reduction of semiconductor package and shortening of TAT. A method is used. FIG. 9A is a schematic sectional view of a conventional semiconductor device package. The package is based on a copper substrate 1 formed by bending a copper plate. A central portion of the copper substrate 1 has a depression serving as an LSI chip mounting area 1a. The copper substrate 1 is connected to the ground potential. A bonding stitch 4 and a wiring pattern 4 are formed by patterning a copper foil provided on the polyimide 2 around the copper substrate 1.
a and ball pads 4b and 4c. A solder resist 8 is applied as an insulating material to the outer periphery of the package, and a pad opening 8a is provided immediately above the ball pad 4b.
Is provided. Further, a solder ball 9 is provided on the pad opening 8a as a terminal for electrically connecting the LSI to the outside, for example, a printed circuit board. A dam 10 for damping the resin at the time of sealing is provided inside the solder ball 9.

[0003]

In the above-mentioned conventional semiconductor package, since the wiring layer cannot be sandwiched between the ground layers, the cross-sectional view of FIG.
As shown in the potential model diagram of (c), it was not possible to form a lower loss transmission line such as a coaxial cable surrounded by a ground potential. FIG. 9 (c) is the same as FIG.
It can be seen that there is a potential model in (b) and the drive wiring of 4d is not completely surrounded by the ground potential. Further, when a semiconductor LSI having a transmission line such as a coaxial cable is formed in a package manufacturing process, the semiconductor LSI must be formed in a laminated structure, so that the TAT of manufacturing the package becomes longer and the manufacturing cost increases. There is.

Accordingly, an object of the present invention is to form a ground layer and a wiring layer of a substrate in a package manufacturing process and to form a ground layer on a wiring in an assembling process, respectively. The purpose is to form a semiconductor LSI having a transmission line close to a coaxial cable.

[0005]

According to a semiconductor package of the present invention, an LSI chip mounted on a metal substrate is sealed with a resin, a conductive layer is formed on the sealing surface, and the conductive layer is connected to connection terminals. Is electrically connected to the ground potential of the metal substrate. Also, the LSI chip is mounted on the metal substrate, a bonding stitch is provided on the LSI chip and a wiring provided on the metal substrate via an insulating layer, and bonding is performed between the bonding stitch and the LSI chip by a wire. Resin sealing means, means for connecting the conductive layer to the metal substrate, means for attaching the conductive layer to the surface of the resin sealing, and for electrically connecting the conductive layer and the metal substrate; It is characterized by having. The connection between the metal substrate and the conductive layer is through a solder ball. Further, the conductive layer is formed of a conductive sheet. Further, the conductive layer is formed of a conductive thin plate. Also,
The present invention is characterized in that a sealing resin injection port is provided in the conductive thin plate. Further, the present invention is characterized in that a portion of the conductive plate corresponding to the wiring pattern is thickened.

Further, in the method of manufacturing a semiconductor package according to the present invention, the LSI chip is attached to the metal substrate, and the LSI chip and the bonding stitch of wiring on the metal substrate are electrically connected by wire bonding. A resin for encapsulating the LSI chip on the metal substrate is applied, and the encapsulating resin completely covers the LSI chip and wire bonding, and the tip of the ground connection solder ball on the conductive sheet or the metal thin plate is made of resin. As it comes out of the sealing surface, the resin is filled so as not to exceed the dam arranged in the peripheral portion of the metal substrate, then the resin baking is performed, and further the conductive sheet or Affixing the metal thin plate, and connecting the conductive sheet or the metal thin plate to the ground connection solder ball so as to have a ground potential. And butterflies. The resin baking is performed in a nitrogen atmosphere at about 150 ° C. for about 2 hours. Also, mounting the LSI chip, performing wire bonding, and then attaching the conductive thin plate,
The electrical connection is performed by soldering the solder ball for ground connection, and then, the sealing resin is injected from the resin injection port. Further, an epoxy resin is used for the resin sealing.

[0007]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a schematic sectional view showing the configuration of the first embodiment of the present invention. As shown in FIG. 1, in this embodiment, FIG. 1A is a schematic sectional view of a semiconductor device package of the present invention. The package is based on a copper substrate 1 formed by bending a copper plate. A central portion of the copper substrate 1 has a depression that becomes the LSI chip mounting area 1a. The copper substrate 1 is connected to the ground potential. A bonding stitch 4, a wiring pattern 4a, and ball pads 4b and 4c formed by patterning a copper foil disposed on the polyimide 2 are provided on the periphery of the copper substrate 1 with a polyimide 2 serving as an insulating layer. Having. A solder resist 8 is applied as an insulating material to the outer peripheral portion of the package, and a pad opening 8 is formed immediately above the ball pads 4b and 4c.
a and 8b are provided. Further, L is placed on the pad opening 8a.
Solder balls 9 are provided as terminals for electrically connecting the SI to the outside, for example, a printed circuit board. Further, the solder ball 1 for conductive sheet ground connection is provided on the pad opening 8b.
2 is provided. A dam 10 is provided between the solder balls 9 and 12 for damping the resin during sealing. The solder ball 12 is electrically connected to the copper substrate 1 by a ball pad 4c and a ground via 5, and is generally connected to a ground potential.

First, assembling is performed in the same manner as in a general manufacturing method.
The SI chip 6 is mounted on the LSI chip mounting area 1a,
The SI chip 6 and the bonding stitch 4 of the package are electrically connected by a bonding wire 7. Next, the encapsulating resin 11 is applied on the LSI chip 6 and then baked. A conductive sheet 13 is attached on the encapsulating resin 11. At this time, the conductive sheet 13 has the same potential as the substrate 1, that is, the ground potential, due to the conductive sheet ground connection solder balls 12. In this case, since the upper and lower sides of the wiring can be sandwiched between the ground layers, for example, as shown in FIGS. 1B and 1C, the ground wiring 4 is provided on both sides of the signal wiring 4d.
In the case where there is e, a pseudo coaxial structure can be taken, so that a transmission line with lower loss can be obtained as compared with the case where there is a ground layer only under the wiring layer. FIG. 1B is a cross-sectional view taken along line AA ′ of FIG. 1A, and FIG. 1C is a model diagram showing the potential of FIG. Indicates the copper substrate 1, the GND wiring 4e, and the conductive sheet 1.
3 surrounds it. Further, as shown in FIG. 1D, a ground layer can be provided near the bonding wire 7, so that loss due to crosstalk noise between the wires can be reduced. In addition, FIG.
It is sectional drawing in the BB 'line of (a).

An embodiment of a semiconductor device according to the present invention will be described with reference to FIGS. FIG. 1 is a schematic sectional view of a package of a semiconductor device according to the technique of the present invention. FIG. 2 is a view showing a process of manufacturing a semiconductor package according to the technique of the present invention. As the substrate, a plate having a laminated structure of a polyimide 2 serving as an insulating layer on a copper substrate 1 serving as a base and a copper foil 3 used as a wiring layer is used. As shown in FIG. 2A, the base is a copper plate having a thickness of 0.25 to 0.35 mm, the polyimide is about 30 μm, the relative dielectric constant is about 3, and the copper foil is about 20 μm. Next, the copper foil 3 and the polyimide 2 are patterned using a photolithography technique. Further, copper plating is performed, and similarly, patterning is performed by using a photolithography technique to form a bonding stitch 4, a wiring pattern 4a, ball pads 4b and 4c, and a ground via 5, respectively. In addition, as shown in FIG. 2B, the ball pad 4c is electrically connected to the copper substrate 1 at the ground potential by the ground via 5.

Next, a drawing process is performed using a die to form a chip mounting region 1a, a bonding stitch layer, and the like. Thereafter, a solder resist 8 serving as an insulating layer is formed by attaching a sheet and patterning by photolithography. At this time, as shown in FIG. 2C, pad openings 8a and 8b of solder resist are simultaneously formed on the ball pads 4b and 4c. Next, a solder ball 9 serving as a connection terminal with the outside such as a printed board is placed on the ball pad 4b, and a solder ball 12 for electrically connecting the conductive sheet to the board after assembly is connected to the ball pad 4c. It is formed on each. Solder ball 9
Usually has a diameter of 680 μm, and the conductive sheet ground connection solder ball 12 has a diameter of about 200 to 450 μm. Finally, a dam 10 is formed inside the solder ball 9 to prevent resin flow during sealing. Epoxy resin is used for the dam material. In addition, as shown in FIG. 2D, the dam width is about 1 mm, and the dam height is 100 to 30.
It is about 0 μm. Next, the operation of the semiconductor device according to the embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a view showing a process of assembling a semiconductor device according to the technique of the present invention. First, the LSI chip 6 is mounted with an epoxy resin or the like by a general manufacturing method, and the LSI chip 6 and the bonding stitch 4 are electrically connected by wire bonding 7 by a bonding operation. A gold wire having a diameter of 30 μm is usually used for the wire. Next, the sealing resin 11 is sealed by potting and baking. At this time, the encapsulating resin 11 completely covers the LSI chip 6 and the wire bonding 7, and the solder balls 12 for the ground connection of the conductive sheet.
So that the tip of the resin comes out of the resin sealing surface. FIG.
(A) As shown in FIG. An epoxy resin is used for the resin sealing. The resin baking is performed in a nitrogen atmosphere at about 150 ° C. for about 2 hours. Next, as shown in FIG. 3B, a conductive sheet 13 is attached to the surface of the resin sealing 11. The conductive sheet 13 is formed by attaching a conductive seal, coating a conductive material, or bonding a conductive thin plate. At this time, the conductive sheet 13 is electrically connected to the substrate 1 via the conductive sheet ground connection solder ball 12 so that the conductive sheet 13 is at the ground potential.

FIG. 5 is a schematic sectional view of a semiconductor device according to a second embodiment of the present invention. A conductive thin plate 13a is used instead of the conductive sheet 13 in FIG. At the center of the conductive thin plate, there is a resin injection port 11a for injecting the sealing resin. The package structure other than the conductive thin plate 13 is the same as that of the first embodiment. Next, the assembling process will be described with reference to the drawings. FIGS. 6A and 6B are views showing a process of assembling the semiconductor device according to the second embodiment of the present invention. Assembly is performed by mounting the LSI chip 6 in the same manner as in the first embodiment,
Wire bonding 7 is performed. Next, the conductive thin plate 13a
Paste. The conductive thin plate 13 is attached to the conductive sheet ground connection solder ball 12 by soldering. Next, as shown in FIG. 6B, the sealing resin 11 is injected from the resin injection port 11a. In this way, the height of the sealing surface can be easily adjusted in addition to the noise reduction effect.

FIG. 7 is a schematic sectional view of a semiconductor device according to a third embodiment of the present invention. FIG. 8 shows A-
It is a potential model of the cross section in the A 'line. Conductive thin plate 13
4B, the portion corresponding to the wiring pattern 4a is a thickened conductive plate portion 13c. Since the distance between the wiring pattern 4a and the conductive thin plate 13b can be reduced, for example, as shown in FIG. 8, the distance between the copper substrate 1 and the wiring pattern 4a, that is, the thickness of the polyimide is d1, the capacitance is C1, and the conductive plate is Thick portion 13c and wiring pattern 4a
Where d2 is the thickness of the encapsulating resin, C2 is the capacitance of the encapsulating resin, ε1 is the dielectric constant of the polyimide 2 and ε2 is the dielectric constant of the encapsulating resin 11, C1 = C2, that is, d1: d2.
= Ε1: ε2, more ideal impedance matching is achieved, and a transmission line with less loss can be obtained.

The effects of the embodiment of the present invention will be described with reference to the drawings. FIG. 4A is a diagram comparing an electric model in a cross section of the signal wiring portion of the package with and without the conductive sheet 13. In the case of the technology of the present invention,
Since the wiring pattern is sandwiched between the copper substrate 1 serving as the ground potential layer and the conductive sheet 13, the noise path to the adjacent wiring is considered. Can be partially cut off, and noise can be reduced accordingly.
FIG. 4B is an example of a potential model diagram of a cross section in the semiconductor device of the present invention. As shown in FIG.
When the ground wiring 4e is provided on both sides of the signal wiring 4d, the upper, lower, left and right sides of the signal wiring 4d are surrounded by ground, so that a so-called low-loss pseudo-coaxial structure can be obtained.

FIG. 4 (c) is a cross-sectional view of FIG.
It is a sectional perspective view and a sectional view in the B 'line. FIG.
As shown in (c), since the conductive sheet 13 of the ground potential layer is provided near the bonding wire 7, it is possible to suppress the spread of the electromagnetic field 21 generated from each wire even when, for example, two wires approach each other. As a result, crosstalk noise between wires can be reduced.

[0015]

As described above, according to the present invention, the wiring pattern is sandwiched between the copper substrate serving as the ground potential layer and the conductive sheet. Since the transmission path of the noise passing through the upper part can be partially cut, the noise to the adjacent wiring can be reduced. When the ground wiring is provided on both sides of the signal wiring, the upper, lower, left and right sides of the signal wiring are surrounded by the ground, so that a low-loss pseudo-coaxial structure can be obtained. Also, since there is a conductive sheet of the ground potential layer near the bonding wire,
For example, even when two wires approach each other, the spread of an electromagnetic field generated from each wire can be suppressed, and crosstalk noise between the wires can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a first embodiment of the present invention.

FIG. 2 is a diagram of a package manufacturing process according to the first embodiment.

FIG. 3 is a diagram of an assembly process according to the first embodiment.

FIG. 4 is a diagram of an electric model according to a second embodiment of the present invention.

FIG. 5 is a schematic sectional view of a second embodiment of the present invention.

FIG. 6 is a view showing an assembling process according to a second embodiment of the present invention.

FIG. 7 is a schematic sectional view of a third embodiment of the present invention.

FIG. 8 is a potential model diagram taken on line AA ′ of a schematic sectional view according to a third embodiment of the present invention.

FIG. 9 is a schematic sectional view of a conventional semiconductor device package.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 Copper substrate 1a LSI chip mounting area 2 Polyimide 3 Copper foil 4 Bonding stitch 4a Wiring pattern 4b, 4c Ball pad 4d Signal wiring 4e GND wiring 5 Ground via 6 LSI chip 7 Bonding wire 8 Solder resist 8a, 8b Pad opening 9 Solder Ball 10 dam 11 sealing resin 11a resin injection port 12 conductive sheet grounding solder ball 13 conductive sheet 13b conductive thin plate 13c conductive plate thick portion 21 electromagnetic field C1, C2 capacitance d1, d2 distance ε1, ε2 dielectric constant GND ground potential

Claims (11)

[Claims] An LSI chip mounted on a metal substrate is sealed with a resin, and a conductive layer is formed on the sealing surface.
A semiconductor package, wherein the conductive layer is electrically connected to a ground potential of a metal substrate by a connection terminal. 2. The LSI chip is mounted on the metal substrate, and a bonding stitch is provided on a wiring provided on the LSI chip and the metal substrate via an insulating layer,
This bonding stitch and the LSI
Bonding between chips, resin sealing means, means for connecting the conductive layer to the metal substrate, bonding the conductive layer to the surface of the resin sealing, electrically connecting the conductive layer and the metal substrate 2. The semiconductor package according to claim 1, further comprising means for connecting. 3. The semiconductor package according to claim 1, wherein the connection between the metal substrate and the conductive layer is through a solder ball. 4. The semiconductor package according to claim 1, wherein said conductive layer is formed of a conductive sheet. 5. The semiconductor package according to claim 1, wherein said conductive layer is formed of a conductive thin plate. 6. The semiconductor package according to claim 5, wherein a sealing resin injection port is provided in the conductive thin plate. 7. The semiconductor package according to claim 5, wherein a portion of said conductive plate corresponding to said wiring pattern is thickened. 8. The LSI chip is mounted on the metal substrate, the LSI chip and the bonding stitch of wiring on the metal substrate are electrically connected by wire bonding, and then the LSI chip on the metal substrate is connected. A sealing resin is applied, and at this time, the sealing resin is an LSI chip,
The resin completely covers the wire bonding so that the tip of the ground connection solder ball on the conductive sheet or the metal thin plate comes out of the resin sealing surface, and the resin passes over the dam provided on the periphery of the metal substrate. Filling, then baking the resin, and then pasting the conductive sheet or the metal thin plate on the surface of the resin sealing, and soldering the ground connection solder so that the conductive sheet or the metal thin plate is at the ground potential. A method for manufacturing a semiconductor package, wherein the method is connected to a ball. 9. The method according to claim 8, wherein the resin baking is performed in a nitrogen atmosphere at about 150 ° C. for about 2 hours. 10. The LSI chip is mounted, wire bonding is performed, then the conductive thin plate is attached, and the electrical connection is performed by soldering the ground connection solder ball. A method of manufacturing a semiconductor package, comprising injecting more sealing resin. 11. The method for manufacturing a semiconductor package according to claim 2, wherein an epoxy-based resin is used for said resin encapsulation.