JP2001332557A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a plating deposition speed for wiring uniform on the entire surface of a wafer, and at the same time to prevent voids and defects from occurring inside the wiring in a semiconductor device-manufacturing process for manufacturing copper wiring by the electric plating method. SOLUTION: The sum (C+D) of intervals C and D in the left and right directions of the wiring is set to 40 times or less larger than that (A+2B) of circumference length A of the bottom surface of a wiring section and circumference length B of both sides, and the volume of the wiring in a square region (20×20 mm) at an arbitrary position on the surface of the wafer is nearly fixed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having copper wiring formed on a wafer surface by electroplating and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, when a copper wiring is formed on a wafer by an electroplating method, as described in Japanese Patent Application Laid-Open No. 9-306914, a plating pattern of a dummy wiring is used in addition to a plating pattern required as a wiring. There has been a method of forming a wiring by plating both patterns at the same time. Further, as disclosed in Japanese Patent Application Laid-Open No. H11-74266, a groove having an inverted trapezoidal cross section is formed on a wafer in accordance with a required wiring shape, and copper is filled therein by plating to form a wiring. There was a method of forming.

[0003]

In the electroplating method, a metal film can be grown only in a concave portion (inside a groove) on a substrate by mixing an additive with a plating solution. Since the metal film is grown only inside the groove, only the groove can be filled with metal, and the production efficiency is high. On the other hand, in this method, since plating current and plating ion diffusion are concentrated only in the groove portion, there is a problem that voids and defects are easily generated in the metal film in the groove.

The first prior art is intended to equalize the plating density over the entire surface of the wafer by adding a dummy wiring pattern. However, in the case of a large-diameter wafer, a plating area and a non-plating area are used. When the area ratio of the metal becomes large, there is a problem that voids and defects occur in the plated metal material.

The second prior art is intended to prevent a metal defect generated at the time of plating by forming a groove in an inverted trapezoidal shape. However, the degree of integration of a semiconductor is increased and the wiring density is increased. There is no consideration of the case where the width of the groove for forming the wiring is narrow and deep, and if the side wall of the groove is inclined, extra space is increased by that amount, so that the integration density cannot be increased. Was.

An object of the present invention is to form a uniform metal wiring without forming voids or defects in the wiring on the wafer surface when copper wiring of a semiconductor device is formed on a wafer by electroplating.

[0007]

Means for Solving the Problems In order to achieve the above object, the present invention employs the following means. Regarding the arrangement of the wiring on the wafer surface and the dummy wiring provided as needed, the sum of the shortest distances between the wiring adjacent to the left and right or the dummy wiring in the same wiring layer at any position in the longitudinal direction of each wiring is The wiring and the dummy wiring are arranged so as to be 40 times or less, preferably 10 times or less, the sum of the perimeters of both sides and the bottom surface of the cross section of the wiring. The wiring on the wafer surface and the dummy wiring provided as necessary are arranged so that the volume of the wiring in a square area of 20 mm square at an arbitrary position on the wafer surface is substantially constant. The cross-sectional shape of the wiring is such that the bottom surface (surface serving as the starting point of plating) is convex toward the substrate side. Regarding the through hole connecting the wirings, the through hole near the connection portion with the wiring is formed in a shape that expands in a tapered shape toward the wiring side.

The above-mentioned constitutions are used alone or in combination.

According to the above configuration, when forming the wiring by the electroplating method, in a small region on the order of μm,
Plating film formation occurs only in the wiring area, but by specifying a numerical upper limit for the wiring interval, it is possible to prevent excessive concentration of plating current in a specific wiring area, prevent defects from occurring, and ensure uniform metallization. Can be wiring.

[0010] According to the above configuration, the plating film grows on average in a large region of the order of mm, but if the volume of the wiring is constant every 20 mm square on the wafer surface, the plating film is required inside. Thus, a plating film can be grown at a uniform rate within the wafer surface.

According to the above configuration, since the bottom surface of the wiring is convex toward the substrate side, large crystal growth from the bottom surface of the groove can be prevented during plating, and the wiring is free from metal material defects. be able to.

According to the above configuration, by forming the vicinity of the connection between the through hole and the wiring tapered, large crystal growth near the connection can be prevented, and voids are generated in the through hole. Can be prevented.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is an enlarged vertical sectional view showing a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a horizontal sectional view taken along line 11-11 of FIG. 1 is a vertical sectional view taken along line 12-12 of FIG.

In the semiconductor device shown in the figure, a large number of transistor elements 2 and resistance elements 3 are formed on the surface of a silicon substrate 1, and these are interconnected 4 (on the order of a cross-sectional dimension of 1 μm).
Are electrically connected to each other to form an electric circuit. The wiring 4 has a rectangular cross section and is made of a metal material such as copper or aluminum, and an insulating film 5 such as a SiO ₂ film is formed around the wiring.
Electrically insulated by In order to form a large number of wiring networks, the wiring layers have a multi-layered structure.

FIG. 3 shows a part of the semiconductor device in the course of manufacture, and is a vertical sectional view taken along line 13-13 of FIG. An insulating film 5 is formed on the substrate 1, and a wiring 6 is formed in the insulating film 5.
Is formed. The surface of the substrate shown in FIG. 3 is covered with a metal thin film (seed film) including the inner surface of the groove 7 by a sputtering method or the like. Such a substrate is immersed in a plating solution and a current is applied to grow a metal film on the surface by electroplating. In this case, the plating mainly starts from the bottom of the groove 7 by the action of the additive.

In this embodiment, the width A (14 in FIG. 3) and the depth B of both side walls (15 in FIG. 3) of the cross-sectional shape of the groove 7 on the substrate, and the same wiring layer When the distance from an arbitrary position in the longitudinal direction of the wiring to the nearest wiring in the horizontal direction is C and D (16 and 17 in FIG. 2), {(C + D) /
(A + 2B)} is set to 40 or less (preferably 10 or less). That is, the sum (C + D) of the distance to the nearest wiring in the horizontal direction of the wiring is set to 40 times or less (preferably 10 or less) the sum (A + 2B) of the circumferential lengths of both side surfaces and the bottom surface of the wiring. . As shown in the horizontal plane of FIG. 2, when the above condition cannot be satisfied only by forming a real wiring required for electric circuit design, a dummy wiring 9 which is not electrically required is formed and {(C + D ) / (A + 2B)} is set to 40 or less (preferably 10 or less).

FIG. 4 is a horizontal sectional view taken along line 18-18 of FIG. At various positions in the longitudinal direction of the wiring, distances C ₁ , D ₁ , C ₂ , to the nearest wiring in the horizontal direction of the wiring,
An example of how to measure D ₂ , C ₃ , D ₃ , C ₄ , and D ₄ will be described.

The conditions for ordinary copper plating with copper sulfate are as follows:
It is on the street. Copper ion diffusion coefficient G = 5 × 10^-Tenm²/ S, copper ion concentration E = 400 mol /
m³The concentration of the substrate surface when the solution in the plating equipment is sufficiently stirred
Degree boundary layer thickness (diffusion layer thickness) δ = 2 × 10^-Fivem, current density per substrate surface area 100A / m²  The copper ion diffusion limit condition (one of the causes of defects) is
It is calculated by the following equation according to the theoretical equation of gas chemistry.

I = nFGE / δ where n: number of electrons involved in the electrode reaction (valence: n = 2 in the case of copper ion), F: Faraday constant (F = 9.65 × 10 ⁴ C / mol) ). From this, the diffusion limit current i is i = 2000 A /
m ^2, which is 20 times the average current density of 100 A / m ² . When the current exceeds the limit current, copper ions are not sufficiently supplied to the surface of the plating film, and voids, cavities and defects occur in the plating film. Therefore, it is desirable to keep the current concentration at 20 times or less.

In this embodiment, {(C + D) / (A + 2
B)} is 40 or less (preferably 10 or less), so that the plating current and the concentration of plating ion diffusion are 20 times or less (preferably 5 times or less).
And the occurrence of voids and defects can be prevented. Since the ratio of the sum (C + D) of the distances to the two closest wirings in the left-right direction and the sum (A + 2B) of the circumferential lengths of one groove is defined, the current concentration is １ ／ of that.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a plan view of the silicon wafer 21. Independent electric circuits are formed on the surface of the wafer 21 for each region 22 of 5 to 10 mm square, and are later cut for every 5 to 10 mm square to be semiconductor devices as LSI chips. The configuration of the electric circuit is shown in FIGS.
This is a set of wirings 4. The electric circuit (LSI chip) for every 5 to 10 mm square may have the same pattern repeated, or there may be a test pattern portion 23. In the present embodiment, when a square area 24 of 20 mm square is drawn at an arbitrary position in each wiring layer on the silicon wafer 21, the total volume of the wiring of the wiring layer inside the square area 24 is determined by the position of the square area. Irrespective of the same value (in this embodiment,
(± 10% of the reference value). If possible, it is desirable that the total volume of the wirings in the 5 mm square area be substantially the same regardless of the position of the square area. In particular, dummy wiring is also formed on the peripheral portion 25 of the wafer and the portion 23 of the test pattern so that the total volume of the wiring is substantially the same regardless of the position of the square area.

In a typical electroplating apparatus, the current density per surface area of the substrate is adjusted so as to have a constant distribution. Therefore, the total amount of the plating film becomes substantially constant within the region of 20 mm square (μm as in the first embodiment).
When considered in the region of, plating film is concentrated locally,
(In a large area of about 0 mm square, the average is obtained.) In this embodiment, since the volume of the wiring is set to be substantially the same for each area of 20 mm square, the film formation rate can be made constant over the entire surface of the wafer.

The effect of the present embodiment is numerically analyzed using a computer under the wiring conditions shown in FIG. 6, and the results are shown in FIG. The condition shown in FIG. 6 is based on a certain position (origin, x
= 0), when there is no wiring on one side, the wiring is formed on the other side with an area ratio of 50%, and the depth and width are assumed to be the same as the shape of the wiring. FIG. 7 shows a calculation result of the variation in the film forming speed when the plating current density is 100 A / m ² . The horizontal axis indicates the distance x (mm), and the vertical axis indicates the variation ratio of the film forming speed. That is, the numerical value on the vertical axis is the variation ratio (%) of the film forming speed between a point having a distance x in the positive direction from the origin and a point having a distance x in the negative direction from the origin. FIG.
According to the graph, it is found that the film forming speed varies at 35% at the point of x = 10 mm. Since the sum of the distances in the positive and negative directions is the total distance, x = 10 mm is a distance of 20 mm. Therefore, by making the volume of the wiring substantially constant in each area of 20 mm square, it is possible to make the variation of the plating film formation rate within 35% (preferably, to keep the volume of the wiring substantially constant in each area of 5 mm square). By doing so, the variation in the plating film forming speed can be made within 10%), and the film can be formed uniformly over the entire surface of the wafer.

A third embodiment of the present invention will be described with reference to FIG. FIG. 8 is a vertical sectional view of a wiring portion of the semiconductor device. The shape of the lower portion 26 of the wiring 4 on the surface of the substrate 1 is a curved surface convex downward. As described above, in the electroplating method, a metal film is grown only in a groove in a substrate by the action of an additive. By making the lower shape of the wiring 4 a curved surface that is convex downward, it is possible to prevent the generation of a large crystal in a uniform direction when the metal film is grown from the lower surface, and to form a dense metal structure with a collection of small crystals. be able to. Also,
By making the lower shape of the wiring 4 a curved surface, there is also an advantage that breakage of the film can be prevented in a seed film forming process by a sputtering method or the like before plating. Further, when a semiconductor device is obtained, there is also an effect of improving electric characteristics of wiring. In the present embodiment, the shape of the wiring lower portion 26 is a curved surface that is convex downward. However, the shape is not necessarily a curved surface but may be a shape including a straight line as long as the shape is convex downward.

A fourth embodiment of the present invention will be described with reference to FIG. FIG. 9 is a vertical sectional view of a wiring portion of the semiconductor device. The wirings 4a, 4b, 4c are arranged in the same wiring layer, the wiring 4d is arranged in a wiring layer therebelow, and the wirings 4e, 4f are arranged in a wiring layer thereunder. The wiring 4b and the wiring 4d, and the wiring 4d and the wiring 4e are
7 are connected. In the present embodiment, the wires 4b, 4
At the bottom surface of d, the shape is slightly inclined in a conical shape only in the vicinity 28 of the through hole 27. In other words,
The connection portion between the through hole and the wiring has a shape that is tapered toward the wiring. Wiring 4b, 4d
Is slightly inclined only in the vicinity of the through-hole 27 at the bottom surface of the through-hole, so that it is possible to prevent the generation of a large-sized crystal at the entrance of the through-hole at the time of growing the metal film by plating. The generation of voids can be prevented.

[0026]

According to the present invention, the electroplating film forming rate for forming the wiring can be made uniform over the entire surface of the wafer, and the production efficiency can be improved. In addition, it is possible to prevent the occurrence of voids and defects inside copper constituting wiring and through holes,
The product yield can be increased.

[Brief description of the drawings]

FIG. 1 is a vertical sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a horizontal sectional view taken along line 11-11 of FIG.

FIG. 3 is a cross-sectional view showing a state in the course of manufacture of a vertical cross-sectional portion taken along line 13-13 of the semiconductor device of FIG. 2;

FIG. 4 is a horizontal sectional view taken along line 18-18 of FIG. 1;

FIG. 5 is a plan view of a silicon wafer according to a second embodiment of the present invention.

FIG. 6 is a cross-sectional view showing an arrangement of wirings for explaining an effect of the present invention.

FIG. 7 is a graph showing an example of a relationship between a variation in plating film forming speed and a width of a region for averaging a wiring volume.

FIG. 8 is a vertical sectional view showing a third embodiment of the present invention.

FIG. 9 is a vertical sectional view showing a fourth embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Transistor element 3 Resistance element 4, 4a-4f Wiring 5 Insulating film 6 Wiring 7 Groove 9 Dummy wiring 21 Wafer 22 5-10mm square electric circuit area 23 Test pattern part 24 20mm square area 25 Wafer periphery Part 26 Lower part of wiring 27 Through hole 28 Lower part of wiring near through hole

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/82 H01L 21/82 W 21/88 S (72) Inventor Hideyuki Yamaguchi Shinmachiroku, Ome-shi, Tokyo F-term (reference) 4K024 AA09 AB01 AB02 AB15 BB12 CB08 CB21 DA10 GA16 4M104 BB04 DD52 FF06 HH13 HH20 5F033 HH11 JJ01 JJ11 KK11 MM01 MM01 MM01 NN32 XX01 PP15 5F064 EE01 EE14 EE15 EE32 EE60 GG10

Claims (6)

[Claims] 1. A method for manufacturing a semiconductor device, comprising the steps of: forming a groove at a wiring position on a substrate and filling the groove with metal by electroplating to form a wiring; Wherein the sum of the closest distances to other wirings in the direction of both sides of the wiring in the same plane as the wiring is the circumferential length of both sides and the lower surface of the groove in a cross section orthogonal to the longitudinal direction of the wiring. A method of manufacturing a semiconductor device, comprising: examining how many times the sum of the sums is, and if the sum is more than 40 times, setting a wiring position so as to be 40 times or less, and providing dummy wires as needed. 2. A semiconductor device comprising the steps of: forming a groove at a position of a wiring and a dummy wiring on a wafer including a plurality of semiconductor chips and filling the groove with metal by electroplating to form the wiring and the dummy wiring. In the manufacturing method, a square area of a predetermined size is set at an arbitrary position on the wafer, and the sum of the volumes of the wiring and the dummy wiring in the area is made uniform regardless of the position of the area. Wherein the position of the dummy wiring is set. 3. A semiconductor device comprising: a substrate; a semiconductor element provided on the substrate; wiring for electrically connecting the semiconductor element; and dummy wiring not functioning as an electric circuit. And the dummy wiring is formed by electroplating. At an arbitrary position in the longitudinal direction of the wiring, another wiring or the dummy wiring in the direction of both sides of the wiring in the same plane as the wiring is provided. The sum of the closest distances is
A semiconductor device, wherein the sum is 40 times or less the sum of the circumferential lengths of both side surfaces and the lower surface in a cross section orthogonal to the longitudinal direction of the wiring. 4. In a semiconductor device including a plurality of semiconductor elements provided on a wafer and wirings for electrically connecting the semiconductor elements, dummy wirings not connected to the semiconductor elements are arranged on the wafer. When a square area having a side of 20 mm is set at an arbitrary position on the wafer, the sum of the volumes of the wiring and the dummy wiring existing in the square area is substantially constant regardless of the position of the square area. A semiconductor device, comprising: 5. A semiconductor device comprising: a substrate; a semiconductor element provided on the substrate; and a wiring for electrically connecting the semiconductor element, wherein the wiring is formed by electroplating. A semiconductor device, wherein a surface shape of the wiring on an inner side of the substrate is a shape protruding in an inner direction of the substrate. 6. A semiconductor comprising: a substrate; a semiconductor element provided on the substrate; and a plurality of layers of wiring for electrically connecting the semiconductor element, wherein the wiring is formed by electroplating. In the device, a through hole for connecting the wiring to a wiring of another layer is provided, and at a connection portion between the through hole and the wiring, the through hole has a shape that is enlarged toward the wiring side. Characteristic semiconductor device.