JP2001331475A - Vector instruction processor and vector instruction processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the first problem that the speed of a vector instruction is suppressed since the flash processing of a cache is slower than the throughput of the storage processing of the vector instruction itself and the second problem that flash is performed even to data which are not the object of the flash since the data of plural bytes are registered to one cache line in a communication cache. SOLUTION: This processor is provided with a main storage means for storing the data, an instruction discrimination means for discriminating whether an effective object instruction is the vector instruction or not, an address generation means for generating an address in the main storage means for the processing data of the vector instruction when it is discriminated that it is the vector instruction by the instruction means, the storage register of the processing data and an instruction performance means for performing data transfer between the register and the address generated by the address generation means without performing cache flash.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a vector instruction processing device and a vector instruction processing method.

[0002]

2. Description of the Related Art In a conventional vector instruction processing apparatus and vector instruction processing method, since a vector instruction transfers a large amount of data at a time, a vector storage directly accesses a main storage unit without accessing a cache. However, usually, when performing some operation, scalar operation and vector operation are mixed, and in the scalar operation, the operation is executed using cache data. Therefore, in order to maintain consistency between the cache and the main storage unit in consideration of a case where common data is handled by the scalar operation and the vector operation, all store data is simultaneously written to the cache and the main storage unit. In.

[0003]

The above-described conventional vector instruction processing apparatus and vector instruction processing method have the following two problems in order to maintain the above consistency. The first problem is that the cache flush process is slower than the throughput of the vector instruction store process itself, so that the cache flush process becomes a bottleneck and the speed of the vector instruction is suppressed. The second problem is that the cache usually has a plurality of bytes of data registered in one cache line, and therefore, also flushes data that is not to be flushed. That is, since flushing is performed in units of cache lines, even if only one byte in a cache line is to be flushed, all other data is flushed.

As techniques for solving the first problem, Japanese Patent Application Laid-Open Nos. Hei 5-20190 and Hei 9-2514 are known.
No. 24 discloses a method of speeding up flash processing by hardware. However, this method still had a second problem.

The present invention has been made in view of the above problems, and provides a vector instruction processing device and a vector instruction processing method for solving both the first problem and the second problem.

[0006]

In order to achieve the above object, according to the first aspect of the present invention, there is provided a main storage unit for storing data, and an instruction determining unit for determining whether an instruction to be executed is a vector instruction. An address generating means for generating an address in the main storage means for processing data of the vector instruction when the instruction determining means determines that the processing instruction is a vector instruction; and a register for storing the processing data. And an instruction executing means for executing data transfer between the register and the address generated by the address generating means without performing cache flush.

More specifically, when data is exchanged between a register and data stored in a cache or a main storage unit to execute processing for various instructions, the present invention employs a cache flash when processing for vector instructions is performed. Is configured not to execute. Therefore, in the present invention, data is stored in the main storage means, and the instruction determination means determines whether or not the instruction to be executed is a vector instruction.

The processing data is stored in a register. When the instruction determining means determines that the instruction is a vector instruction, the address generating means stores the processing data of the instruction in the main storage means. Generate the address at Then, the instruction executing means exchanges data between the register and the address generated by the address generating means without performing cache flush. Therefore, the throughput at the time of executing the vector instruction can be improved.

According to a second aspect of the present invention, in the vector instruction processing device according to the first aspect, the instruction determining means determines whether or not the instruction is a vector instruction by a code indicating the vector instruction. This is a configuration for determining. That is, in the present invention, a code indicating a vector instruction is newly provided in order to omit the cache flush processing performed in the above-described conventional example.
Therefore, by performing the vector processing according to the present invention in accordance with the code, the processing according to the present invention can be easily started in the processing of a series of programs.

More specifically, a vector store and a vector scatter that do not perform cache flush at the instruction set level, and a scalar load instruction and a scalar store instruction that do not register data in the data cache are newly prepared. It is possible to eliminate the need to consider the consistency, thereby improving the throughput and speeding up the processing. Further, by newly providing a new instruction, it is possible to execute a processing method involving a cache flush as necessary, as required.

Further, even if the processing according to the present invention is executed while being determined by the code, various configurations are possible to generate such a code at a high-level language level. According to a third aspect of the present invention, in the vector instruction processing device according to any one of the first to second aspects, the variable handled in the instruction to be executed in a high-level language is a variable for vector processing. Is a configuration that can be declared.
That is, according to such a configuration, it is only necessary to specify a variable type in order to perform the vector instruction processing as in the present invention, and the programmer can very easily execute the processing without performing the cache flush.

According to a fourth aspect of the present invention, in the vector instruction processing device according to the second or third aspect, the instruction to be executed is a vector instruction and the variable declared above is handled. Is compiled to obtain a code indicating the vector instruction. That is, it is possible to generate an instruction set for performing the vector processing while providing an environment in which a programmer can easily select a process in which cache flush is not performed.

According to a fifth aspect of the present invention, in the vector instruction processing device of the first to fourth aspects, the instruction executing means transfers the address generated by the address generating means for cache flash. By doing so, the cache flush is not performed.

That is, in normal scalar instruction processing and the like, the generated address is transferred for cache flush, and when a search for a transfer address hits, the valid bit is invalidated to enable the cache to be flushed. Perform a flush. Therefore, in the present invention, the cache flush itself is not performed by not performing such an address transfer for the cache flush. Therefore, it is possible to execute the vector processing without performing the cache flush simply by adding the configuration according to the present invention to the existing hardware.

Further, the invention according to claim 6 is a vector instruction processing method for processing data transfer between a main storage unit and a register by a vector instruction, wherein the execution target instruction is a vector instruction. When it is determined that the instruction to be executed is a vector instruction, an address for processing data is secured in the main storage unit, and data transfer between the register and this address is performed without performing a cache flush. There is a configuration to execute. That is,
It is not necessarily limited to a substantial device, and there is no difference that the method is effective.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic block diagram showing a vector instruction processing device according to an embodiment of the present invention. In the figure, a scalar unit 120 mainly related to processing of a scalar instruction and a vector unit 130 mainly related to processing of a vector instruction are shown. Further, the main storage unit 110 stores processing data of the instruction to be executed, instructions, and the like.

The scalar unit 120 includes an instruction cache 100, an instruction fetch unit 101, and an instruction decode unit 102.
A scalar register 103, a data cache unit 104, and a flash address search unit 105. The instruction cache 100 is a buffer for caching instructions. The instruction fetch unit 101 reads an execution target instruction from the instruction cache 100 or the main storage unit 110, and the instruction decode unit 102 decodes the execution target instruction read by the instruction fetch unit 101. Further, whether or not the decoded instruction is a vector instruction is determined based on the code. When the decoded instruction is determined to be a vector instruction, the instruction is sent to the vector unit 130.

On the other hand, if the decoded instruction is a scalar load instruction or a scalar store instruction, it is sent to the data cache unit 104. The data cache unit 104 is a cache for a scalar register. The flash address search unit 105 determines a cache hit or mishit for the input cache flash address. Here, if the search hits, the data is transferred from the data cache unit 104 to the scalar register 103, and if the search hits, the main storage unit 110
Is transferred to the scalar register 103. The scalar register 103 is a register used to execute a scalar operation other than a vector operation, and is used to exchange data when executing a scalar instruction.

The vector unit 130 includes an address generator 106, a vector load / store controller 107, a vector register 108, and a vector calculator 109. The address generation unit 106 is a part of the instruction decoding unit 1
An address of the processing data in the main storage unit 110 is generated in accordance with the instruction output from the main unit 02. The vector register 108 is a register used to execute a vector operation, and can store a plurality of elements per register. The vector load / store control unit 107 stores the vector register 108 and the main storage unit 11 with respect to the main storage address generated by the address generation unit 106.
Controls the execution of vector loads between 0 and vector stores.

As described above, in the present embodiment, the main storage unit 110 constitutes the main storage unit, the instruction decoding unit 102 constitutes the instruction determination unit, and the address generation unit 1
06 constitutes the address generation means, the vector register 108 constitutes the register, and the vector load / store control section 107 constitutes the instruction execution means.

Next, the processing in such a configuration will be described using a specific FORTRAN program as an example.
FIG. 2 shows a FO for performing vector processing according to the present invention.
It is an example of a RTRAN program. In the figure, 2
Lines 00 and 201 declare variable types. D
In line 200, which is an IMENSION statement, array B (I),
The types of C (I) and IA (I) are declared, and these are declared as ordinary arrays. On the other hand, in order to perform the vector processing according to the present invention in the present embodiment, it is sufficient to declare a variable as a vector type, and the declaration statement for that is the VDIMENTION statement in the 201st line.

The VDIMENTION statement 201 is an array declaration statement newly established in the present invention. When an array declared by this statement is accessed, a different instruction set is used depending on whether the accessing instruction is a scalar instruction or a vector instruction. Compiled as: That is, if the instruction is a scalar load instruction or a store instruction, the compiler outputs a scalar load instruction (LDSN) and a scalar store instruction (STSN) that do not register data in the data cache. On the other hand, in the case of a store instruction for a vector register, the compiler outputs a vector store instruction (VSTN) that does not perform cache flush processing.

A vector store instruction and a vector load instruction directly access the main storage unit 110 without accessing the data cache unit 104 in order to transfer a large amount of data at a time. On the other hand, for a normal scalar store instruction that is not a vector instruction, when the data cache unit 104 is configured as a store-through cache,
No need to consider cache coherency. However, when the vector store instruction directly rewrites the contents of the main storage unit 110, there is a possibility that the contents of the data cache unit 104 and the contents of the main storage unit 110 may be inconsistent. At this time, it is necessary to consider the coherency of the cache. is there.

Therefore, when a vector store instruction (VST) or a vector scatter instruction (VSCN) is executed, an address to be stored in the main storage unit 110 is stored in the data cache unit 104 in order to prevent inconsistency in the cache data. Search for the existence. And
When the corresponding address exists in the data cache unit 104, a process of invalidating the cache line of the address is performed. VSTN instruction and VS newly established in the present invention
The CN instructions are a vector store instruction and a vector scatter instruction in which the process of invalidating the cache is omitted. The LDSN instruction and the STSN instruction are a scalar load instruction and a scalar store instruction that do not pass through a cache.

In the loop shown at 202 in FIG.
(I), C (I) and IA (I) are initialized, and 20
The loop shown in FIG. 3 is the actual operation. In the loop shown in 202, “I” is a variable indicating the repetition of the loop,
"I" loops to "1-3". Array B
The variable “I” is assigned to (I), “I + 3” is assigned to array C (I), and “I * I *” is assigned to array IA (I).
100 ”is substituted. Therefore, through this loop, each array value becomes a value shown in FIG.

In the loop indicated by 203, the elements of the array B (I) and the elements of the array C (I) are added, and the VDIMEMSI
Assign to the array A (I) declared by the ON statement. Further, in this example, after exiting the loop shown by 203, the variable E is set to A
The value obtained by adding the value of (100) and the value of A (400) is substituted. FIG. 4 shows a part of the assembler code output by compiling such a FORTRAN program. FIG. 5 shows values stored in the main storage unit 110 and values stored in the vector register 108 by the program. ing.

Here, the VLD instruction is a vector load instruction, in which the address specified by the third operand is set as the start position on the main memory, the value specified by the second operand is set as the distance, and the first operand is specified. Is stored in each element of the registered vector register 108. The VFAD instruction is
The operand and each element of the vector register of the third operand are added and stored in the vector register of the first operand. The VSCN instruction sequentially stores each element of the vector register specified by the second operand in a memory location whose execution address is each element of the vector register specified by the first operand.

The LDSN instruction stores the data at the memory location of the second operand in the scalar register of the first operand. This instruction always loads data directly from the main storage unit 110, and the loaded data is not registered in the data cache. The ADD instruction adds the values of the scalar registers of the second and third operands and stores the result in the scalar register of the first operand. When the program is executed, each instruction is read from the instruction cache 100 or the main storage unit 110 in FIG. 1, and the read instruction is sent to the instruction decoding unit 102.

If the instruction decoded by the instruction decoding unit 102 is found to be a vector instruction, the instruction is sent to the vector unit 130. That is, the VLD of FIG.
The instruction is sent to the vector unit 130. As described above, the VLD instruction stores data at a predetermined position on the main memory in the vector register 108, and the first VLD instruction stores the data at the position S in the main storage unit 110 shown in FIG.
The values are extracted in order from 50, and V
0 is stored. In the second VLD instruction, the values after the position S51 are sequentially stored in V1 of the vector register 108,
In the third VLD instruction, the values after the position S52 are sequentially stored in V2 of the vector register 108 (step A).
1). That is, the values shown in FIG. 3A are stored in the vector register 108.

Subsequently, the VFAD instruction shown in FIG.
And V1 are added and stored in V3 (step A2). Next, the left side A in the loop shown by 203 in FIG.
As a process corresponding to the substitution into (IA (I)), V in FIG.
The SCN instruction is executed. Since the array access here is for array A in FIG. 2, the VSCN instruction 202, which is a vector scatter instruction that does not access the cache, is executed. When this instruction arrives at the address generation unit 106 of the vector unit 130 shown in FIG. 1, the flash address is not transferred unlike the conventional instruction, and only the transfer of the vector register 108 and the main storage unit 110 is performed (step A3). . That is, FIG.
As shown in (1), the result of each sum is stored in the main storage unit 110 at an address corresponding to the subscript of the array A.

In this way, the loop indicated by 203 in FIG. 2 has been executed, and finally, the sum shown in line 204 is calculated. Reference numeral 303 in FIG. 4 is an instruction corresponding to this addition. Since the array access here is for array A in FIG. 2, an LDSN instruction that does not access the cache is output by the compiler. Therefore, LD
When the SN instruction is output to the address generation unit 106, the data is directly loaded from the main storage unit 110 without accessing the cache, and the data is stored in the scalar register. At this time, since no data is registered in the cache, it is not necessary to consider the coherency of the cache even if a vector store instruction or a vector scatter instruction is executed again on data at the same address in the future. Using this result, the addition between the scalar registers is performed by an ADD instruction, and a predetermined addition result is substituted for a variable E.

As described above, according to the present invention, in a vector instruction processing method for processing data transfer between a main storage unit and a register by a vector instruction, it is determined whether an instruction to be executed is a vector instruction, When it is determined that the instruction to be executed is a vector instruction, an address for processing data is secured in the main storage unit, and data transfer between the register and this address is performed without performing cache flush. Therefore, the speed of vector instructions is not suppressed by cache flush, and
Processing for a vector instruction can be executed without unnecessary flushing.

[0033]

As described above, according to the present invention, since an instruction is executed without performing cache flush, the throughput at the time of executing a vector instruction can be improved. According to the second aspect of the present invention, the processing according to the present invention can be started easily in the processing of a series of programs. Furthermore, according to the third aspect of the present invention, the programmer can very easily execute the process without performing the cache flush.

Further, according to the invention of claim 4,
An instruction set for performing the vector processing can be generated while providing an environment in which a programmer can easily select a process in which cache flush is not performed. Further, according to the fifth aspect of the present invention, it is possible to execute vector processing that does not perform cache flushing by merely adding the configuration according to the present invention to conventional hardware. Furthermore, according to the invention of claim 6, since the instruction is executed without performing the cache flush, the throughput at the time of executing the vector instruction can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a vector instruction processing device according to an embodiment of the present invention.

FIG. 2 shows an F for performing vector processing according to the invention;
It is an example of an ORTRAN program.

FIG. 3 is a diagram showing values of array variables.

FIG. 4 shows a part of assembler code output by compiling a FORTRAN program.

FIG. 5 is a diagram showing values stored in a main storage unit and values stored in a vector register.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 instruction cache 101 instruction fetch unit 102 instruction decode unit 103 scalar register 104 data cache unit 105 flash address search unit 106 address generation unit 107 vector load / store control unit 108 vector register 109 vector operation unit 110 main storage unit 120 scalar unit 130 vector unit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 12/08 G06F 12/08 310A 9/30 340A 310 9/44 322G

Claims (6)

[Claims] A main storage unit for storing data; an instruction judging unit for judging whether or not the instruction to be executed is a vector instruction; and when the instruction judging unit judges that the instruction is a vector instruction, An address generating means for generating an address in the main storage means for processing data of the vector instruction; a register for storing the processing data; and a register generated by the register and the address generating means without performing a cache flush. A vector instruction processing apparatus, comprising: an instruction executing means for executing data transfer with an address. 2. The vector instruction processing device according to claim 1, wherein the instruction determining means determines whether the instruction is a vector instruction based on a code indicating the vector instruction. Instruction processing unit. 3. The vector instruction processing apparatus according to claim 1, wherein a high-level language can declare that a variable handled by the execution target instruction is a variable for vector processing. A vector instruction processing device characterized by the above-mentioned. 4. The vector instruction processing device according to claim 2, wherein the instruction to be executed is a vector instruction and the vector instruction is a vector instruction by compiling when handling the declared variable. A vector instruction processing device, which obtains a code indicating the fact. 5. The vector instruction processing device according to claim 1, wherein the instruction executing means does not perform cache flush by not transferring an address generated by the address generating means for cache flush. A vector instruction processing apparatus characterized in that: 6. A vector instruction processing method for processing data transfer between a main storage unit and a register by a vector instruction, comprising: determining whether an instruction to be executed is a vector instruction; A vector for securing a processing data address in the main storage unit when the instruction is determined to be a vector instruction, and executing data transfer between the register and this address without performing cache flush; Instruction processing method.