JP2001331441A - Constitution circuit for stipulating one or more virtual ports and integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a constitution circuit for stipulating a virtual port on a data bus capable of receiving narrow data by the virtual port without wasting a data pin. SOLUTION: A constitution input/output circuit is provided with plural constitutable input/output elements and one of the plural bits of the data bus is connected to corresponding one input/output terminal for the respective input/ output elements. Plural clock selection signals and programmable enable signals can be connected to different interface elements and the activation of the connected interface element is controlled. The activated interface element constitutes the virtual port which can be an optional bit width equal to or less than the fixed width of a physical port. Thus, the virtual port narrower than the physical port is constructed on the data bus so as to utilize the narrower data inside the port without wasting any latent uses of the data pin.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a microcontroller, and more particularly, to a connection between a data bus and input / output terminals.

[0002]

BACKGROUND OF THE INVENTION Many microcontrollers have ports that allow a programmer to move data to and from the chip. Typically, these ports are connected to the rest of the system by a bus as shown in FIG. In the prior art system 100 shown in FIG.
10 and an address bus 111, which are connected to a fixed-width (16-bit) port by a two-part bus. The address on the address bus 111 is
Decoded by one of the 20 to enable an input or output port. The addresses corresponding to these ports are fixed. Input data is input / output (I
/ O) Received by one of the pads 180 and going through buffer 136 to input register 128. Clock 115 and other signals are input to multiplexer 116, which multiplexes them into input register 1
28. Clock 115 and other signals received at input register 128 may be selected from a variety of sources, which may be internal or external to the microcontroller. Enable signal 140 from one of decoders 120 enables input data to be received on data bus 110 through tri-state buffer 124. Output data transferred from data bus 110 to input / output pad 180 first passes through one of output latches 132. The output enable signal 141 from one of the decoders 120 is output from the latch 1
32 through buffer 138 to input / output pad 180. Output latch 132 and input register 128 comprise storage and can be replaced by other types of storage means, such as FIFO registers.

The prior art system of FIG. 7 works well for 16-bit wide data, but is not very efficient for narrower data. For example, if the microcontroller is a 10-bit wide CC
If data is to be read from the D imaging device, all 16-bit ports must be occupied for input even though only ten pins are used, and the other six pins of the port are It cannot be used for any purpose and is substantially lost. Although FIG. 8 shows only a prior art input port, the output port is essentially an input port except that an enable latch may be used instead of a register as in FIG. The same is true. In the prior art, all bits in a byte (8 bits) have the same clock signal and also have the same fixed enable signal to the bus. Thus, there are no more than two fixed enable signals and no more than two clock selection mechanisms per port. 8, the first enable signal 143 and the first clock select signal 151 correspond to bits 0-7 of the data bus 110.
, While the second enable signal 144 and the second clock select signal 152 control bits 8-15 of the data bus 110. Fixed enable is 1
If there is only one, the port must be read and written as a 16-bit entity.
Thus, in the prior art, unless the data is constructed as an 8-bit entity or as a 16-bit entity, there will be extra unused pins in the port, and the maximum capability of the port will be completely reduced. It will not be used.

[0004] US Patent No. 4,758,746 to Birkner et al. Discloses that an output term can be assigned to a selected pin via a programmable bus.
A programmable logic array having individually programmable output pins is provided. U.S. Pat. No. 5,872,463 to Pederson discloses a programmable logic device in which each output bus conductor can be connected to one or more output drivers to make efficient use of the provided output drivers. . US Patent No. 5,8 to Shieh et al.
No. 04,985 discloses an output bus with 16 different output configurations for providing a suitable signal interface to peripheral devices. However, only one enable signal is provided to the device.

It is an object of the present invention to define a virtual port on a data bus that can be narrower than a physical port so that the virtual port can accept narrower data so that there are no unused data pins. The purpose of the present invention is to provide a configuration circuit that performs the following.

It is a further object of the present invention to provide a configuration circuit that defines a virtual port that can span two physical ports to allow more flexible use of microcontroller pins.

[0007]

SUMMARY OF THE INVENTION The object described above is a configuration circuit for an integrated circuit having a plurality of configurable input / output interface elements, each configurable input / output interface element comprising:
This is achieved by a configuration circuit for an integrated circuit that connects one of a plurality of bits of a data bus to a corresponding one of the input / output terminals. A plurality of clock select and programmable enable may be connected to different interface elements, each of the clock and programmable enable being configured to control activation of an interface element to which they are connected. The activated interface element constitutes a virtual port which can be any bit width less than or equal to the fixed bit width of the physical port.

In the constituent circuit of the present invention, one bit to one bit
Multiple virtual ports up to 6 bits wide can be programmed. Further, if two physical ports are available, a virtual port may be created from some upper bits of one port and some lower bits of a second port. In this way, a virtual port can be constructed starting from any bit position and having any width less than or equal to the width of the data bus, thereby allowing more flexible use of microcontroller pins.

[0009]

DETAILED DESCRIPTION With reference to FIG.
5 includes a plurality of input / output interface elements 67 connected between the data bus 10 and the input / output pads 68.
Although only the input section of the input / output interface element 67 is shown in FIG. 1, the configuration of the output section operates in essentially the same manner. As in the prior art circuit of FIG. 7, the output may use a latch activated by an enable signal instead of the register 28 and the buffer 24.
Further, the output latch and input register 28
It can be replaced by another kind of storage means such as an O register. Each interface element 67 includes an input register 28 connected to one of the bits of data bus 10 and receiving data from input / output pad 68. Clock 15
And other input / output signals are provided to input register 28 through multiplexer 16 having clock select line 500. Data is programmable enable 4
Go to the data bus 10 through the tri-state buffer 24 activated by 00. As shown in FIG. 1, the main difference between the present invention and the prior art circuit described above is that each bit in the data bus has an interface element 67 controlled by a different clock select line and a different programmable enable line. It is a point that it has.
For example, bit 0 has an interface element controlled by select line 500 and programmable enable signal 400, and bit 1 has select line 501.
And an interface element controlled by a programmable enable signal 401, and bit 2 includes a select line 502 and a programmable enable signal 40.
2 having an interface element controlled by ...
Bit 15 has an interface element controlled by select line 515 and programmable enable signal 415. All interface elements 67 activated by a particular select line and the programmable enable signal define the bits of the virtual port. In the case of FIG. 1, 16 different select lines 50
0-515 and programmable enable signal 400
~ 415, so 16 different virtual ports
It can be mapped to a 6-bit bus. Thus, virtual ports of various sizes are possible. If, for example, the same select and enable signals are provided for bits 2-7, a 6-bit wide virtual port could be achieved. The second set of select and enable signals provided on bits 9-13 will achieve a second virtual port having a width of 5 bits. As will be appreciated, multiple virtual ports 1 to 16 bits wide can be programmed as long as the total number of bits is less than the width of the bus.

Referring to FIG. 5, the input / output interface element 67 of FIG. 1 including the output section is shown. The complete input / output interface element 67 includes an input latch described with reference to FIG. 1 above, as well as an output latch 32 that receives data from the data bus and sends data to the input / output pad 68. The output latch is controlled by the output enable signal 600. The input / output interface element 67 for each bit may have a different output enable signal for controlling each latch 32, as described above with reference to the enable signal for controlling the buffer 24 at the input of the circuit.

The invention, in its most general form, allows up to 16 virtual ports to be mapped to a 16-bit bus, which requires a programmable decoder for each bit. And such programmable decoders can be expensive for some applications. Since it is unlikely that virtual ports need to be less than 6 bits wide, a preferred embodiment of the present invention uses a more economical aspect of implementing the present invention, where there are three programmable enable signals per physical port. I can do it. Referring to the configuration circuit 77 of FIG. 2, the tri-state buffer 24 of each input / output interface element 67 has three possible enable signals E.
An enable signal is provided which can be one of n0, En1 or En2. The enable signals En0, En1, and En2 are provided as data inputs to a multiplexer 17 for selection of a desired enable signal. Configuration bit 30 is provided as a data select for multiplexer 17, and there are two possible configuration bits for each input / output interface element. In this example,
Three virtual ports within a 16-bit bus are possible, which allows greater flexibility than prior art fixed bit width physical ports. In FIG. 6 showing the complete input / output interface element 67 of the embodiment of FIG. 2, each output latch 32 has three possible output enable signals OE.
It can be seen that an output enable signal, which can be one of 0, OE1, or OE2, is provided. The output enable signals OE0, OE1, and OE2 are supplied as data inputs to the multiplexer 23 for selection of a desired output enable signal. Configuration bit 31 is provided as a data select for multiplexer 23. The configuration bit 31 for the multiplexer 23 of the latch 32 is
The configuration bits may be the same as configuration bits 30 for multiplexer 17 for buffer 24, or each set of configuration bits 30, 31 may be generated separately. if,
If the configuration bits are generated separately, the configuration bits must be identical so that the combined enable signal (ie, En0 and OE0) is selected.

In the present invention, if two physical ports are available, a virtual port can be created from some upper bits of one physical port and some lower bits of a second physical port. Therefore, a virtual port having an arbitrary width equal to or less than the width of the data bus can be constructed starting from an arbitrary bit position. The ability to create virtual ports using adjacent ports allows creating ports of different widths without wasting any data pins, but the data in virtual ports created from adjacent physical ports Is often difficult to use. Referring to FIG. 3A, the last 3 bits 212 of the first physical port and the first 4 bits 2 of the next physical port
11 to create a 7-bit virtual port. Thus, data bus 210 has valid bits V0, V1 and V2 in bits 13-15 of the bus.
The valid bits V3, V4,
V5 and V6, where Vn is the nth bit of the virtual port. This form of data is difficult to use. However, FIG. 3B shows the data bus 210 after the data has been rotated by three bits. As you can see from the figure,
The 7-bit virtual port 225 is connected to bits 0-
6 are aligned together and this data is much easier to use. Bit rotation can be performed by adding a rotating unit to the bus.

Referring to FIG. 4, five virtual ports 90-9
4 are created and virtual ports 90-94 overlap four physical ports 80-83. The configuration circuit 7 shifts the bits in the virtual port so that the data can be easily used.
6, a rotation circuit is added. An address bus 11 is coupled to the program decoder 20, which supplies addresses to the rotating RAM 18. Rotation RA
M18 is a RAM of (n × 4) bits, which is connected to the rotation circuit 19, and the rotation circuit 19 transfers data to the data bus 1
Shift data from 0 based on command received from capture processor 12. Rotation circuit 19 can be a barrel shifter circuit or any other type of circuit that can shift data by n positions. Decoder 20 for RAM 18 should be programmed to select the word in rotating RAM 18 that corresponds to the virtual port. Further, when processor 12 writes to a virtual port instead of reading from the virtual port, the direction of rotation will be reversed.

The present invention allows the use of more flexible microcontroller pins than is achieved in the prior art. Rather than requiring the use of standardized 8-bit and 16-bit sized data ports, the present invention addresses narrower data without wasting any of the data pins in the physical port. Allows customization of virtual ports within physical ports. Further, the present invention allows the creation of virtual ports that overlap two adjacent physical ports, thereby allowing greater versatility in the use of microcontroller pins.

[Brief description of the drawings]

FIG. 1 is a circuit-level schematic diagram of a configuration circuit for defining a virtual port according to the present invention.

FIG. 2 is a circuit-level schematic of a preferred embodiment of the circuit of FIG. 1;

FIG. 3A is a diagram of a virtual port before bit rotation, and FIG. 3B is a diagram of a virtual port of FIG. 3A after bit rotation.

FIG. 4 is a block-level schematic diagram of an embodiment of the present invention where a virtual port overlaps a physical port and the constituent circuits include a rotating circuit.

FIG. 5 is a circuit-level schematic diagram of an input / output interface element for the configuration circuit of FIG. 1;

6 is a circuit-level schematic diagram of an input / output interface element for the configuration circuit of FIG. 2;

FIG. 7 is a circuit-level schematic diagram of a microcontroller system known in the prior art.

8 is a circuit-level schematic of a circuit for a physical port in the system of FIG. 5;

[Explanation of symbols]

10 data bus, 15 clock signal, 16 multiplexer, 24 tristate buffer, 28 register, 67 input / output interface element, 68 input / output pad, 400 to 415 programmable enable signal, 500 to 515 clock select line.

Continued on the front page F term (reference) 5B061 FF02 GG14 SS04 5J056 AA01 AA04 AA11 BB53 CC00 CC18 FF01 FF07 FF08

Claims (20)

[Claims] An integrated circuit of a type having a fixed bit width bus for transmitting information, a plurality of input / output terminals, and a plurality of physical ports, wherein each physical port has a fixed bit width. A configuration circuit for defining one or more virtual ports in an integrated circuit of a type having a width and connecting a bus to a corresponding set of input / output terminals, comprising: a plurality of configurable input / output interface elements;
Each interface element includes storage means for connecting one of a plurality of bits of the bus to one corresponding input / output terminal;
The configuration circuit further includes at least one selectable clock connected to the storage means of each interface element, and at least one programmable enable connected to each interface element, wherein the plurality of clocks and the programmable enable comprise an interface. The clock and the programmable enable may each be configured to control activation of an interface element to which it is connected, and the activated input / output element may be connected to a different one of the elements. Wherein the virtual port is any bit width less than or equal to the fixed bit width of the physical port. 2. The circuit of claim 1, wherein said virtual port comprises a set of bits completely contained within a single physical port. 3. The configuration circuit according to claim 1, wherein said virtual port includes a first set of bits from a first physical port and a second set of bits from a second physical port. . 4. The configuration circuit according to claim 3, further comprising a rotation circuit for shifting bits in a desired order. 5. The rotating circuit includes a barrel shifter circuit.
The configuration circuit according to claim 4. 6. The configuration circuit of claim 1, wherein three separate programmable enables are connected to each interface element in a single physical port. 7. The first virtual port comprises an interface element selected by a first programmable enable, the second virtual port comprises an interface element selected by a second programmable enable, 7. The configuration circuit according to claim 6, wherein the third virtual port is configured by an interface element selected by a third programmable enable. 8. The configuration circuit according to claim 1, wherein said storage means includes an input register. 9. The configuration circuit according to claim 1, wherein said storage means includes an output latch. 10. The configuration circuit according to claim 1, wherein said storage means includes a FIFO register. 11. An integrated circuit, comprising: a bus having a fixed bit width for transmitting information; a plurality of input / output terminals; and a plurality of physical ports, each physical port having a fixed bit width. A plurality of configurable input / output interface elements having a width, each interface element including storage means for connecting one of a plurality of bits of the bus to a corresponding one of the input / output terminals; In addition, the plurality of clocks and the programmable enable include at least one selectable clock connected to the storage means of each interface element, and at least one programmable enable connected to each interface element and paired with the clock. Can be connected to several different interface elements, each clock and The programmable enable may be configured to control activation of an interface element to which they are connected, wherein the activated input / output element configures a virtual port, the virtual port being equal to or less than a fixed bit width of the physical port. An integrated circuit of any bit width. 12. The integrated circuit of claim 11, wherein said virtual port comprises a set of bits completely contained within a single physical port. 13. The virtual port comprises a first set of bits from a first physical port and a second set of bits from a second physical port.
The integrated circuit of claim 11, comprising: 14. The integrated circuit according to claim 13, further comprising a rotation circuit for shifting bits in a desired order. 15. The integrated circuit according to claim 14, wherein said rotation circuit includes a barrel shifter circuit. 16. The integrated circuit of claim 11, wherein three separate programmable enables are connected to each interface element in a single physical port. 17. The first virtual port comprises an interface element selected by a first programmable enable, the second virtual port comprises an interface element selected by a second programmable enable, 17. The integrated circuit according to claim 16, wherein the third virtual port comprises an interface element selected by a third programmable enable. 18. The circuit according to claim 11, wherein said storage means includes an input register. 19. The circuit according to claim 11, wherein said storage means includes an output latch. 20. The circuit according to claim 11, wherein said storage means includes a FIFO register.