JP2001312899A - Memory pause device and memory pause method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize a test by reducing a current flowing at the time of memory pause test, to perform plural memory pause tests simultaneously and quickly, and to easily detect a memory in which a fault exists in LSI where plural memories are mounted. SOLUTION: Data for test is inputted successively to each memory block 21-23 from each input terminal 101-103 utilizing a control circuits 5 incorporating flip-flop circuits 51-53 and selectors 31-39. Thereby, each memory is enabled to have an enable state and a disable state in chip-select(CS). Further, an exclusive OR circuit and an OR circuit being not illustrated are used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test for a semiconductor circuit, and more particularly to a memory pause test for performing a pause test on an internal memory.

[0002]

2. Description of the Related Art FIG. 1 shows a circuit for a pause test in a conventional semiconductor device. In the figure, reference numeral 100 is an overall diagram of a circuit for performing a memory pause test. 2 is an internal circuit, and 21 is a first circuit attached to this internal circuit.
And 22 is a second memory in the same manner.
101 is a first input terminal, and S101 is its input signal. 102 is a second input terminal, S10
2 is the input signal. 103 is a third input terminal, and S103 is the third input signal. 104
Is an input terminal of a selector selection signal, and S104 is the select signal.

In step S211 a first output from the internal circuit 2 is performed.
Address signal. S212 is the first input data (signal) output from the internal circuit. S213 is a first control signal output from the internal circuit to control read / write (R / W) of the first memory 21. S20
1 is a first output signal output from the internal circuit.

In step S221, a second output from the internal circuit 2 is output.
Address signal. S222 is a second input data signal output from the internal circuit. S223 is a second control signal output from the internal circuit to control read / write of the second memory 22. S202 is a second output signal output from the internal circuit.

Reference numeral 31 denotes an input (upstream) first selector for selecting a first input signal S101 and a first address signal S211 by a select signal S104. S3
Reference numeral 11 denotes an address signal output from the selector 31. Reference numeral 32 denotes a second selector on the input side that selects the second input signal S102 and the first input data signal S212 by the select signal S104. S321 is input data output from the selector 32. 33
Is a third selector on the input side that selects a third input signal S103 and a first control signal S213 for controlling read / write of the first memory 21 by a select signal S104. S331 is a read / write signal output from the selector 33.

S210 is output data of the first memory 21. 41 is output data S210 of the first memory
And a first selector on the output (backstream, downstream) side that selects a first output signal S201 output from the internal circuit 2 by a selector signal S104. S411 is an output signal from the selector 41. 111 is a first output terminal for outputting this output signal.

Reference numeral 34 denotes a fourth selector on the input side for selecting the first input signal S101 and the second address signal S221 by the select signal S104. S341 is
An address signal output from this selector. 35
Are the second input signal S102 and the second input data signal S
An input-side fifth selector 222 is selected by the select signal S104. In step S351, the selector 3
5 is an input data signal output from the control unit 5. 36 is the third
And a second control signal S223 for controlling read / write of the memory by a select signal S104. S361
Is a read / write signal output from the selector 36.

[0008] S222 is output data of the second memory 22. 42 is the output data S220 of the second memory
And a second selector on the output side that selects a second output signal S202 output from the internal circuit 2 by a selector signal S104. S421 is an output signal from the selector 42. 112 is a second output terminal.

Next, a description will be given of the state of the pause inspection of the memory pause circuit.

First, in order to directly access the two memories 21 and 22, a control signal is input from a selector terminal 104 to input an address of the first memory 21, input data and read / write, and an address of the second memory 22. , Input data and read / write from the first input terminal, the second input terminal, and the third input terminal, respectively, and write to the first memory and the second memory. Next, after completion of writing to all addresses, a fixed pause time is taken. Finally, an input is made from the first input terminal 111, the second input terminal 112, and the third input terminal 113, and the first memory 111 and the second memory 112 are connected to the first output terminal 111 and the second output terminal 112, respectively. Of the data stored in the memory of the above.
Thereafter, the output data is inspected to determine whether or not the written information is correctly held.

[0011]

However, in such a method, a plurality of memories are accessed at the same time or a state that cannot be realized in an actual operation occurs. Therefore, a large current flows through the entire LSI including the memories. There is a danger of raising the ground level or lowering the power supply level. Eventually, the inspection of the memory becomes unstable, and stable inspection may become difficult. For this reason, there has been a demand for the development of a technology capable of performing a memory pause test stably.

[0012]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and each memory block can control whether or not data can be input to the inside by a predetermined signal from the outside. Thus, data for a memory pause test can be input from a common input terminal. At the same time, each memory block has a selector which is controlled by an external signal on the upstream side or the downstream side. Further, in order to further increase the efficiency, an exclusive OR circuit, an OR circuit and the like are provided on the downstream side. Specifically, it is performed as follows.

[0013] In the semiconductor device according to the first aspect, each of the plurality of memory blocks can select an enable state or a disable state. Further, at least some of the plurality of memory blocks may have an enabled state and a disabled state independently of the others.

Therefore, it is possible to input data for a memory pause test to some memory blocks at the same time or to each memory block.
As a result, predetermined test data is sequentially input to each memory block to be subjected to the memory pause test or a predetermined number of memory block groups.

As a result, in a pause test in which a series of operations of data writing, pause, and data reading to the memory block are performed, the current flowing through the memory block is equal to or less than a predetermined current amount.

As a result, in a memory pause test, a current flowing through a semiconductor device or the like at a time can be reduced to a predetermined value or less, and a rise in the ground level or a drop in the power supply level can be prevented, and a stable test can be performed. Become.

In the present invention, each memory block has an input / output unit for exchanging data with the internal circuit.
A memory pause test is performed by externally controlling the selection of the selector signal. By the way, both the input (upstream) side and output (downstream) side selectors perform selection by a selection instruction signal from an external common terminal. Next, the output (or reading) of the data held in each memory block is performed by a predetermined output instruction signal (including a read instruction signal to a reading unit). As a result, at least two of the plurality of memory blocks can be paused in parallel.

As a result, the inspection time can be shortened by overlapping the pause time as compared with the case where a series of operations of data writing, pause, and pause inspection are repeated for each memory block.

According to a third aspect of the present invention, the memory state instruction signal input means includes a data flip-flop for delaying the signal, and enables a plurality of memory blocks by a plurality of control signals each having a phase difference due to the delay. And disable.

As a result, a plurality of memories can be inspected even with a 1-bit test terminal, so that the number of test terminals can be reduced.

According to the fourth aspect of the present invention, at least a part of each memory block sharing the input terminal of the data for the pause test is provided by the control signal input means of the upstream selector or the memory state indication in addition thereto. Shares signal input means.

Thus, the same test data can be simultaneously written into a plurality of memories (and the number of signal input terminals can be reduced).
The digital circuit at the power supply level is prevented.

According to the fifth aspect of the present invention, "substantially the same in hardware" means "substantially the same in hardware" has the same function as the object to be tested as in the case of the same in hardware. Specifically, the address length /
Even if the data bits are different, all the memories can be included. And this is the same in other claims. ), The same test data is input to these memories, output to the exclusive OR circuit at the same timing, and the output can be output to the OR circuit.

This makes the pause test easier.

According to the present invention, in at least one of the plurality of memory blocks which are substantially the same in hardware, the test data held by the memory block alone can be output to the outside.

As a result, even if the memory block which is substantially the same in hardware has the same portion damaged due to the same cause (however, the probability itself is naturally low), the inspection can be performed correctly.

According to the present invention, test data is input to a plurality of memory blocks in order, and the data is output in order of elapse of a predetermined pause time to check whether or not the data is held correctly. .

Thus, the inspection time can be shortened.

According to the present invention, a plurality of test data are sequentially or simultaneously inputted to a plurality of memories which are substantially the same in hardware, and after a predetermined pause time elapses,
The internal data is output from the plurality of memories to the exclusive OR circuit at the same timing, and the output from the circuit is output to the OR circuit.

This facilitates a pause test of a plurality of memory blocks that are substantially the same in hardware.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on its embodiments.

(First Embodiment) In this embodiment, the number of memory blocks is two.

FIG. 2 shows a circuit configuration for a memory pause test of the semiconductor device of the present embodiment. In this figure, the same reference numerals are given to portions (components) having the same functions and functions as those of the circuit of the prior art shown in FIG. 1 except for the functions and functions according to the present invention. Therefore, a repetitive description thereof will be omitted. This is the same in the other embodiments described later.

Hereinafter, portions different from FIG. 1 and related to the present invention will be described in order.

Both the first memory 21 and the second memory 22 have a chip select terminal (CS) for determining enable or disable. Reference numeral 105 denotes a chip select selection terminal for inputting a control signal for switching enable or disable of the first memory and the second memory, and S105 is a control signal. Reference numeral 5 denotes a control circuit, which generates a first control signal S501 and a second control signal S502 by receiving and decoding the chip select selection signal S105. Although there are only two memories in the figure, the provision of the control circuit 5 makes it possible to reduce the number of control signal input terminals to N or less even when there are more memories, for example, N memories.

Next, the contents of the memory pause test in the circuit shown in FIG.

First, in order to directly access the memory, the selector terminal 104 is controlled and the first memory 2 is controlled.
1 address signal S311, the input data signal S321 and the read / write signal S331, the address signal S341 of the second memory 22, the input data signal S351 and the read / write signal S361, the first input terminal 101 and the second input terminal.
A test path accessible from the input terminal 102 and the third input terminal 103 is secured.

Next, the chip select selection terminal 105 is controlled, and the control circuit 5 enables the first memory 21 and disables the second memory 22.
Below this, the first input terminal 101 and the second input terminal 10
Input is performed from the second and third input terminals 103, and data is written to all addresses of the first memory 21.

Next, the chip select selection terminal 105 is controlled, and the second memory 22 is enabled and the first memory 21 is disabled via the control circuit 5. Below this, the first input terminal 101 and the second input terminal 1
02 and the third input terminal 103, and writes data to all addresses of the second memory 22.

Under the above, a fixed pause time is taken. After that, the first input terminal 101, the second input terminal 102,
It is checked whether or not the contents written into the second memory 22 by inputting from the third input terminal 103 are correctly held. For this reason, the contents held from the second output terminal 112 are output and inspected to perform a memory pause inspection of the second memory 22.

Next, the chip select selection terminal 105 is controlled, and the control circuit 5 enables the first memory 21 and disables the second memory 22 to set the first memory 21 in the first state.
Input from the first input terminal 101, the second input terminal 102, and the third input terminal 103 to check whether the content written in the first memory 21 is correctly stored. Outputs the contents, the first
Of the memory 21 of the memory 21 is performed.

As described above, according to the present embodiment, in an LSI in which a plurality of memories are mounted, the chip select is controlled even though there are many memories, so that only one memory is used. An inspection can be performed. For this reason, the current flowing through the LSI is smaller than in the case where a plurality of memories are inspected at the same time. as a result,
There is no danger of an increase in the ground level or a decrease in the power supply level, and a stable inspection can be performed.

Normally, writing to the first memory and the second memory is considerably shorter than the pause time required for each pause test. Therefore, (1) writing to the first memory, (2) writing to the second memory, (3) pause between the first and second memories, and (4) first writing described in the present embodiment. And the step of inspecting the pause of the second memory, for example, (1) writing to the first memory, (2) pause of the first memory, and (3) first pause
Inspection time is shortened as compared with the steps of (4) writing to the second memory, (5) pausing the second memory, and (6) inspecting the pause of the second memory. You can do it.

(Second Embodiment) This embodiment relates to reducing the number of input terminals for controlling chip select when the number of memories (blocks) is large.

As the number of memory blocks increases, the number of input terminals for controlling chip select is also required. Therefore, it is conceivable to reduce the number of chip select select terminals by using a control circuit. Hereinafter, this will be described.

FIG. 3 shows a circuit diagram of a memory pause test according to the present embodiment. In this figure, not only the same reference numerals are given to the same operation and function as those shown in FIGS. 1 and 2, and the figure becomes obvious for the obvious configuration such as the select signal line. The description is omitted to prevent it.

In the present embodiment, since the third memory 23 is added to the circuit, the third address signal S231 and the third input data S23
2, third control signal S233, third output signal S203
Are output, and three selectors 37, 38, and 39 are provided on the input side of the third memory, and one selector 43 is provided on the output side.
Is added. However, these operations and the like are basically the same as those connected to the first memory and the second memory, and the description thereof is omitted. Also, the internal circuit 2 is shown at the top of the figure, but this is only done because of space on the paper.

Hereinafter, the control circuit 5 which is closely related to the gist of the present embodiment will be mainly described.

Reference numeral 105 denotes a chip select selection terminal, and S105 denotes a chip select signal of the chip select selection terminal. 106 is a serial clock input terminal. S106 is a serial clock signal of the serial clock input terminal 106. 5 is a chip select signal S105, a serial clock signal S106
And a control circuit for controlling the first, second and third memories 21, 22, and 23. 51 is a first flip-flop, and S501 is the first flip-flop.
This is a first chip select signal for controlling the first memory 21 output from the flop. 52 is a second flip-flop, and S502 is a second chip select signal for controlling the second memory 22 output from the second flop-flop. 53
Is a third flip-flop, and S503 is a third chip select signal for controlling the third memory 23 output from the third flop-flop.

Next, the operation of the memory pause test of the circuit shown in this figure will be described.

First, in order to directly access each memory, the selector terminal 104 is controlled in the same manner as in the previous embodiment, and the address signal, the input data signal, the read / write signal, the second Address signal, input data signal and read / write signal of the memory 22;
A test path accessible from the first input terminal 101, the second input terminal 102, and the third input terminal 103 to the address signal, the input data signal, and the read / write signal of the memory 23 is secured.

Next, predetermined signals are inputted from the chip select selection terminal 105 and the serial clock input terminal 106, and the first flip-flop 51 and the second flip-flop 51 are inputted.
The flop 52 and the third flip-flop 53 are controlled, and the first memory, the second memory, and the third memory are sequentially enabled one by one, and the other memories are disabled.

On this basis, the first input terminal 101, the second input terminal 102, and the third input terminal 10 are added to all addresses of the memory enabled by this chip select.
Input data from 3 and write data.

After writing data in each memory, a fixed pause time is taken. After that, in order to check whether or not the contents written by inputting from the three input terminals are correctly held, the memories 21, 22, and 23 are connected to the first output terminal 111 and the second output terminal 111, respectively. Output terminal 11
2. The stored contents are sequentially output from the third output terminal 113.

As described above, the pose inspection of each memory is performed.

As can be seen from the above description, according to the present embodiment, even in an LSI in which a large number of memories are mounted,
An independent access to the memory is enabled by the output from the two signal lines of the serial data and the serial clock, and each memory can be inspected. Because of this,
The number of test terminals can be reduced.

As described above, the time required for writing to each memory is usually much shorter than the time required for each pause check. Therefore, as described in the first embodiment, (1) writing to the first, second, and third memories, (2) parallel pause of the first, second, and third memories;
By performing the steps of (3) pause inspection of the first, second, and third memories, for example, (1) writing to the first memory, pause, pause inspection, and (2) writing to the second memory Inspection time can be shortened as compared with the case of performing steps of writing, pause, pause inspection, and (3) writing to the third memory, pause, and pause inspection.

In the above description, the case where the number of memories is three has been described so that the contents can be easily understood.

It goes without saying that writing of data to each memory and the like need not be performed one by one. That is, first write to the first and second memories, then write to the third memory, or if there are many memories,
Of course, it is also possible to write and output two by two or output.

(Third Embodiment) This embodiment relates to reducing the number of terminals for inspection when reading and inspecting data, and shortening the inspection time.

FIG. 4 shows a configuration of a semiconductor device in consideration of the memory pause test of the present embodiment. This semiconductor device is basically the same as that of the previous embodiment shown in FIG. 3 except for the output section. For this reason, also in this drawing, basically the same parts (components) are schematically described, and the obvious configuration is not described in order to prevent the drawing from being complicated.

Hereinafter, a description will be given of portions forming the gist of the present embodiment.

As shown in the figure, two 3-input selectors, one (2-input) selector, two output terminals, and one exclusive There is an OR circuit and an OR circuit. In the figure, reference numeral 44 denotes a fourth (downstream) side fourth selector, and each memory 21, 2
Outputs 2 and 23 are connected, and one of them is input by a select signal S204 from the internal circuit 2. 45
Is a fifth selector, to which outputs from respective memories are connected, and a select signal S2 from an internal circuit.
04 is input. (Note that the two three-input selectors of this semiconductor device are slightly different from the downstream selectors in the preceding embodiment, so that the “fourth” and “fifth” selectors are used. The selector is the “sixth.” The same applies to the output terminal, and the “fourth” and “fifth” output terminals are the same.) 61 is an exclusive OR (EXOR) circuit, The output signal S441 of the fourth selector 44 and the fifth selector 45
The exclusive OR with the output signal S451 is calculated. Regarding the calculation, the output signals S441 and S451 both have a normal bus width, and the calculation is performed for each bit.

Reference numeral 62 denotes a logical sum (OR) circuit, which performs a logical OR operation on each bit of the output S611 of the exclusive OR circuit 61, and outputs the result S621 to the fifth output terminal 115.

Reference numeral 46 denotes the output data S441 of the downstream fourth selector and the signal S206 output from the internal circuit 2, and the selector signal S206 input from the selector selection terminal 104.
A sixth selector on the downstream side selected by 104.

Hereinafter, a memory pause test in this circuit will be described.

First, in order to directly access each memory, a control signal is input from the selector terminal 104 to input an address signal, an input data signal and a read / write signal of the first memory 21 and an address signal of the second memory 22. ,
The input data signal and the read / write signal, the address signal of the third memory 23, the input data signal and the read / write signal are respectively supplied from the first input terminal 101, the second input terminal 102, and the third input terminal 103. An accessible test path is secured, and for the output, the output S441 of the downstream fourth selector 45 is selected by the input of the control signal from the selector terminal 104, and the test path of the fourth output terminal 114 is simultaneously set. Secure.

Next, the chip select selection terminal 105 and the serial clock input terminal 106 are controlled, and the first flip-flop 51 and the second flip-flop 5 are controlled.
2. Data is input to the third flip-flop 53 and set, and the first memory, the second memory, and the third memory are enabled or disabled.

Under this, first, a test path is secured so that the first memory and the second memory can be simultaneously accessed directly, and data is written to all the addresses of the first memory and the second memory. A test path is secured so that the memory can be directly accessed, data is written to all addresses of the third memory, and a fixed pause time is taken.

Next, a test path is secured so that the first memory and the second memory can be directly accessed at the same time.
The data of all the addresses are read from the memory and the second memory. By controlling the selector selection signal S204, the output signal S210 from the first memory 21 is
Is selected by the fourth selector 44 on the downstream side, and is output from the fourth output terminal 114 in order to verify whether or not the written contents are correctly held, and a memory pause check is performed.

At the same time, the output data of the second memory 22 is selected by the fifth selector 45 on the downstream side according to the selector selection signal S204. Now, the access to the first memory 21 and the second memory 22 is performed simultaneously, and the outputs S441 and S442 of both memories are selected by the fourth and fifth selectors 44 and 45, respectively, and the selected output is selected. Are input to the exclusive OR circuit 61 to perform an operation. By the way, since the first memory and the second memory are written at the same time, exactly the same data is output when no failure occurs.

As a result, the output data S611 of the exclusive OR circuit outputs L (low) for all M bits. Further, all (M) bits of the output S611 of the exclusive OR circuit 61 are operated by the OR circuit 62, and the result S621 is output from the fifth output terminal 115.

By the way, if the first memory block 21
In the case where there is a failure, since the output data S210 is directly output from the fourth output terminal 114 to the outside, the failure location can be detected by a measuring device such as an LSI tester. The output of the operation result of the exclusive OR circuit 61 and the OR circuit 62 is output to the fifth output terminal 115.
Is output as H (high), whereby it can be determined that one of the memory blocks has failed.

At this time, if the second memory block also has a failure and coincides with the failure of the first memory block, a failure is observed in the first output result and the second output data is Since it becomes L, a failure of the second memory block can be detected at the same time. (However, it is unlikely that a failure occurs in the same way in practice.) In addition, when a failure occurs in the second memory block,
The operation result of the exclusive OR circuit and the OR circuit is output to the second output data, and H is output from the fifth output terminal only for the fault address, so that the fault address can be detected.

Next, the test path for the third memory is secured, and the test paths for the first and second memories are cut off. The output signal S230 from the third memory is output by the fourth selector 45 on the downstream side according to the selector selection signal S204 from the internal circuit 2. As a result, the data of the third memory block is output to the fourth output terminal 114, and a pause check can be performed.

As can be seen from the above description, according to the present embodiment, in an LSI in which a plurality of memories are mounted, a single selector and an exclusive OR circuit on the downstream side of the memory block perform a single operation. Inspection of the memory by access or simultaneous access can be performed. Therefore, the number of test terminals can be reduced, and reading and writing of each memory can be performed at the same time, and the inspection time can be shortened.

In the present embodiment, one test block is composed of two selectors and one exclusive OR circuit. However, three or more selectors are excluded within an allowable current range according to the number of memory blocks. Needless to say, two or more logical OR circuits may be used.

(Fourth Embodiment) This embodiment relates to a case where the number of memory blocks that can be subjected to a memory pause test is limited.

In the third embodiment, the case where an arbitrary memory block is selected by the selector is described. However, the case where the memory blocks that can be subjected to the memory pause test are already limited according to the current characteristics of the memory block. There is. The memory pause test circuit at this time will be described.

FIG. 5 shows a circuit configuration for a memory pause test of the semiconductor device of the present embodiment. Also in the circuit shown in this figure, up to each memory block, it is the same as the semiconductor device shown in FIGS. 4 and 3, and therefore, this portion is simply shown. The major difference from the third embodiment is that one of the two inputs is selected on the downstream side of the first and third memory blocks 21 and 23 by a select signal from the selector selection terminal 104. Selector 41,
43, the exclusive OR circuit 61 and the OR circuit 62 are provided on the downstream side of the second memory block 22.

The exclusive OR circuit 61 calculates the exclusive OR of the output signal S210 from the first memory block 21 and the output signal S220 from the second memory block 22. Then, the operation result S611 is output to the OR circuit 6.
Output to 2. The two memory blocks 21 and 22
Output signals S210 and S220 have a normal bus width, and therefore, the exclusive OR circuit performs an operation for each bit. The OR circuit 62 calculates the OR of each bit of the output S611 from the exclusive OR circuit.
621 is output.

The first selector 41 on the downstream side converts the output data S 210 from the first memory block 21 and the signal S 207 output from the internal circuit 2 into the selector selection terminal 10.
4 is selected by the selector signal S104 input from the control signal No. 4.

Hereinafter, the contents of the memory pause test of the semiconductor device having the above configuration will be described.

First, in order to directly access each memory, control is performed from the selector terminal 104, and the address signal of the first memory 21, the input data signal and the read / write signal, the address signal of the second memory 22, A first input terminal 101 and a second input terminal 10 are provided to the data signal and the read / write signal, the address signal of the third memory 23, the input data signal and the read / write signal, respectively.
Second, a test path accessible from the third input terminal 103 is secured, and the output of the selector terminal 104 is
The first selector 4 on the downstream side by input of a control signal from the
1 selects the output 340 from the first memory 21 and also secures a test path for the first output terminal 111.

Next, control is performed from the chip select selection terminal 105 and the serial clock input terminal 106, and data is set in the first flip-flop 51, the second flip-flop 52, and the third flip-flop 53. Then, the first memory 21, the second memory 22, and the third memory 23 are enabled or disabled according to the input of the test data.

First, the first memory 21 and the second memory 2
2, a test path is secured so as to allow direct simultaneous access to both memories, and data is written to all addresses of both memories. Thereafter, a test path is secured so as to directly access the third memory 23, and data is secured to all addresses of the third memory. And take a certain pause time.

Next, a test path is secured so that the first memory and the second memory can be directly accessed at the same time.
The data of all addresses is read from the memory of the second memory and the second memory. At this time, in order to detect whether or not the contents written in the first memory block can be properly held, the data is output from the output terminal 112 to perform a memory pause test.

Access to the first memory and the second memory is performed simultaneously, and the output results S210 and S2
20 is input to the exclusive OR circuit 61, and the operation is performed. By the way, since the first memory and the second memory write data at the same time, exactly the same data is output unless both memories are out of order. Therefore, the output data S611 of the exclusive OR circuit 61 is L for all M bits.
Is output. Next, the output S611 from the exclusive OR circuit 61 is input to the OR circuit 62, and the logical sum of all M bits is calculated, and the output result S621 is output from the second output terminal 112.

When a failure occurs in the first memory block 21, the output data S210 is output to the outside from the first output terminal 111 as it is. Can be observed. The operation result S621 of the exclusive OR circuit 61 and the OR circuit 62 is output as H to the second output terminal 112, and it can be determined that a fault still exists.

At this time, if the second memory block also has a failure and coincides with the failure of the first memory block, a failure is observed in the output result of the first memory block, and Output data becomes L, whereby the second
Of the memory block can be detected.

When a failure occurs in the second memory block, the operation result S621 of the exclusive OR circuit 61 and the exclusive OR circuit 62 is output to the second output data.
Since only the fault address is output from the second output terminal, the fault address can be observed.

Next, a test path for the third memory block is secured, and the test paths for the first and second memories are cut off. As a result, the paused data of the third memory block is output to the third output terminal 113, and the inspection can be performed.

That is, in this embodiment, it is possible to reduce the number of selectors corresponding to the current characteristics of the memory block, as compared with the third embodiment.

Although the present invention has been described based on several embodiments, it goes without saying that the present invention is not limited to this. That is, for example, the following may be performed. 1) As shown in FIG. 6, an input terminal 10 for test data
Numerals 1 to 103 also serve as input terminals for original data for exhibiting the original function of the semiconductor device. For this reason,
A selector 4 is provided between the circuit and the internal circuit so that an input to the memory block can be made. This figure shows a schematic circuit configuration. 2) Since there are many memory blocks, there are also many test data input terminals. 3) Depending on the production quantity, the type of the semiconductor device, and the like, as shown in FIG. 7, a separate exclusive OR circuit and a logical OR circuit can be connected for a pause test of the semiconductor device. 4) Regarding the type of data to be written to the memory, in the present embodiment, an SRAM is assumed, and three types are used because three types are available for R / W access. For this reason, for example, DRA
As can be seen from the assumption of M RAS, CAS, etc., the number of control terminals and data is three or more. 5) Since writing to the memory to be tested can be freely performed, an exclusive OR circuit or the like is tested first.

[0095]

As can be seen from the above description, according to the present invention, the current flowing at one time can be reduced to a predetermined value or less in the pause test of the memory block. For this reason, there is no danger of a rise in the ground level or a drop in the power supply level, and a stable inspection can be performed.

Further, by using the exclusive OR circuit and the OR circuit, it becomes easy to detect a memory block having a failure.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration focusing on a memory pause test of a conventional semiconductor device.

FIG. 2 is a diagram illustrating a circuit configuration of the semiconductor device according to the first embodiment of the present invention, focusing on a memory pause test;

FIG. 3 is a diagram illustrating a circuit configuration of a semiconductor device according to a second embodiment of the present invention, focusing on a memory pause test;

FIG. 4 is a diagram illustrating a circuit configuration of a semiconductor device according to a third embodiment of the present invention, focusing on a memory pause test;

FIG. 5 is a diagram showing a circuit configuration of a semiconductor device according to a fourth embodiment of the present invention, focusing on a memory pause test;

FIG. 6 is a diagram showing a circuit configuration of a semiconductor device according to another embodiment of the present invention, focusing on a memory pause test and selection of original data.

FIG. 7 is a diagram showing a circuit configuration of a semiconductor device according to still another embodiment of the present invention, focusing on a memory pause test;

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 memory pause test circuit main body 101 first input terminal 102 second input terminal 103 third input terminal 104 selector selection terminal 105 chip select selection terminal 106 serial clock input terminal 111-115 first to fifth output terminals 2 Internal circuit 21 First memory block 22 Second memory block 23 Third memory block 31 to 39 First to ninth selectors on input side 4, 40 to 46 First to sixth selectors on output side 5 Control Circuits 51 to 53 First to third flip-flops 61 Exclusive OR circuit 62 OR circuit

Claims (8)

[Claims] 1. An internal circuit, a plurality of memory blocks for inputting / outputting data to / from the internal circuit, and capable of independently taking a writable state and a non-writable state by a state instruction signal from the outside, An input terminal common to a plurality of memory blocks and inputting data for a memory pause test; an output signal from the internal circuit and data from the common input terminal; and an upstream side of each of the memory blocks An upstream selector for each memory block provided in the memory, a signal obtained by branching the output from the memory block to the internal circuit and an output signal from the internal circuit are input, and the downstream of each memory block A downstream selector provided on the side, a selector control signal input means for controlling selection of signals of the upstream selector and the downstream selector, A memory state instruction signal input unit for inputting a state instruction signal indicating whether the plurality of memory blocks are in a writable state or in an unwritable state. 2. The selector control signal input means, when the selector on the upstream side of each memory block selects the test data for memory pause from the input terminal, simultaneously with the selector on the downstream side, Up / downstream common selector control signal input means for inputting a selector control signal for selecting a signal obtained by branching an output from a memory block to an internal circuit, wherein each memory block is written with a predetermined output instruction signal. 2. The memory pause according to claim 1, wherein the memory block is an output timing controllable memory block that outputs data, and further includes an output instruction signal input unit that inputs an output signal to the output timing controllable memory block. Semiconductor device considering test. 3. The memory status indication signal input means, which corresponds to each of the memory blocks and delays the status indication signal to the corresponding memory block in a predetermined procedure in conjunction with a separately input clock signal. 3. The semiconductor device according to claim 1, further comprising a data flip-flop to be inputted. 4. At least a part of the plurality of memory blocks shares the selector control signal input means to a corresponding selector or the memory state instruction signal input means in addition to the selector control signal input means. The semiconductor device according to claim 1, wherein the memory pause test is taken into consideration. 5. At least a part of the memory block whose output timing is controllable is a memory block that is substantially the same in hardware, and the input terminal is a pause test that is the same in a plurality of memory blocks that are substantially the same in hardware. The same data input type input terminal for inputting application data, the output instruction signal input means being held at the same timing in a plurality of memory blocks to which the hardware is substantially the same and the same data is input. Common output instructing signal input means for instructing data output, further comprising: an exclusive OR circuit; and an output signal having the same content from the substantially same hardware block as the hardware, together with the corresponding downstream type selector. Provided to operate or provided in place of the corresponding downstream selector, and input to the exclusive OR circuit at the same timing. An exclusive-OR circuit input control means for causing an output signal from the exclusive-OR circuit to be input; and an OR output terminal for outputting an output signal from the OR circuit to the outside. 5. The semiconductor device according to claim 2, wherein a memory pause test is taken into account. 6. At least one subsequent stage of the plurality of memory blocks that are substantially the same in hardware, the same data held in the plurality of memory blocks that are substantially the same in hardware is stored in the memory block. It is characterized by having various output control means for the same memory block which can output to the outside independently and output to the exclusive OR circuit at the same timing as the other memory blocks. 6. A semiconductor device in which a memory pause test is taken into consideration. 7. A memory pause test method for a semiconductor device having an internal circuit and a plurality of memory blocks, wherein a signal line is connected to the plurality of memory blocks so that data for a pause test can be inputted from outside. A pre-processing step; a test data input step of sequentially inputting data for a pause test from the outside to the plurality of memory blocks after the pre-processing step is completed; and a pause for holding a predetermined time after the test data input step is completed. In order to enable the data in the plurality of memory blocks to be output to the outside after the time holding step and the pause time holding step, a signal line is provided to enable the data held in the plurality of memory blocks to be output to the outside. A pause test data output preparation step to be connected; and the pause test data output preparation step. A test data output step of sequentially outputting test data held in the plurality of memory blocks to the outside after completion of the pause time holding step. Pose test method. 8. A memory pause test method performed by using an exclusive OR circuit and an OR circuit of a semiconductor device having an internal circuit and a plurality of hardware blocks that are substantially the same in hardware. A pre-processing step of connecting a signal line so that data for a pause test can be externally input to a substantially same memory block in hardware; and after the pre-processing step, the plurality of memory blocks are sequentially or simultaneously the same from outside. A test data inputting step of inputting data for a pause test, a pause time holding step of holding a predetermined time after the test data inputting step is completed, and a plurality of hardware steps after the completion of the pause time holding step. In order to be able to independently output the data inside one of the substantially identical memory blocks to the outside, A data output preparation step for one memory pause test for connecting a signal line so that the data held in at least one corresponding memory block can be output to the outside independently as it is; And outputting the test data held in at least one memory block capable of outputting the internal data to the outside after completion of the step and the pause time holding step. An exclusive-OR circuit, before or after the one memory target test data output step, together with another substantially identical memory holding data of the same content before or after the step. Connecting the plurality of memory outputs to the memory, and after the completion of the plurality of memory output connecting steps, and A plurality of memory output steps for outputting the data stored in the plurality of memories to the exclusive OR circuit at the same timing after a lapse of time; and an exclusive OR for outputting the operation result of the exclusive OR circuit to the exclusive OR A memory pause test method for a semiconductor device, comprising: an output step; and an OR output step of outputting an operation result of the OR circuit to the outside.