JP2001309205A - Processing circuit for video image signals - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a simply-configured processing circuit for video image signals, using a frame cyclic filter circuit, in which the fluctuation of an electric field can be detected with high accuracy and the displayed images are more clear to see. SOLUTION: Depending on the volume of video signal noise, this circuit controls the frame cyclic filter coefficient 1-K and K to reduce the noise of the displaying image. It detects the disturbance of synchronous signals HD and DV that are separated from a video signal as the noise volume, to control the filter coefficient based on the noise volume. This control system, because it is based on the disturbance of the synchronous signals detected, causes no delay in detection and also enables coping with the degradation of images in a medium or strong electric field. As a synchronous signal, either of horizontal or vertical one, or both can be used. When there is a sharp change in the disturbance in the synchronous signal, the noise can be removed by increasing the filter coefficient.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit used for a television receiver.

[0002]

2. Description of the Related Art In an on-vehicle television receiver, a sudden change in a received electric field may occur depending on a moving environment, and a displayed image may be significantly deteriorated. On the other hand, a video signal processing circuit using a frame recursive filter circuit has been conventionally proposed in order to obtain a more easily viewable display video.

FIG. 1 shows a video signal processing circuit using a conventional frame recursive filter circuit. The illustrated video signal processing circuit subtracts the video signal stored in the frame memory 2 and delayed by one frame from the video signal output by the television tuner 1, and uses the obtained inter-frame difference signal as an output video signal.

[0004] Filter coefficients K-1 and K for generating an inter-frame difference signal are adaptively controlled according to an IF-AGC voltage that changes with the received electric field strength in the television tuner 1. The IF-AGC signal is A / D converted, and the filter coefficients K-1, K written in the coefficient RAM 3 are read out by the digital data. The filter coefficient is previously written in the coefficient RAM 3 by the CPU 4.

[0005] When the received electric field strength is reduced and the degradation of the video signal is increased, the coefficient K is controlled to be large, and the influence of the video signal one frame before is increased. Thereby, the influence of noise from the output video signal can be reduced, and the S / N ratio can be improved. Further, when the received electric field strength is increased and the deterioration of the video signal is small, the coefficient K is controlled to be small, and the output video signal is strongly influenced by the latest video signal.

[0006]

In the above prior art,
IF-AGC to detect the degree of video signal degradation
Voltage is used. However, the AGC of the IF stage circuit
There is a problem that a detection delay occurs due to response characteristics.
Further, since the IF-AGC voltage responds only when the electric field is weak, the frame recursive filter coefficient is not controlled for, for example, image degradation due to multipath in a medium or weak electric field state, and a noise removing effect cannot be obtained. There was a case. Further, an A / D for digitizing the IF-AGC voltage
There is a problem that the converter 5 is required.

According to the present invention, in a video signal processing circuit using a frame recursive filter circuit, a change in an electric field which degrades a video signal is accurately detected with a simple configuration.
The purpose is to obtain a display image that is easier to see.

[0008]

SUMMARY OF THE INVENTION The present invention has been made to achieve the above object. The present invention provides a video signal processing circuit that uses a frame recursive filter circuit and controls a frame recursive filter coefficient according to the amount of noise in an input video signal. An image deterioration detection circuit for detecting the amount and controlling the frame recursive filter coefficient based on the amount of the disturbance; As the synchronization signal, one of a horizontal synchronization signal and a vertical synchronization signal can be used, or both signals can be used together.

In the present invention, the deterioration of the video signal is detected from the disturbance of the synchronization signal, and the frame recursive filter coefficient is controlled. This synchronization signal disturbance can be easily detected by detecting the difference between the synchronization signal and the system clock.
No detection delay occurs. According to the present invention, since the detection delay of the electric field fluctuation can be almost eliminated, the correction accuracy at the time of image deterioration is improved. In addition, since the disturbance of the synchronization signal is detected, a noise removing effect can be obtained even for image deterioration due to multipath in a medium or strong electric field state. Furthermore, I
Since the F-AGC voltage is not used, an A / D converter is not required.

Further, according to the present invention, when it is detected that the disturbance of the synchronization signal fluctuates suddenly, it is determined that rapid image degradation has occurred, and the SN improvement rate is increased (for example, K =
0.9), it is possible to prevent rapid deterioration of the displayed image.

[0011]

Embodiments of the present invention will be described with reference to the drawings. FIG. 2 shows a video processing circuit using a frame recursive filter circuit to which the present invention is applied. The video signal stored in the frame memory 2 is subtracted from the video signal (composite video signal) detected and amplified by the television tuner 1. The frame memory 2 stores a video signal delayed by one frame. The video signal from the television tuner 1 is multiplied by a filter coefficient 1-K by a coefficient circuit 6, and the video signal from the frame memory 2 is digitized by an A / D converter 5,
The coefficient circuit 10 multiplies the filter coefficient K. The two signals are added by the adder 7 and output as the video signal of the video signal processing circuit, and are stored in the frame memory 2 as the video signal of one frame before.

The current NTSC television signal has very high correlation between frames, while noise has no correlation.
Therefore, by synthesizing the latest video and the video one frame before, the influence of noise appearing randomly between frames can be reduced and the S / N ratio can be greatly improved. The theoretical SN improvement rate of the circuit shown is 10 log ｛(1 + K)
/ (1-K)｝ dB. As is clear from this equation, the SN improvement rate can be increased by increasing the coefficient K when the degree of deterioration of the video signal is large, and by decreasing the coefficient K when the degree of deterioration is small. In this method, when the coefficient K is increased, an afterimage is generated. On the contrary, the afterimage is hardly perceived in a display image having a low S / N ratio (noisy) due to human visual characteristics. .

Filter coefficient 1 for determining SN improvement rate 1
K and K are controlled by the video deterioration detection circuit 8 according to the disturbance (wobble) of the synchronization signal. A video signal output from the television tuner 1 is processed by the sync separation circuit 9 and the AFC circuit 11 to be extracted from the video signal output from the television tuner 1. As the synchronization signal, one of the horizontal synchronization signal HD and the vertical synchronization signal VD is used, or both signals are used together.

An image deterioration detection circuit 8 is supplied with a quadrupled clock (frequency 4 fsc) processed and extracted from a video signal by a band pass filter (BPF) 12 and an automatic phase control circuit (APC) 13. BPF12 is
A color burst component is extracted by passing only a 3.58 MHz component (color signal) from the video signal. AFC circuit 11
Signal insertion position timing (BG
The APC 13 is operated at P (burst gate pulse). As a result, a quadrupled clock phase-locked to the color burst signal is generated. The quadrupled clock operates as a basic clock (4fsc).

In the NTSC broadcasting standard, the frequency relationship between the frequency fsc of the color burst signal, the frequency fh of the horizontal synchronizing signal HD, and the frequency fv of the vertical synchronizing signal VD is strictly defined as follows. fsc = 455/2 × fh → 4 fsc = 910 × f
h fh = 525/2 × fv → 4 fsc = 910 × 2
The 62.5 × fv video deterioration detection circuit 8 converts the AFC-processed horizontal synchronization signal HD (fh) and / or vertical synchronization signal VD (fv) into
It detects how much there is a variation from the standard clock (4fsc) which is a standard value, or detects the reception electric field from the fluctuation of the frequency of the horizontal synchronizing signal HD / vertical synchronizing signal VD itself, and obtains a filter coefficient 1-K , K.

[Embodiment 1] An embodiment of the image deterioration detecting circuit 8 will be described below. In the following description, an example in which the horizontal synchronization signal HD is used as a synchronization signal will be described.
It is also possible to use the vertical synchronization signal VD. FIG.
Shows a first example of the video deterioration detection circuit 8, and FIG. 4 shows the timing of each signal.

The horizontal synchronizing signal HD is input to an N-ary counter 14. Note that N is an integer of 2 or more. The basic clock (4fsc) is input to the counter 15. When the N-ary counter 14 counts N horizontal synchronization signals HD,
The counter 15 is reset. The difference between the count value calculated by the counter 15 for N cycles of the basic clock (4 fsc) and the specified value (910 × N) recorded in the memory 16 is obtained by the subtractor 17. The value of this difference represents the disturbance (fluctuation) of the horizontal synchronization signal HD, the degree of deterioration of the received electric field strength, and the amount of noise.

The value of the difference is converted to an absolute value by an absolute value circuit (ABS) 18 and recorded in M latches 19 prepared. Note that M is an integer of 2 or more. M latches 1
In 9, every time the counter 15 is reset, the absolute value of the difference is sequentially recorded. Maximum value detection circuit 21
Is obtained by M operations, and the maximum value is extracted from the difference values recorded in each latch 19. The maximum value of this difference is detected as the amount of noise, and the coefficient RAM
From 3, the process of reading out the filter coefficients 1-K and K is performed.

Instead of the horizontal synchronizing signal HD, the vertical synchronizing signal V
When D is used, 910 × 262.5 × N is used instead of 910 × N as the specified value. [Embodiment 2] FIG. 5 shows a second example of the image deterioration detection circuit 8. In this example, the circuit configuration from the N-ary counter 14 to the maximum value detection circuit 21 is the same as that of FIG. 3 of the first embodiment. In this example, a minimum value detection circuit 22 is further provided, and the minimum value is extracted from the difference values recorded in the M latches 19. Maximum value detection circuit 21 and minimum value detection circuit 22
Are added by the adder 7 and are multiplied by 1/2 in the coefficient circuit 27. Thereby, an intermediate value of the difference values obtained by the M operations is obtained. In this example, an intermediate value of the difference values is detected as the noise amount.

In this embodiment, similarly to the first embodiment, it is possible to detect the deterioration of the received electric field strength from the disturbance of the vertical synchronization signal VD instead of the horizontal synchronization signal HD. [Embodiment 3] FIG. 6 shows a third example of the image deterioration detection circuit 8. In this example, the latch 1
The circuit configuration up to 9 is the same as that of FIG. 3 of the first embodiment. In this example, an average value circuit 23 is provided, and an average value of the difference values recorded in the M latches 19 is extracted. Thereby, an average value of the difference values obtained by the M operations is obtained. In this example, the average value of the difference values is detected as the noise amount.

Also in this embodiment, it is possible to detect the deterioration of the received electric field strength from the disturbance of the vertical synchronization signal VD instead of the horizontal synchronization signal HD. [Embodiment 4] FIG. 7 shows a fourth example of the image deterioration detecting circuit 8, and FIG. 8 shows the timing of each signal.

In this embodiment, the circuit configuration from the N-ary counter 14 to the maximum value detection circuit 21 is the same as that of the first embodiment shown in FIG. In this example, the output of the maximum value detection circuit 21 is input to the latch 24 and the subtractor 7. The subtractor 7 calculates the difference between the maximum value of the current difference output from the maximum value detection circuit 21 and the maximum value of the previous difference recorded in the latch 24. The value of the difference is a fluctuation value of the disturbance value of the horizontal synchronization signal HD between the previous operation and the current operation. A large variation value means that the received electric field has changed abruptly.
The output of the subtractor 7 is converted into an absolute value by an absolute value circuit 25 and input to a comparator 26. In the comparator 26, the data is compared with a predetermined threshold value stored in the memory 28. When the fluctuation value becomes equal to or larger than the threshold value, a sudden change in the received electric field is detected, and a large filter coefficient is selected from the coefficient RAM 3.

When the received electric field strength changes suddenly,
That is, when there is a transition from a weak electric field to a strong electric field or vice versa, the displayed image is largely deteriorated. For example, when there is no input video signal, in the case of an extremely weak electric field, or when only the synchronization component is lost due to the effect of multipath or the like, the displayed video is disturbed in synchronization and video at the same time, making it very difficult to see. Become. Under such a reception condition, the AFC-processed horizontal synchronization signal HD is in a free-run state, and is in a self-transmission state at a certain frequency. Such a state is detected when the variation value of the difference value is equal to or greater than a predetermined threshold value. In this example, when this is detected, for example, the filter coefficient K = 0.
By setting it to 9, the S / N ratio improvement rate is increased.

Also in this embodiment, it is possible to detect the deterioration of the received electric field strength from the disturbance of the vertical synchronization signal VD instead of the horizontal synchronization signal HD. [Embodiment 5] FIG. 9 shows a fifth example of the image deterioration detecting circuit 8. In this example, the circuit configuration from the N-ary counter 14 to obtaining the intermediate value of the difference value by the coefficient circuit 27 is the same as that of FIG. The circuit configuration after the latch 24 and the subtractor 7 is the same as that of FIG. 7 of the fourth embodiment. In this example, when the variation value of the intermediate value of the difference value is equal to or greater than the threshold value, it is determined that a sudden change in the reception electric field has been detected.

Also in this embodiment, it is possible to detect the deterioration of the received electric field strength from the disturbance of the vertical synchronizing signal VD instead of the horizontal synchronizing signal HD. Embodiment 6 FIG. 10 shows a sixth example of the image deterioration detection circuit 8. In the present embodiment, the circuit configuration from the N-ary counter 14 to obtaining the average value of the difference value by the average value circuit 21 is the same as that of FIG. Latch 24,
The circuit after the subtractor 7 is the same as that in FIG. 7 of the fourth embodiment. In this example, when the variation value of the average value of the difference values is equal to or greater than the threshold value, it is determined that a sudden change in the reception electric field has been detected.

Also in this example, it is possible to detect the deterioration of the received electric field strength from the disturbance of the vertical synchronization signal VD instead of the horizontal synchronization signal HD. [Embodiment 7] FIG. 11 shows a seventh example of the image deterioration detecting circuit 8. In the present example, the circuit configuration from the N-ary counter 14 to the absolute value circuit 18 converting the difference value to an absolute value is the same as that of FIG. 3 of the first embodiment. The absolute value of the difference value is a fluctuation value of the value of the horizontal synchronization signal HD between the previous operation and the current operation. This variation value is recorded in the latch 19 and is compared with the threshold value by the comparator 26 every time the counter 15 is reset. When the fluctuation value becomes equal to or larger than the threshold value, a large filter coefficient is selected from the coefficient RAM 3 as in the above-described fourth to sixth embodiments.

Also in this embodiment, it is possible to detect the deterioration of the received electric field strength from the disturbance of the vertical synchronization signal VD instead of the horizontal synchronization signal HD. [Eighth Embodiment] FIG. 12 shows an eighth embodiment of the image deterioration detecting circuit 8. Depending on the reception conditions, only the horizontal synchronizing signal HD deteriorates, only the vertical synchronizing signal VD conversely deteriorates, or both synchronizing signals deteriorate. Actually, the displayed image is disturbed when both the horizontal and vertical synchronization signals are deteriorated. In order to detect the occurrence of the large synchronization disturbance and the image deterioration, the detection of the disturbance of the horizontal synchronization signal HD and the detection of the disturbance of the vertical synchronization signal VD are used together.
A more accurate video deterioration detection circuit can be configured.

In this embodiment, a first circuit 31 for detecting the amount of noise from the disturbance of the horizontal synchronizing signal HD and a second circuit 32 for detecting the amount of noise from the disturbance of the vertical synchronizing signal VD are provided. As the first circuit 31, FIG.
The image deterioration detection circuit shown in FIG. Second circuit 3
As 2, the video deterioration detection circuit using the vertical synchronization signal VD instead of the horizontal synchronization signal HD described in the first embodiment is used.

The outputs of the two circuits 31, 32 are added by an adder 7, and the added value is output as a combined noise amount. Reading processing of the filter coefficients 1-K and K from the coefficient RAM 3 is performed according to the synthesized noise amount. As a modification of the present embodiment, the video degradation detection circuit shown in FIG. 5 of the second embodiment is a first circuit 31, and the video degradation detection circuit using the vertical synchronization signal VD described in the second embodiment is a second circuit 31. Circuit 3
It can be 2. Similarly, the video degradation detection circuit shown in FIG. 6 of the third embodiment is a first circuit 31, and the video degradation detection circuit using the vertical synchronization signal VD described in the third embodiment is a second circuit 32. You can also.

[Embodiment 9] FIG. 13 shows a ninth example of the image deterioration detection circuit 8. In this example, the horizontal synchronization signal H
A first circuit 33 that increases the SN improvement rate when a sudden change in the reception electric field is detected by D, and a second circuit 34 that increases the SN improvement rate when a sudden change in the reception electric field is detected by the vertical synchronization signal VD. Provided. As the first circuit 33, the image deterioration detection circuit shown in FIG. 7 of the fourth embodiment is used. As the second circuit 34, the video deterioration detection circuit using the vertical synchronization signal VD described in the fourth embodiment is used.

The outputs of the first and second circuits 33 and 34 are
The signals are output to the OR circuit 35 and the AND circuit 36. Circuit 3
When both 3 and 34 output, the SN improvement rate is controlled to the maximum by the output of the AND circuit 36. Circuits 33, 3
When only one of the four outputs is provided, the output of the OR circuit 35 controls the SN improvement rate to be larger than the maximum value.

As a modification of the fifth embodiment, the video deterioration detecting circuit shown in FIG.
The video degradation detection circuit using the vertical synchronizing signal VD described in the first embodiment is the second circuit 34, and the video degradation detection circuit shown in FIG.
The video degradation detection circuit using the vertical synchronizing signal VD described in the above section is the second circuit 34, and the video degradation detection circuit shown in FIG.
The video deterioration detection circuit using the vertical synchronizing signal VD described above can be used as the second circuit 34.

[0033]

According to the present invention, in a video signal processing circuit using a frame recursive filter circuit, a change in an electric field that degrades a video signal is accurately detected with a simple configuration, and a more easily viewable display video is displayed. Obtainable.

[Brief description of the drawings]

FIG. 1 is a diagram showing a conventional frame recursive filter configuration.

FIG. 2 is a diagram showing a configuration of a frame recursive filter to which the present invention is applied.

FIG. 3 is a diagram showing a first embodiment of the image deterioration detection circuit in FIG. 2;

FIG. 4 is a diagram showing operation timings of the circuit of FIG. 3;

FIG. 5 is a diagram showing a second embodiment of the image deterioration detection circuit in FIG. 2;

FIG. 6 is a diagram showing a third embodiment of the image deterioration detection circuit in FIG. 2;

FIG. 7 is a diagram showing a fourth embodiment of the video deterioration detection circuit in FIG. 2;

FIG. 8 is a diagram showing operation timings of the circuit of FIG. 7;

FIG. 9 is a diagram showing a fifth embodiment of the video deterioration detection circuit in FIG. 2;

FIG. 10 is a diagram showing a sixth embodiment of the image deterioration detection circuit in FIG. 2;

FIG. 11 is a diagram showing a seventh embodiment of the video deterioration detection circuit in FIG. 2;

FIG. 12 is a diagram showing an eighth embodiment of the image deterioration detection circuit in FIG. 2;

FIG. 13 is a diagram showing a ninth embodiment of the video deterioration detection circuit in FIG. 2;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... TV tuner 2 ... Frame memory 3 ... Coefficient RAM 4 ... CPU 5 ... A / D converter 6 ... Coefficient circuit 7 ... Adder 8 ... Video deterioration detection circuit 9 ... Synchronization separation circuit 10 ... Coefficient circuit 11 ... AFC 12 ... BPF 13 ... APC 14 ... N-ary counter 15 ... Counter 16 ... Memory 17 ... Subtractor 18 ... ABS 19 ... Latch 21 ... Maximum value detection circuit 22 ... Minimum value detection circuit 23 ... Average value circuit 24 ... Latch 25 ... Absolute value circuit 26 comparator 27 coefficient circuit 28 memory 31 first circuit 32 second circuit 33 first circuit 34 second circuit 35 OR circuit 36 AND circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C020 AA01 AA09 BA05 BA07 BA09 BB15 CA07 5C021 PA17 PA22 PA38 PA56 PA66 PA82 PA85 PA87 PA89 RA16 RB07 SA01 SA05 XA13 YA02 5C066 AA03 CA07 DA04 DA08 DC07 DC08 DD07 EB11 EC12 EG01 EG01 GA16 HA01 KA01 KB01 KC07 KD03 KD07 KE02 KE07 KE19

Claims (9)

[Claims] 1. Using a frame recursive filter circuit,
In a video signal processing circuit that controls a frame recursive filter coefficient according to an amount of noise in an input video signal, detecting a disturbance amount of a synchronization signal extracted from the input video signal, and based on the disturbance amount, A video signal processing circuit comprising a video degradation detection circuit for controlling a frame recursive filter coefficient. 2. The image deterioration detecting means calculates an interval of the synchronization signal, performs an operation for obtaining a difference between the value of the synchronization signal and an original standard value a predetermined number of times, and calculates a maximum value of the difference during the operation of the predetermined number of times. The video signal processing circuit according to claim 1, wherein a value is detected as an amount of disturbance of the synchronization signal. 3. The image deterioration detecting means calculates a cycle of the synchronization signal, performs a predetermined number of operations for obtaining a difference between the value of the synchronization signal and an original standard value, and calculates a maximum value of the difference during the predetermined number of operations. The video signal processing circuit according to claim 1, wherein an intermediate value between the value and the minimum value is detected as an amount of disturbance of the signal. 4. The image deterioration detecting means calculates a cycle of the synchronization signal, performs a predetermined number of operations for obtaining a difference between the value and an original standard value, and averages the difference during the predetermined number of operations. The video signal processing circuit according to claim 1, wherein a value is detected as the amount of the disturbance. 5. The image deterioration detecting means detects a change amount of the disturbance amount, and when the change amount is equal to or more than a predetermined threshold value, sets the value of the frame recursive filter coefficient to a large value. The video signal processing device according to claim 2, wherein the control is performed. 6. Using a frame recursive filter circuit,
A video signal processing circuit that controls a frame recursive filter coefficient according to an amount of noise in an input video signal, wherein a period of a synchronization signal extracted from the input video signal is detected, and a difference between the value and an original standard value is detected. A video signal processing circuit comprising: video degradation detection means for controlling the frame recursive filter coefficient to a large value when is greater than or equal to a predetermined threshold value. 7. The video signal processing device according to claim 2, wherein said video degradation detection means uses a horizontal synchronization signal as said synchronization signal. 8. The video signal processing device according to claim 2, wherein said video degradation detection means uses a vertical synchronization signal as said synchronization signal. 9. The video degradation detecting means uses a horizontal synchronization signal and a vertical synchronization signal together as the synchronization signal.
7. The video signal processing device according to any one of claims 6 to 6.