JP2001308122A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor deviceInfo
- Publication number
- JP2001308122A JP2001308122A JP2000116648A JP2000116648A JP2001308122A JP 2001308122 A JP2001308122 A JP 2001308122A JP 2000116648 A JP2000116648 A JP 2000116648A JP 2000116648 A JP2000116648 A JP 2000116648A JP 2001308122 A JP2001308122 A JP 2001308122A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- jig
- semiconductor element
- semiconductor device
- external connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は半導体装置の製造方
法に関し、より詳細には半導体素子を厚さ方向に貫通し
て半導体素子の表裏面間を電気的に接続する導通部を設
けた半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor device having a conductive portion which penetrates a semiconductor element in a thickness direction and electrically connects the front and back surfaces of the semiconductor element. And a method for producing the same.
【0002】[0002]
【従来の技術】回路基板に複数個の半導体素子を搭載し
た半導体装置はマルチチップモジュール(MCM)等と
して従来から使用されている。しかしながら、回路基板
に平面的に複数の半導体素子を搭載する場合は搭載する
スペースを広く確保する必要が生じるから、よりコンパ
クトに搭載する方法として、半導体素子自体を積み重ね
て三次元的に搭載する方法が考えられている。半導体素
子を積み重ねて回路基板に搭載する場合は、半導体素子
の表裏面間を電気的に接続しなければならない。半導体
素子の表裏面間を電気的に接続する方法としては、半導
体素子に貫通孔を設け貫通孔に金属あるいは導電性樹脂
等の導電材を充填して半導体素子の表裏面を電気的に接
続する導通部を形成する方法がある(特開平8-306724号
公報)。2. Description of the Related Art A semiconductor device having a plurality of semiconductor elements mounted on a circuit board has been conventionally used as a multi-chip module (MCM) or the like. However, when a plurality of semiconductor elements are mounted two-dimensionally on a circuit board, it is necessary to secure a large mounting space. As a more compact mounting method, a method of stacking the semiconductor elements themselves and three-dimensionally mounting them. Is considered. When semiconductor elements are stacked and mounted on a circuit board, the front and back surfaces of the semiconductor elements must be electrically connected. As a method of electrically connecting the front and back surfaces of the semiconductor element, a through hole is provided in the semiconductor element, and the through hole is filled with a conductive material such as a metal or a conductive resin to electrically connect the front and back surfaces of the semiconductor element. There is a method of forming a conductive portion (Japanese Patent Application Laid-Open No. 8-306724).
【0003】図8は、半導体素子10の表裏面を電気的
に接続する導通部を形成する製造工程を示す。図8(a)
は電極端子12が形成された半導体素子10の断面図で
あり、図8(b)は電極端子12の位置に貫通孔14を形
成した状態を示す。貫通孔14は電極端子12の位置と
同じ位置に形成してもよいし、電極端子12が形成され
た位置とは別の位置で半導体素子10の機能に支障のな
い位置に形成してもよい。この場合、電極端子12と貫
通孔14とは導体パターンにより電気的に接続される。
図8(c)は、貫通孔14に導電性樹脂を充填して導通部
16を形成した状態、図8(d)は、半導体素子10の下
面の導通部16に外部接続端子18を接合した状態を示
す。FIG. 8 shows a manufacturing process for forming a conductive portion for electrically connecting the front and back surfaces of the semiconductor element 10. Fig. 8 (a)
FIG. 8 is a cross-sectional view of the semiconductor element 10 on which the electrode terminals 12 are formed, and FIG. 8B shows a state where the through holes 14 are formed at the positions of the electrode terminals 12. The through hole 14 may be formed at the same position as the position of the electrode terminal 12, or may be formed at a position different from the position where the electrode terminal 12 is formed and at a position that does not hinder the function of the semiconductor element 10. . In this case, the electrode terminals 12 and the through holes 14 are electrically connected by a conductor pattern.
FIG. 8C shows a state in which a conductive portion 16 is formed by filling the through hole 14 with a conductive resin, and FIG. 8D shows an external connection terminal 18 joined to the conductive portion 16 on the lower surface of the semiconductor element 10. Indicates the status.
【0004】図8(d)に示す半導体装置11は導通部1
6を介して半導体素子10の表裏面が電気的に接続され
ているから、半導体素子10の電極端子12が形成され
た面を上向きにして実装することができ、複数の半導体
装置11を重ねるように配置して、相互に電気的に接続
することが可能となる。なお、図8に示す製造工程で
は、個片の半導体素子10を被加工品として製造するこ
ともできるし、半導体素子が多数個形成された半導体ウ
エハを被加工品として製造することも可能である。The semiconductor device 11 shown in FIG.
Since the front and back surfaces of the semiconductor element 10 are electrically connected via the semiconductor device 6, the semiconductor element 10 can be mounted with the surface on which the electrode terminals 12 are formed facing upward, so that the plurality of semiconductor devices 11 are stacked. And electrically connected to each other. In the manufacturing process shown in FIG. 8, the individual semiconductor element 10 can be manufactured as a workpiece, or a semiconductor wafer on which a large number of semiconductor elements are formed can be manufactured as a workpiece. .
【0005】[0005]
【発明が解決しようとする課題】上記のように半導体素
子10に貫通孔14を形成して導通部16を設ける場
合、従来は貫通孔14に導電性樹脂を充填する方法、あ
るいはめっきによって貫通孔14に導通部16を形成す
るといった方法が行われている。しかしながら、導電性
樹脂を使用する場合は電気的な接続抵抗が大きくなるこ
とから、このような半導体素子10を用いた半導体装置
は高速信号特性が劣化するという問題がある。また、め
っきによって導通部16を形成する場合は、めっきを付
着させない部位をレジスト膜によって被覆するといった
処理が必要となり、作業工程が複雑になるという問題が
ある。また、導通部16と半導体素子(シリコン)との
熱膨張係数の差によって生じる熱応力によって半導体素
子にクラックが生じるといった問題があった。As described above, when the conductive portion 16 is formed by forming the through hole 14 in the semiconductor element 10 as described above, the conventional method is to fill the through hole 14 with a conductive resin or by plating. For example, a method of forming a conductive portion 16 on the substrate 14 is performed. However, when a conductive resin is used, the electrical connection resistance increases, so that a semiconductor device using such a semiconductor element 10 has a problem in that high-speed signal characteristics deteriorate. Further, in the case where the conductive portion 16 is formed by plating, it is necessary to perform a process of covering a portion where no plating is to be adhered with a resist film, and there is a problem that a working process is complicated. In addition, there is a problem that a crack occurs in the semiconductor element due to a thermal stress caused by a difference in thermal expansion coefficient between the conductive portion 16 and the semiconductor element (silicon).
【0006】本発明は、これらの問題点を解消すべくな
されたものであり、その目的とするところは、半導体素
子の表裏面間を電気的に接続する導通部を設けた信頼性
の高い半導体装置を容易に製造でき、半導体素子を三次
元的に積み重ねることも容易に可能となる半導体装置の
製造方法を提供するものである。SUMMARY OF THE INVENTION The present invention has been made to solve these problems, and an object of the present invention is to provide a highly reliable semiconductor device having a conductive portion for electrically connecting the front and back surfaces of a semiconductor element. It is an object of the present invention to provide a method of manufacturing a semiconductor device in which a device can be easily manufactured and semiconductor elements can be easily stacked three-dimensionally.
【0007】[0007]
【課題を解決するための手段】上記目的を達成するた
め、本発明は次の構成を備える。すなわち、半導体素子
の一方の面に形成された電極端子あるいは該電極端子と
電気的に接続して形成されたランド部に、半導体素子を
厚さ方向に貫通する貫通孔を形成し、該貫通孔が形成さ
れた半導体素子を、該貫通孔が形成された位置に対応し
て前記貫通孔の開口径よりも大径の開口径を有する凹部
が形成された支持治具の前記凹部が形成された面に前記
貫通孔と凹部とが連通するように位置合わせして支持
し、前記貫通孔を通して前記支持治具の凹部に導電線材
の端部をボンディングするとともに、貫通孔から導電線
材を所定の長さ引き出して導電線材を切断し、該導電線
材の切断部が当接する部位に前記貫通孔の開口径よりも
大径の開口径を有する凹部が形成されたつぶし加工治具
と前記支持治具とで前記半導体素子を挟んで前記導電線
材をつぶし加工して、半導体素子の両面から両端部が突
出する外部接続用バンプを成形した後、前記半導体素子
を支持する支持治具を前記外部接続用バンプから分離す
ることを特徴とする。To achieve the above object, the present invention comprises the following arrangement. That is, a through hole penetrating the semiconductor element in the thickness direction is formed in an electrode terminal formed on one surface of the semiconductor element or a land portion formed by being electrically connected to the electrode terminal. The concave portion of the support jig was formed by forming a concave portion having an opening diameter larger than the opening diameter of the through hole corresponding to the position where the through hole was formed. The through-hole and the concave portion are aligned and supported so that they communicate with each other, the end of the conductive wire is bonded to the concave portion of the support jig through the through-hole, and the conductive wire is passed through the through-hole for a predetermined length. The crushing jig and the support jig, in which a recess having an opening diameter larger than the opening diameter of the through hole is formed at a portion where the cut portion of the conductive wire comes into contact with the drawn out and cut conductive wire, With the conductive element sandwiching the semiconductor element Processed to crush wood, after both end portions from both sides of the semiconductor element is molded with external connection bumps protruding, and separating the support jig that supports the semiconductor element from the external connection bumps.
【0008】また、前記導電線材として、金線を使用す
ることは外部接続用バンプの電気抵抗を下げ、半導体装
置の電気的特性を向上させることができる点、外部接続
用バンプと半導体素子との間で生じる熱応力を好適に緩
和できる点で有効である。また、前記前記支持治具とし
て、前記凹部の内面が金属層によって被覆された治具を
使用することにより、外部接続用バンプの成形が容易に
でき、外部接続用バンプの電気的接続の信頼性が高まる
という利点がある。また、前記前記支持治具及びつぶし
加工治具として、半球状の凹部が形成された治具を使用
することを特徴とする。また、前記支持治具と外部接続
用バンプとの分離を、該支持治具をエッチングによって
除去して行うことを特徴とする。The use of a gold wire as the conductive wire can reduce the electrical resistance of the external connection bump and improve the electrical characteristics of the semiconductor device. This is effective in that the thermal stress generated between them can be suitably reduced. Further, by using a jig in which the inner surface of the concave portion is covered with a metal layer as the support jig, it is possible to easily form the bump for external connection, and to improve the reliability of the electrical connection of the bump for external connection. There is an advantage that is increased. Further, a jig having a hemispherical concave portion is used as the support jig and the crushing jig. Further, the support jig is separated from the external connection bumps by removing the support jig by etching.
【0009】[0009]
【発明の実施の形態】以下、本発明の好適な実施形態に
ついて、添付図面に基づき詳細に説明する。図1、2、
3は本発明に係る半導体装置の製造工程を示す説明図で
ある。図1は、半導体素子10に貫通孔14を形成し、
貫通孔14を通して半導体素子10を支持する支持治具
20に金線24をボンディングするまでの工程、図2
は、支持治具20とつぶし加工治具30とで金線24を
つぶし加工して外部接続用バンプ40を形成するまでの
工程、図3は支持治具20を除去して外部接続用バンプ
40を形成した半導体装置を得る工程を示す。Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Figures 1, 2,
FIG. 3 is an explanatory view showing a manufacturing process of the semiconductor device according to the present invention. FIG. 1 shows a case where a through hole 14 is formed in a semiconductor element 10,
FIG. 2 shows a process until the gold wire 24 is bonded to the supporting jig 20 supporting the semiconductor element 10 through the through hole 14.
FIG. 3 shows a process until the gold wire 24 is crushed by the support jig 20 and the crushing jig 30 to form the external connection bumps 40. FIG. A step of obtaining a semiconductor device formed with is shown.
【0010】図1(a)は、被加工品の半導体素子10を
示す断面図である。半導体素子10は上面側に電極端子
12が形成されている。図1(b)は、半導体素子10の
電極端子12を形成した部位に貫通孔14を形成した状
態である。貫通孔14はレーザ光を半導体素子10に照
射して形成することができる。レーザ光を利用する方法
として、半導体素子10の貫通孔14を形成する部位に
向けて直径50μm程度の柱状に水を放射し、その柱状
の中にレーザ光を透過させて半導体素子10にレーザ光
を照射して貫通孔14を形成する方法がある。FIG. 1A is a sectional view showing a semiconductor element 10 to be processed. The semiconductor device 10 has an electrode terminal 12 formed on the upper surface side. FIG. 1B shows a state in which a through hole 14 is formed in a portion of the semiconductor element 10 where the electrode terminal 12 is formed. The through holes 14 can be formed by irradiating the semiconductor element 10 with laser light. As a method using laser light, water is radiated into a column having a diameter of about 50 μm toward a portion where the through hole 14 of the semiconductor element 10 is formed, and the laser light is transmitted through the column to transmit the laser light to the semiconductor element 10. Is applied to form the through holes 14.
【0011】図4に半導体素子10の厚さ方向に貫通孔
14を形成した状態の平面図を示す。本実施形態では電
極端子12の中央に貫通孔14を形成している。電極端
子12は1辺が80μm程度の矩形状に形成され、貫通
孔14は開口部の開口径を50μm程度に形成する。貫
通孔14の開口径を電極端子12よりも小さく設定する
のは、貫通孔14に形成する外部接続用バンプ40と電
極端子12とが確実に電気的に接続されるようにするた
めである。FIG. 4 is a plan view showing a state in which the through-hole 14 is formed in the thickness direction of the semiconductor element 10. In the present embodiment, a through hole 14 is formed at the center of the electrode terminal 12. The electrode terminal 12 is formed in a rectangular shape having one side of about 80 μm, and the through hole 14 is formed to have an opening diameter of about 50 μm. The reason why the opening diameter of the through hole 14 is set smaller than that of the electrode terminal 12 is to ensure that the external connection bumps 40 formed in the through hole 14 and the electrode terminal 12 are electrically connected.
【0012】なお、貫通孔14を形成する部位は、必ず
しも電極端子12の中央の位置に限るものではない。す
なわち、電極端子12の中央から偏位した位置で電極端
子12の領域と重複する位置に貫通孔14を形成しても
よいし、電極端子12が形成された位置から離間した位
置に貫通孔14を形成し、貫通孔14と電極端子12と
を導体パターンにより電気的に接続することも可能であ
る。外部接続用バンプ40は貫通孔14を形成した位置
に形成されるから、外部接続用バンプ40を形成した半
導体装置を積み重ねて三次元的に半導体装置を実装する
ことを考慮して貫通孔14の配置を設定する。Note that the portion where the through hole 14 is formed is not necessarily limited to the center position of the electrode terminal 12. That is, the through hole 14 may be formed at a position deviated from the center of the electrode terminal 12 and at a position overlapping the region of the electrode terminal 12, or at a position separated from the position where the electrode terminal 12 is formed. May be formed, and the through hole 14 and the electrode terminal 12 may be electrically connected by a conductor pattern. Since the external connection bumps 40 are formed at the positions where the through holes 14 are formed, the semiconductor devices on which the external connection bumps 40 are formed are stacked and the through holes 14 are formed in consideration of the three-dimensional mounting of the semiconductor device. Set the placement.
【0013】図1(c)は、半導体素子10を支持治具2
0に位置合わせして支持した状態を示す。支持治具20
は半導体素子10を支持する治具であり、半導体素子1
0に形成する貫通孔14の各々の位置に合わせて凹部2
0aを形成し、凹部20aの内面に、めっき等によって
パラジウムや金からなる金属層22を形成したものであ
る。凹部20aは外部接続用バンプ40を形成する際に
バンプの端部を半球状に形成するためのもので、凹部2
0aの内面形状はバンプの形状に合わせて半球状に形成
されている。金属層22は外部接続用バンプ40の一部
となるものである。なお、支持治具20はすべての貫通
孔14に外部接続用バンプ40を形成した後、半導体素
子10から除去される。したがって、エッチング等によ
って容易に除去できる素材、たとえばガラス板、銅板等
を使用する。FIG. 1C shows a semiconductor device 10 supported by a support jig 2.
It shows a state where it is positioned and supported by zero. Support jig 20
Is a jig for supporting the semiconductor element 10 and the semiconductor element 1
The concave portion 2 is aligned with each position of the through hole 14 formed at
0a, and a metal layer 22 made of palladium or gold is formed on the inner surface of the recess 20a by plating or the like. The concave portion 20a is for forming the end of the bump in a hemispherical shape when the external connection bump 40 is formed.
The inner surface shape of Oa is formed in a hemispherical shape according to the shape of the bump. The metal layer 22 becomes a part of the external connection bump 40. The support jig 20 is removed from the semiconductor element 10 after forming the external connection bumps 40 in all the through holes 14. Therefore, a material that can be easily removed by etching or the like, such as a glass plate or a copper plate, is used.
【0014】図1(d)は、ワイヤボンディング用のツー
ル23を用いて貫通孔14内に金線24を立てる工程で
ある。貫通孔14の直下に支持治具20に形成した凹部
20aが位置し、貫通孔14の底部に金属層22が位置
しているから、貫通孔14にツール23を差し込むよう
にして金属層22に金線24をワイヤボンディングする
ことができる。図1(d)は、金線24の先端に形成した
ボール部を金属層22にボンディングした状態である。FIG. 1 (d) shows a step of erecting a gold wire 24 in the through hole 14 using a wire bonding tool 23. Since the concave portion 20a formed in the support jig 20 is located immediately below the through hole 14 and the metal layer 22 is located at the bottom of the through hole 14, the tool 23 is inserted into the through hole 14 so that the metal layer 22 is formed. The gold wire 24 can be wire-bonded. FIG. 1D shows a state in which a ball portion formed at the tip of the gold wire 24 is bonded to the metal layer 22.
【0015】図1(e)は、ツール23を貫通孔14の上
方に引き上げて金線24を貫通孔14の開口部の上方に
引き出した状態である。図1(f)は、引き出した金線2
4を所定長さで切断した状態である。金線24は引きち
ぎるようにして切断することができる。金線24を貫通
孔14の開口部の上方に引き出して切断することによっ
て金線24は支持治具20によって支持され、貫通孔1
4を通して起立して支持される。なお、金線24の切断
長さは、つぶし加工した際に貫通孔14が金によって埋
まり、半導体素子10の表裏面から突出するバンプを形
成するに必要な長さとする。ボンディングに使用する金
線24の太さは25μm程度である。FIG. 1E shows a state in which the tool 23 is pulled up above the through hole 14 and the gold wire 24 is drawn out above the opening of the through hole 14. FIG. 1 (f) shows the drawn gold wire 2
4 is cut into a predetermined length. The gold wire 24 can be cut off like a tear. By pulling out the gold wire 24 above the opening of the through-hole 14 and cutting it, the gold wire 24 is supported by the support jig 20 and the through-hole 1
4 stands up and is supported. Note that the cut length of the gold wire 24 is a length necessary to form a bump projecting from the front and back surfaces of the semiconductor element 10 by filling the through hole 14 with gold when crushing. The thickness of the gold wire 24 used for bonding is about 25 μm.
【0016】図1(g)は、上述したと同様に、半導体素
子10のすべての貫通孔14について、金線24をワイ
ヤボンディングし、各々の貫通孔14について、金線2
4を所定の長さに切断して、起立して支持した状態を示
す。このようにすべての貫通孔14について、金線24
を所定の長さで起立させて支持治具20に支持すること
は、通常のワイヤボンディング法を利用することによっ
て、容易にかつ効率的に行うことができる。FIG. 1 (g) shows that the gold wire 24 is wire-bonded to all the through holes 14 of the semiconductor element 10 and the gold wire 2 is
4 shows a state where the sheet 4 is cut to a predetermined length and is supported upright. In this way, the gold wire 24
Can be easily and efficiently raised by a predetermined length and supported by the support jig 20 by using a normal wire bonding method.
【0017】図2(a)は、半導体素子10の貫通孔14
内で起立して支持治具20に支持されている金線24の
上方につぶし加工治具30を配置した状態である。つぶ
し加工治具30の、金線24の切断端部が当接する加圧
面には、外部接続用バンプ40を半球状に成形するため
の凹部30aが形成されている。凹部30aの開口径は
貫通孔14の開口径よりも若干大きく設定し、金線24
をつぶし加工した際に、バンプ部分が半導体素子10の
電極端子12を覆って、外部接続用バンプ40と電極端
子12とが確実に電気的に接続されるようにしている。FIG. 2A shows the through hole 14 of the semiconductor element 10.
In this state, the crushing jig 30 is arranged above the gold wire 24 that stands up inside and is supported by the supporting jig 20. On the pressing surface of the crushing jig 30 where the cut end of the gold wire 24 contacts, a concave portion 30a for forming the external connection bump 40 into a hemispherical shape is formed. The opening diameter of the recess 30 a is set slightly larger than the opening diameter of the through hole 14,
When crushing is performed, the bump portions cover the electrode terminals 12 of the semiconductor element 10 so that the external connection bumps 40 and the electrode terminals 12 are reliably electrically connected.
【0018】図2(b)は、つぶし加工治具30により金
線24をつぶし加工した状態を示す。支持治具20によ
って半導体素子10を支持し、つぶし加工治具30によ
って金線24をその切断部の上方から加圧することによ
り、貫通孔14が金によって埋まり、貫通孔14の両面
に半球状のバンプが成形される。図2(c)は、支持治具
20に支持されたすべての金線24について、同様につ
ぶし加工を行って各々の貫通孔14に外部接続用バンプ
40を形成した状態を示す。FIG. 2B shows a state in which the gold wire 24 is crushed by the crushing jig 30. When the semiconductor element 10 is supported by the support jig 20 and the gold wire 24 is pressed from above the cut portion by the crushing jig 30, the through-hole 14 is filled with gold, and a hemispherical shape is formed on both surfaces of the through-hole 14. A bump is formed. FIG. 2C shows a state in which all the gold wires 24 supported by the support jig 20 are similarly crushed to form the external connection bumps 40 in the respective through holes 14.
【0019】支持治具20とつぶし加工治具30に形成
する凹部20a、30aの開口径を貫通孔14の開口径
よりも若干大径とすることによって、外部接続用バンプ
40の両端部の周縁が貫通孔14の開口部の周縁を係止
するように成形され、外部接続用バンプ40が貫通孔1
4から抜け落ちることがない。なお、金線24をつぶし
加工する際には、支持治具20とつぶし加工治具30を
200℃程度に加熱して、金線24を成形しやすくして
加工するのがよい。また、金線24をつぶし加工する際
には、図2(a)、(b)に示すように金線24を1本ずつつ
ぶし加工してもよいし、金線24を一度につぶし加工し
てもよい。金線24を一度につぶし加工する際は、たと
えば、平板状の加圧面に各々の貫通孔14の位置に合わ
せて半球状のバンプを成形するための凹部を形成したつ
ぶし加工治具を使用して加工することができる。By making the opening diameters of the recesses 20a, 30a formed in the supporting jig 20 and the crushing jig 30 slightly larger than the opening diameter of the through hole 14, the peripheral edges of both ends of the external connection bump 40 are formed. Are formed so as to lock the periphery of the opening of the through hole 14, and the external connection bump 40 is
It does not fall out of 4. When the gold wire 24 is crushed, the supporting jig 20 and the crushing jig 30 are preferably heated to about 200 ° C. so that the gold wire 24 is easily formed. Further, when the gold wire 24 is crushed, the gold wire 24 may be crushed one by one as shown in FIGS. 2A and 2B, or the gold wire 24 may be crushed at a time. You may. When the gold wire 24 is crushed at a time, for example, a crushing jig in which a concave portion for forming a hemispherical bump in accordance with the position of each through hole 14 is formed on a flat pressing surface is used. Can be processed.
【0020】上記のように、ワイヤボンディング用のツ
ール23を用いて支持治具20の金属層22に金線24
をボンディングする操作は、従来のワイヤボンディング
と同様の操作によって行えるから、従来装置及び従来方
法が適用でき、能率的な操作によって行えるという利点
がある。また、つぶし加工治具30を用いて外部接続用
バンプ40を成形する容易にかつ能率的に行えるという
利点がある。As described above, the gold wire 24 is applied to the metal layer 22 of the support jig 20 by using the wire bonding tool 23.
Can be performed by the same operation as the conventional wire bonding, so that the conventional apparatus and the conventional method can be applied, and there is an advantage that the operation can be performed by an efficient operation. In addition, there is an advantage that the external connection bumps 40 can be easily and efficiently formed using the crushing jig 30.
【0021】図5は、金線24をつぶし加工して外部接
続用バンプ40を成形した状態の平面図を示す。同図で
は、金線24をつぶし加工した状態と、金線24をつぶ
し加工する前の状態を示す。貫通孔14の開口径よりも
外部接続用バンプ40の外周径を大径に形成して、半球
状のバンプ部分と電極端子12とが電気的に接続するよ
うに形成することを示す。電極端子12をアルミニウム
等の金と接合しやすい金属によって形成しておけば、金
線24をつぶし加工した際に電極端子12と外部接続用
バンプ40との電気的接続がさらに確実となる。FIG. 5 is a plan view showing a state in which the gold wire 24 is crushed and the external connection bumps 40 are formed. The figure shows a state in which the gold wire 24 is crushed and a state before the gold wire 24 is crushed. This shows that the outer diameter of the external connection bump 40 is formed to be larger than the opening diameter of the through hole 14 so that the hemispherical bump portion and the electrode terminal 12 are electrically connected. If the electrode terminals 12 are formed of a metal such as aluminum which can be easily bonded to gold, the electrical connection between the electrode terminals 12 and the external connection bumps 40 is further ensured when the gold wire 24 is crushed.
【0022】図6は、半導体素子10の電極端子12が
形成された位置から離間した位置に貫通孔14を設けた
例である。13は電極端子12と外部接続用バンプ40
とを電気的に接続するための導体パターン、13aは貫
通孔14の開口部の近傍に形成したリング状のランド部
である。このランド部13aは導体パターン13に接続
して貫通孔14よりも若干大径の円形のランド部を形成
しておき、ランド部の領域内に貫通孔14を形成するこ
とにより貫通孔14の周縁部にリング状に形成される。
貫通孔14の周縁部にリング状のランド部13aを形成
することにより、金線24をつぶし加工して外部接続用
バンプ40を成形した際に、ランド部13aに外部接続
用バンプ40が当接して外部接続用バンプ40と電極端
子12とが確実に電気的に接続される。図6は、貫通孔
14にランド部13aが形成された状態と、いくつかの
貫通孔14に外部接続用バンプ40を形成した状態を示
す。FIG. 6 shows an example in which a through hole 14 is provided at a position separated from a position where the electrode terminal 12 of the semiconductor element 10 is formed. 13 denotes an electrode terminal 12 and an external connection bump 40
13a is a ring-shaped land formed near the opening of the through hole 14. The land portion 13a is connected to the conductor pattern 13 to form a circular land portion having a diameter slightly larger than that of the through hole 14, and by forming the through hole 14 in the land area, the periphery of the through hole 14 is formed. The part is formed in a ring shape.
By forming the ring-shaped land portion 13a on the periphery of the through hole 14, the external connection bump 40 abuts on the land portion 13a when the gold wire 24 is crushed to form the external connection bump 40. Thus, the external connection bumps 40 and the electrode terminals 12 are reliably electrically connected. FIG. 6 shows a state in which the land portions 13 a are formed in the through holes 14 and a state in which the external connection bumps 40 are formed in some of the through holes 14.
【0023】図3(a)は、前述したように、半導体素子
10のすべての貫通孔14に外部接続用バンプ40を形
成した状態である。図3(b)は、半導体素子10を支持
する支持治具20を除去して貫通孔14に外部接続用バ
ンプ40が形成された半導体装置50を得た状態であ
る。図3(a)の状態から支持治具20を機械的に取り除
くか、化学的に支持治具20を溶解除去することによっ
て半導体装置50を得ることができる。半導体装置50
に形成された外部接続用バンプ40の両端部には、半導
体素子10の表面から半球状に突出するバンプ部40
a、40bが形成され、外部接続用バンプ40を介して
半導体素子10の表面に形成された電極端子12と半導
体素子10の裏面とが電気的に接続されている。FIG. 3A shows a state in which the external connection bumps 40 are formed in all the through holes 14 of the semiconductor element 10 as described above. FIG. 3B shows a state in which the support jig 20 for supporting the semiconductor element 10 is removed to obtain a semiconductor device 50 in which the external connection bumps 40 are formed in the through holes 14. The semiconductor device 50 can be obtained by mechanically removing the support jig 20 from the state of FIG. 3A or chemically dissolving and removing the support jig 20. Semiconductor device 50
The bumps 40 projecting hemispherically from the surface of the semiconductor element 10 are provided at both ends of the external connection bumps 40 formed on the semiconductor device 10.
a, 40b are formed, and the electrode terminals 12 formed on the front surface of the semiconductor element 10 and the back surface of the semiconductor element 10 are electrically connected via the external connection bumps 40.
【0024】図7は、上述した製造方法によって製造し
た半導体装置50を実装基板60に実装した例を示す。
この例は半導体装置50を4枚積み重ねたものである。
各層の半導体装置50は外部接続用バンプ40の半球状
に突出するバンプ部40a、40bを介して電気的に接
続され、すべての半導体装置50が電気的に接続され
る。62は実装基板60に取り付けた外部接続端子、6
4は実装基板60と最下層の半導体装置50の実装面と
の間を封止するアンダーフィル材である。FIG. 7 shows an example in which the semiconductor device 50 manufactured by the above-described manufacturing method is mounted on a mounting board 60.
In this example, four semiconductor devices 50 are stacked.
The semiconductor devices 50 of the respective layers are electrically connected via hemispherical bump portions 40a and 40b of the external connection bumps 40, and all the semiconductor devices 50 are electrically connected. 62 is an external connection terminal attached to the mounting board 60;
Reference numeral 4 denotes an underfill material for sealing between the mounting board 60 and the mounting surface of the lowermost semiconductor device 50.
【0025】このように、半導体素子10を厚さ方向に
貫通して形成した外部接続用バンプ40を備えた半導体
装置50によれば、半導体装置50を積み重ねて立体的
に実装することが容易に可能であり、複数個の半導体装
置を実装する場合でも実装面積を最小限にすることがで
きる。最近は厚さ100μmといった薄い半導体素子が
提供されるようになってきているから、三次元的に半導
体装置を積み重ねた場合でも、装置全体の厚さがそれほ
ど厚くならないという利点がある。As described above, according to the semiconductor device 50 having the external connection bumps 40 formed by penetrating the semiconductor element 10 in the thickness direction, the semiconductor devices 50 can be easily stacked and mounted three-dimensionally. The mounting area can be minimized even when a plurality of semiconductor devices are mounted. Recently, thin semiconductor elements having a thickness of 100 μm have been provided, so that even when three-dimensionally stacked semiconductor devices, there is an advantage that the overall thickness of the device is not so large.
【0026】なお、前述した半導体装置の製造方法の実
施形態では、個片の半導体素子10を被加工品として所
要の加工を施したが、半導体素子10が多数個形成され
た半導体ウエハを被加工品として同様な加工を行って個
片の半導体装置を得ることも可能である。半導体ウエハ
を被加工品とする場合は、半導体ウエハの状態で各々の
半導体素子に貫通孔を形成し、貫通孔にボンディングに
より起立させた金線をつぶし加工して接続バンプを形成
した後、半導体ウエハを個片に分割して個々の半導体装
置を得ればよい。In the above-described embodiment of the method of manufacturing a semiconductor device, the required processing is performed using the individual semiconductor elements 10 as workpieces, but the semiconductor wafer on which a large number of semiconductor elements 10 are formed is processed. It is also possible to obtain individual semiconductor devices by performing similar processing as a product. When a semiconductor wafer is to be processed, a through hole is formed in each semiconductor element in a state of the semiconductor wafer, and a gold wire erected by bonding is crushed in the through hole to form a connection bump, and then a semiconductor bump is formed. The semiconductor device may be obtained by dividing the wafer into individual pieces.
【0027】また、前述した実施形態では、金線を用い
て外部接続用バンプ40を形成したが、金線のかわりに
銅線、はんだ線等の他の導電線材を使用することもでき
る。これらの導電線材を使用する場合も、加工方法は上
記実施形態と同様である。なお、金線24をつぶし加工
して外部接続用バンプ40を形成する方法によれば、導
通部にボイドが発生したりすることがなく、導通部の電
気的抵抗を小さくすることができ、半導体装置の高速信
号特性等の電気的特性を良好にすることができるという
利点がある。また、外部接続用バンプ40を金によって
形成することによって、電気的接続の確実性、信頼性を
得ることが可能である。In the above-described embodiment, the external connection bumps 40 are formed using gold wires. However, other conductive wires such as copper wires and solder wires can be used instead of gold wires. When these conductive wires are used, the processing method is the same as in the above embodiment. According to the method of forming the external connection bumps 40 by crushing the gold wire 24, no void is generated in the conductive portion, and the electrical resistance of the conductive portion can be reduced. There is an advantage that electrical characteristics such as high-speed signal characteristics of the device can be improved. Further, by forming the external connection bumps 40 of gold, it is possible to obtain the reliability and reliability of the electrical connection.
【0028】[0028]
【発明の効果】本発明に係る半導体装置の製造方法によ
れば、上述したように、半導体素子を貫通して設けられ
る導通部としての外部接続用バンプを備えた半導体装置
を容易に製造することができる。これによって、半導体
装置を積み重ねて立体的に実装する等の実装方法に好適
に使用できる半導体装置を提供することが可能になる等
の著効を奏する。According to the method of manufacturing a semiconductor device according to the present invention, as described above, it is possible to easily manufacture a semiconductor device having an external connection bump as a conductive portion provided through a semiconductor element. Can be. As a result, it is possible to provide a semiconductor device that can be suitably used for a mounting method such as stacking and three-dimensionally mounting semiconductor devices, and the like, and it is possible to provide a remarkable effect.
【図1】本発明に係る半導体装置の製造方法を示す説明
図である。FIG. 1 is an explanatory view illustrating a method for manufacturing a semiconductor device according to the present invention.
【図2】本発明に係る半導体装置の製造方法を示す説明
図である。FIG. 2 is an explanatory view illustrating a method for manufacturing a semiconductor device according to the present invention.
【図3】本発明に係る半導体装置の製造方法を示す説明
図である。FIG. 3 is an explanatory view illustrating a method for manufacturing a semiconductor device according to the present invention.
【図4】半導体素子に貫通孔を形成した状態の平面図で
ある。FIG. 4 is a plan view showing a state in which a through hole is formed in the semiconductor element.
【図5】貫通孔に外部接続用バンプを形成した状態の平
面図である。FIG. 5 is a plan view showing a state in which an external connection bump is formed in a through hole.
【図6】貫通孔に外部接続用バンプを形成した状態の平
面図である。FIG. 6 is a plan view showing a state in which a bump for external connection is formed in a through hole.
【図7】半導体装置を実装した状態を示す断面図であ
る。FIG. 7 is a cross-sectional view showing a state where the semiconductor device is mounted.
【図8】半導体装置の従来の製造方法を示す説明図であ
る。FIG. 8 is an explanatory view showing a conventional method for manufacturing a semiconductor device.
10 半導体素子 12 電極端子 13 導体パターン 13a ランド部 14 貫通孔 16 導通部 18 接続端子 20 支持治具 20a 凹部 22 金属層 23 ツール 24 金線 30 つぶし加工治具 30a 凹部 40 外部接続用バンプ 40a、40b バンプ部 50 半導体装置 60 実装基板 DESCRIPTION OF SYMBOLS 10 Semiconductor element 12 Electrode terminal 13 Conductor pattern 13a Land part 14 Through hole 16 Conducting part 18 Connection terminal 20 Support jig 20a Depression 22 Metal layer 23 Tool 24 Gold wire 30 Squeezing jig 30a Depression 40 External connection bump 40a, 40b Bump part 50 Semiconductor device 60 Mounting board
Claims (5)
端子あるいは該電極端子と電気的に接続して形成された
ランド部に、半導体素子を厚さ方向に貫通する貫通孔を
形成し、 該貫通孔が形成された半導体素子を、該貫通孔が形成さ
れた位置に対応して前記貫通孔の開口径よりも大径の開
口径を有する凹部が形成された支持治具の前記凹部が形
成された面に前記貫通孔と凹部とが連通するように位置
合わせして支持し、 前記貫通孔を通して前記支持治具の凹部に導電線材の端
部をボンディングするとともに、貫通孔から導電線材を
所定の長さ引き出して導電線材を切断し、 該導電線材の切断部が当接する部位に前記貫通孔の開口
径よりも大径の開口径を有する凹部が形成されたつぶし
加工治具と前記支持治具とで前記半導体素子を挟んで前
記導電線材をつぶし加工して、半導体素子の両面から両
端部が突出する外部接続用バンプを成形した後、 前記半導体素子を支持する支持治具を前記外部接続用バ
ンプから分離することを特徴とする半導体装置の製造方
法。1. A through hole penetrating a semiconductor element in a thickness direction is formed in an electrode terminal formed on one surface of a semiconductor element or a land portion formed by being electrically connected to the electrode terminal. The semiconductor element having the through-hole formed therein is formed in such a manner that the concave portion of the supporting jig in which a concave portion having an opening diameter larger than the opening diameter of the through hole is formed corresponding to the position where the through hole is formed. Positioning and supporting the through hole and the recess so that the formed surface communicates with the formed surface, bonding the end of the conductive wire to the recess of the support jig through the through hole, and transferring the conductive wire from the through hole. A squeezing jig having a concave portion having an opening diameter larger than the opening diameter of the through hole formed at a portion where the cut portion of the conductive wire comes into contact with the conductive wire rod by drawing out the predetermined length, and With the jig sandwiching the semiconductor element After crushing the conductive wire to form external connection bumps whose both ends project from both surfaces of the semiconductor element, a support jig for supporting the semiconductor element is separated from the external connection bump. A method for manufacturing a semiconductor device.
特徴とする請求項1記載の半導体装置の製造方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein a gold wire is used as the conductive wire.
金属層によって被覆された治具を使用することを特徴と
する請求項1または2記載の半導体装置の製造方法。3. The method for manufacturing a semiconductor device according to claim 1, wherein a jig having an inner surface of the recess covered with a metal layer is used as the support jig.
て、半球状の凹部が形成された治具を使用することを特
徴とする請求項1、2または3記載の半導体装置の製造
方法。4. The method for manufacturing a semiconductor device according to claim 1, wherein a jig having a hemispherical concave portion is used as the supporting jig and the crushing jig.
離を、該支持治具をエッチングによって除去して行うこ
とを特徴とする請求項1、2、3または4記載の半導体
装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 1, wherein the separation of the support jig from the external connection bumps is performed by removing the support jig by etching. Method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000116648A JP2001308122A (en) | 2000-04-18 | 2000-04-18 | Method of manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000116648A JP2001308122A (en) | 2000-04-18 | 2000-04-18 | Method of manufacturing semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2001308122A true JP2001308122A (en) | 2001-11-02 |
Family
ID=18628086
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000116648A Pending JP2001308122A (en) | 2000-04-18 | 2000-04-18 | Method of manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2001308122A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1605738A1 (en) | 2004-06-09 | 2005-12-14 | Shinko Electric Industries Co., Ltd. | Method for production of semiconductor package |
JP2006156436A (en) * | 2004-11-25 | 2006-06-15 | Shinko Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
JP2008546174A (en) * | 2005-05-19 | 2008-12-18 | マイクロン テクノロジー, インク. | Backside processing method and system for manufacturing semiconductor devices using conductive interconnects |
JP2009506539A (en) * | 2005-08-24 | 2009-02-12 | マイクロン テクノロジー, インク. | Microelectronic devices and microelectronic support devices and related assemblies and methods |
JP2009135193A (en) * | 2007-11-29 | 2009-06-18 | Powertech Technology Inc | Semiconductor chip device with silicon through hole, and manufacturing method thereof |
US7919846B2 (en) | 2005-04-08 | 2011-04-05 | Micron Technology, Inc. | Stacked semiconductor component having through wire interconnect |
US8120167B2 (en) | 2006-04-24 | 2012-02-21 | Micron Technology, Inc. | System with semiconductor components having encapsulated through wire interconnects (TWI) |
US9013044B2 (en) | 2005-12-07 | 2015-04-21 | Micron Technology, Inc. | Through wire interconnect (TWI) for semiconductor components having wire in via and bonded connection with substrate contact |
-
2000
- 2000-04-18 JP JP2000116648A patent/JP2001308122A/en active Pending
Cited By (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7262076B2 (en) | 2004-06-09 | 2007-08-28 | Shinko Electric Industries Co., Ltd. | Method for production of semiconductor package |
KR101124547B1 (en) | 2004-06-09 | 2012-03-15 | 신꼬오덴기 고교 가부시키가이샤 | Method for production of semiconductor package |
EP1605738A1 (en) | 2004-06-09 | 2005-12-14 | Shinko Electric Industries Co., Ltd. | Method for production of semiconductor package |
JP4528100B2 (en) * | 2004-11-25 | 2010-08-18 | 新光電気工業株式会社 | Semiconductor device and manufacturing method thereof |
JP2006156436A (en) * | 2004-11-25 | 2006-06-15 | Shinko Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
US8053909B2 (en) | 2005-04-08 | 2011-11-08 | Micron Technology, Inc. | Semiconductor component having through wire interconnect with compressed bump |
US7919846B2 (en) | 2005-04-08 | 2011-04-05 | Micron Technology, Inc. | Stacked semiconductor component having through wire interconnect |
US8546931B2 (en) | 2005-05-19 | 2013-10-01 | Micron Technology, Inc. | Stacked semiconductor components having conductive interconnects |
JP2008546174A (en) * | 2005-05-19 | 2008-12-18 | マイクロン テクノロジー, インク. | Backside processing method and system for manufacturing semiconductor devices using conductive interconnects |
US9129862B2 (en) | 2005-08-24 | 2015-09-08 | Micron Technology, Inc. | Microelectronic devices and microelectronic support devices, and associated assemblies and methods |
US7968369B2 (en) | 2005-08-24 | 2011-06-28 | Micron Technology, Inc. | Microelectronic devices and microelectronic support devices, and associated assemblies and methods |
JP2009506539A (en) * | 2005-08-24 | 2009-02-12 | マイクロン テクノロジー, インク. | Microelectronic devices and microelectronic support devices and related assemblies and methods |
US8174101B2 (en) | 2005-08-24 | 2012-05-08 | Micron Technology, Inc. | Microelectronic devices and microelectronic support devices, and associated assemblies and methods |
US8778732B2 (en) | 2005-08-24 | 2014-07-15 | Micron Technology, Inc. | Microelectronic devices and microelectronic support devices, and associated assemblies and methods |
US9013044B2 (en) | 2005-12-07 | 2015-04-21 | Micron Technology, Inc. | Through wire interconnect (TWI) for semiconductor components having wire in via and bonded connection with substrate contact |
US8120167B2 (en) | 2006-04-24 | 2012-02-21 | Micron Technology, Inc. | System with semiconductor components having encapsulated through wire interconnects (TWI) |
US8581387B1 (en) | 2006-04-24 | 2013-11-12 | Micron Technology, Inc. | Through wire interconnect (TWI) having bonded connection and encapsulating polymer layer |
US8741667B2 (en) | 2006-04-24 | 2014-06-03 | Micron Technology, Inc. | Method for fabricating a through wire interconnect (TWI) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer |
US8404523B2 (en) | 2006-04-24 | 2013-03-26 | Micron Technoloy, Inc. | Method for fabricating stacked semiconductor system with encapsulated through wire interconnects (TWI) |
US8217510B2 (en) | 2006-04-24 | 2012-07-10 | Micron Technology, Inc. | Semiconductor module system having stacked components with encapsulated through wire interconnects (TWI) |
US9018751B2 (en) | 2006-04-24 | 2015-04-28 | Micron Technology, Inc. | Semiconductor module system having encapsulated through wire interconnect (TWI) |
JP2009135193A (en) * | 2007-11-29 | 2009-06-18 | Powertech Technology Inc | Semiconductor chip device with silicon through hole, and manufacturing method thereof |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10510659B2 (en) | Substrate-less stackable package with wire-bond interconnect | |
US5481133A (en) | Three-dimensional multichip package | |
US10297582B2 (en) | BVA interposer | |
US6022758A (en) | Process for manufacturing solder leads on a semiconductor device package | |
JP3186941B2 (en) | Semiconductor chips and multi-chip semiconductor modules | |
US6582992B2 (en) | Stackable semiconductor package and wafer level fabrication method | |
JP4813035B2 (en) | Manufacturing method of substrate with through electrode | |
US7563640B2 (en) | Semiconductor device including semiconductor element surrounded by an insulating member and wiring structures on upper and lower surfaces of the semiconductor element and insulating member, and manufacturing method thereof | |
KR101895019B1 (en) | Stackable molded microelectronic packages with area array unit connectors | |
US8154110B2 (en) | Double-faced electrode package and its manufacturing method | |
CN113130464B (en) | Package structure and method for manufacturing the same | |
US20070045812A1 (en) | Microfeature assemblies including interconnect structures and methods for forming such interconnect structures | |
JP2017038074A (en) | Method for assembling microelectronic package | |
US20100230795A1 (en) | Stacked microelectronic assemblies having vias extending through bond pads | |
EP1111676A2 (en) | Unit interconnection substrate for electronic parts | |
US8202762B2 (en) | Stack package having reduced electrical connection length suitable for high speed operations and method of manufacturing the same | |
US5863812A (en) | Process for manufacturing a multi layer bumped semiconductor device | |
TW202030848A (en) | Semiconductor package, semiconductor package stack and manufacturing method thereof | |
CN111128920A (en) | Semiconductor device and manufacturing method thereof | |
US6400034B1 (en) | Semiconductor device | |
US11362057B2 (en) | Chip package structure and manufacturing method thereof | |
JP2001308122A (en) | Method of manufacturing semiconductor device | |
KR101761502B1 (en) | Semiconductor Device And Fabricating Method Thereof | |
CN112838067A (en) | Chip packaging structure and manufacturing method thereof | |
KR100249539B1 (en) | A semiconductor chip and a method of manufacturing the same |