JP2001297592A - Non-volatile memory and drive method for non-volatile memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a non-volatile memory in which occurrence of read-disturb phenomenon is suppressed by controlling read-out voltage applied to a memory cell and defective read-out can be reduced. SOLUTION: A non-volatile memory is provided with a read-out control circuit controlling signals of word lines WLC connected to memory cells 11,1-1n,m. The read-out control circuit receives an address signal varied by the prescribed period, and applies a signal of an active level to word lines WLC designated by the address signal. And after a sense amplifier 8 decides data output of a memory cell and before the prescribed period elapses after voltage of an active level is applied, voltage of the word lines WLC is made to a non-active level. A non-volatile memory in which defective read-out can be reduced is realized by preventing that read-out voltage is applied to a specific memory cell for a long time to suppress occurrence of read-disturb phenomenon.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile memory device, and more particularly, to a non-volatile memory device and a method of driving a non-volatile memory which suppress the occurrence of a read disturb phenomenon.

[0002]

2. Description of the Related Art In a nonvolatile memory device, a read disturb phenomenon occurs when a long-time voltage application or frequent access to a specific address of a memory cell occurs. The read disturb phenomenon is a phenomenon in which electrons are gradually injected from a word line into a floating gate of a memory cell to which a read voltage is applied. When the read disturb phenomenon occurs, the threshold voltage of an erased cell in which electrons are not injected into the floating gate increases. Then, a current between the drain and the source hardly flows during the reading. for that reason,
The erased cell is erroneously recognized as a write cell into which electrons have been injected in advance, and may cause a read failure.

FIG. 7 is a circuit diagram showing an example of a conventional nonvolatile memory device. The operation of the circuit shown in FIG. 7 will be described. First, the address signal A input to the decode circuit 3
The DDR, specific word line, for example, WL ₁ is selected. On the other hand, the bit line BL is selected by the address signal ADDR input to the Y selector 7, and the memory cell is specified.

FIG. 8 shows a timing chart of each signal of the circuit of FIG. Address signal ADDR changes according to clock signal CLK. When the signal S0 of the word line WL ₁ is active level (H (high) level), a read voltage is applied to the control gates of the memory cells ₁ 1,1 _{~1 1, m.} That period is one clock period (T1).

When electrons are injected into the floating gates of the memory cells 11, ₁ to _{11, and m} when the read voltage is applied, no current flows through the bit line BL, and if no electrons are injected, , Current flows. Generally, the current flowing through the bit line BL is extremely small, and the current is amplified by the sense amplifier 8 having a plurality of sense amplifier elements, and is determined as memory cell data. The memory cell data is held by the latch circuit 9 during the low level (L (low) level) of the clock signal CLK, and the data signals DATA _{1 to} DATA
Output as _k .

[0006]

In a microcomputer with a built-in flash memory, a low-power standby application program uses a low-frequency subclock signal SUBCL to reduce power consumption.
It may be switched to K and used.

[0007] The circuit shown in FIG.
FIG. 9 shows a timing chart of each signal when BCLK is used. The period (T1 ') during which the read voltage is applied to the memory cell is longer than the period (T1) when using the clock signal CLK shown in FIG. Also, the application program in the low power standby mode often loops, and thus frequently accesses a specific address. As described above, when the subclock signal SUBCLK is used, there is a problem that the read disturb phenomenon is more likely to occur than in the normal operation, and it becomes difficult to hold data in the flash memory.

As a technique for suppressing stress applied to unselected memory cells, there is a technique disclosed in Japanese Patent Application Laid-Open No. Hei 6-176585. However, this method controls the signal of the bit line and cannot contribute to the suppression of the read disturb phenomenon due to the application of the read voltage to the control gate.

Further, a technique relating to the read disturb phenomenon is disclosed in Japanese Patent Application Laid-Open No. Hei 10-199267. However, this technique is based on the premise that a read disturb phenomenon occurs, and suppresses the distribution of the threshold voltage of a memory cell to reduce the adverse effect of the phenomenon. This technique is based on the premise that a read disturb phenomenon occurs, and cannot contribute to the essential solution of the problem.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a nonvolatile memory device which suppresses the occurrence of a read disturb phenomenon and reduces read defects.

[0011]

In order to achieve the above object, a nonvolatile memory device according to a first aspect of the present invention comprises:
Arranged in a matrix, each having a floating gate, a control gate, and a current path, according to the charge charged to the floating gate and the voltage application to the control gate,
A memory cell (1) for outputting data, a plurality of word lines (WLC) connected to a control gate of the memory cell in a corresponding row, and a plurality of word lines (WLC) connected to a source or a drain of the memory cell in a corresponding column Bit line (BL),
A sense amplifier (8) electrically connected to the bit line to determine the data output of the memory cell; an active level voltage applied to the word line specified by the address signal upon receiving an address signal that changes every predetermined period; Read control for setting the word line voltage to a non-active level after the sense amplifier determines the data output and before the predetermined period has elapsed after the application of the active level voltage. And a circuit.

[0012] The read control circuit may include a circuit for switching the voltage of the word line from an active level to a non-active level when a predetermined period has elapsed since the address signal was changed.

The read control circuit decodes the address signal in response to a clock signal (S1) and outputs the decoded signal via the word line. Output control means for applying to the control gate of the memory cell and stopping application to the word line when the predetermined period has elapsed;
May be provided.

Further, in the above-mentioned nonvolatile memory device, the output control means becomes an active level in synchronization with a clock signal from the output of the decode circuit, and becomes an inactive level after a lapse of the predetermined period. Means (4, 5, 6,
AND).

Further, the output control means generates a control signal (S5) which becomes an active level in response to a rise of a clock signal and becomes inactive after a lapse of the predetermined period. ,
5, 6), an output of the decoding circuit is received at a first input terminal, a control signal is received at a second input terminal, an output terminal is connected to the word line, and a gate is responsive to the control signal. And a gate circuit for opening and closing the gate.

The control signal generating means receives a clock signal synchronized with the change of the address signal, detects an edge of the clock signal, and outputs a detection signal, and a detection signal from the edge detection circuit. A delay circuit that delays a signal, a circuit that outputs an active level signal in response to a detection signal from the edge detection circuit, and outputs an inactive level signal in response to an output signal of the delay circuit. , May be configured.

Further, a latch circuit (9) for latching an output of the sense amplifier in response to a level change of the control signal (S5) to an inactive level may be provided.

In the above nonvolatile memory device, the output control means may determine a delay circuit for delaying an output signal of the decode circuit, and a difference between an output signal of the decode circuit and an output signal of the delay circuit. And a logic circuit applied to the word line.

The logic circuit may include an inverter for inverting the level of an output signal from the delay circuit, and an AND circuit for calculating a logical product of the output signal of the inverter and the output signal of the decode circuit. Good.

Further, the output control means includes a NOR gate for generating a level-inverted signal of a logical sum of output signals of the plurality of logic circuits, and the NOR gate in response to a level change of an output signal of the NOR gate to an active level. A latch circuit (9) for latching the output of the sense amplifier may be provided.

According to these configurations, by setting the predetermined period, when the read voltage is applied to the word line connected to the memory cell, after the data output of the memory cell is determined, The application of the read voltage can be prevented. Therefore, it is possible to provide a nonvolatile memory device in which the occurrence of the read disturb phenomenon is suppressed.

Further, in the nonvolatile memory device according to the present invention, a first address signal that changes every first predetermined period and a second address signal that changes every second predetermined period different from the first predetermined period are provided. Means for receiving one of the address signals, selecting one of them, and outputting the selected signal to the read control circuit as the address signal.

Further, a first signal which changes every first predetermined period is provided.
And a second address signal longer than the first predetermined period.
Means for receiving a second address signal that changes every predetermined period of time, selecting one of the signals, and outputting the selected signal to the read control circuit as the address signal, wherein the read control circuit includes at least the second address signal. It operates during a period in which a signal is selected and output.

According to these configurations, when the second address signal is selected, the read voltage is reduced after the data output of the memory cell is determined, as compared with the case where the first address signal is selected. The period of application is further reduced. By reducing the period during which the memory cell is subjected to the voltage stress, a nonvolatile memory device in which the occurrence of the read disturb phenomenon is suppressed can be provided.

Also, the nonvolatile memory device of the present invention is arranged in a matrix, each having a floating gate, a control gate, and a current path. , A plurality of word lines (WLC) connected to the control gates of the memory cells in a corresponding row, and a source or a drain of the memory cells in a corresponding column. A plurality of connected bit lines (BL);
A sense amplifier (8) electrically connected to the bit line and determining the data output of the memory cell; and a latch circuit (9) connected to the sense amplifier and latching and outputting the output of the sense amplifier. , Receives the address signal,
A decode circuit (3) for decoding an address signal and outputting a decode signal; and applying an output signal of the decode circuit to the memory cell via the word line, and after the sense amplifier determines the data output, A read control circuit for causing the latch circuit to latch the output of the sense amplifier and setting the voltage of the word line to a non-active level.

According to this configuration, when the memory cell data is determined, the latch circuit latches the output of the sense amplifier, and in synchronization therewith, the application of the read voltage to the word line connected to the memory cell is stopped. This can prevent application of an extra read voltage after the memory cell data is determined. Therefore, it is possible to provide a nonvolatile memory device in which the occurrence of the read disturb phenomenon is suppressed.

[0027] A method of driving a nonvolatile memory according to a second aspect of the present invention includes a floating gate and a control gate, each of which has a floating gate and a control gate. A driving method, which decodes an address signal that changes every predetermined period,
An active-level voltage is applied to the control gate of the memory cell selected by the address signal, the stored data is read from the memory cell in which the active-level voltage is applied to the control gate, and the signal level of the read data is determined and output. After the output signal is latched, and after the output signal is latched, before the next address signal is decoded, and before the predetermined period elapses from the application of the active level voltage, the voltage is applied to the control gate of the memory cell. Switch the active level signal to the non-active level,
It is characterized by the following.

According to this method, when the read voltage is applied to the word line connected to the memory cell, it is possible to prevent the read voltage from being applied continuously after the data output of the memory cell is determined. Therefore, the occurrence of the read disturb phenomenon can be suppressed.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A non-volatile memory device according to an embodiment of the present invention and a driving method thereof will be described below with reference to the drawings. FIG. 1 is a circuit diagram of the nonvolatile memory device according to the first embodiment of the present invention. As shown in FIG.
This nonvolatile memory device includes memory cells 11, ₁ to 1
_{n and m} . The memory cells 11, ₁ to 1 _{n, m} are composed of stacked gate type MOS transistors, and n
They are arranged in a matrix of rows and m columns. Each of the memory cells 11, ₁ to 1n _{, and m} includes a floating gate, a control gate, a source, and a drain. The control gates of the memory cells 1 _{i, 1} to 1 _{i, m} (i is a natural number from 1 to n) in the i-th row are connected to the corresponding word line WLC _i . Also, the memory cells 11 in the j-th column _{, j} to 1
_n, a source or drain of _{j (a} natural number _j from 1 m) is electrically connected to a common bit line BL _j. Each memory cell 1 _{i, j} bit-stores storage data (voltage signal) corresponding to the charge charged in the floating gate when a read active level (H (high) level) voltage is applied to the control gate. and outputs it to the line BL _j.

The selector 2 receives the clock switching signal MODE
, The clock CLK is selected when the clock switching signal MODE indicates that the application using this nonvolatile memory is in the normal operation mode. When the standby mode is indicated for low power consumption, the low-frequency subclock signal S
Select UBCLK.

The decoding circuit 3 is a part (X address) of the address signal ADDR that changes in synchronization with the clock signal.
And selects _{one of} the word lines WL _{1 to} WL _n indicated by the address, applies an active level voltage, and applies an inactive level signal to the other word lines.

The Y selector 7 decodes another part (Y address) of the address signal ADDR, and outputs the bit line BL ₁
One of k sets (for example, eight or sixteen) of .about.BL _m is selected.

The sense amplifier 8 includes k sense amplifier elements, and selects the bit line BL selected by the Y selector 7.
, Amplify the current flowing through the selected bit line BL, determine the data output of the selected memory cell, and output it.

The latch circuit 9 has a storage capacity of k bits, takes in the k signals amplified by the sense amplifier 8 in synchronization with the rising edge of the clock supplied to the clock terminal, and outputs the data signals DATA ₁ to DATA ₁ . Output as DATA _k .

This nonvolatile memory device uses an address signal
Memory cell 1_{1, 1}~ 1 _{n, m}Connected to
Word line WLC₁~ WLC_nControl the signal applied to the
A read control circuit is provided. The read control circuit detects the edge
Path 4, delay circuit 5, SR latch circuit 6, AND circuit AND
₁~ AND_n, And an inverter INV.

The edge detection circuit 4 detects a rising edge of the input clock signal, generates a shot pulse signal synchronized with the rising edge, and supplies the shot pulse signal to the set terminal S of the SR latch circuit 6. The delay circuit 5 delays the shot pulse signal supplied from the edge detection circuit, and supplies the delayed signal to the reset terminal R of the SR latch circuit 6.

The output signal of the SR latch circuit 6 is supplied to the latch clock terminal of the latch circuit 9 via the inverter INV. The output signal of the SR latch circuit 6 is supplied to the first input terminal of 2-input AND circuit AND ₁ ～AND _n,
Controls the opening and closing of the AND circuits AND ₁ ~AND _n. On the other hand, the second input of 2-input AND circuit AND ₁ ~AND _n, word lines WL ₁ to WL _n are connected. Therefore, the output signal of the SR latch circuit 6 is active level and, when the signal on the word line WL _i is active level, A
ND circuit the AND _i outputs an active level signal to the word line WLC _i, the i-th row of the memory cell _{1 i,} 1 to 1
_A read voltage is applied to _{i and m} .

The delay time of the delay circuit 5 is determined as follows. When the read voltage is the memory cell 1 in the i-th row
_i, 1 _{to 1 i,} from the start is applied to _m, the sense amplifier 8 are time required to determine memory cell data, will vary slightly memory cell ₁ i, 1 _{to 1 i,} by _m. Therefore, a preliminary test for confirming the operation of the memory cell is performed, and the maximum time required for data determination is determined. Then, by adding a predetermined time to the maximum value, a period in which reading of all the memory cells 11, ₁ to 1 _{n, and m} is sufficiently possible is set.

[0039] However, in order to effectively reduce the access time to a particular address of the memory cell, all the memory cells 1 _{1, 1 to 1 n,} read enable period _of m, the specified word line WL _i The period is shorter than the period until the address signal ADDR changes. And that period,
The delay time is set in the delay circuit 5 in advance. By this setting, after the sense amplifier 8 is established a data output, the read control circuit, the voltage of the word line WLC _i the address signal ADDR specifies the nonactive level.

Next, the operation of the nonvolatile memory device will be described with reference to signals S1 to S6 supplied to the components of the circuit shown in FIG. FIG. 2 shows a timing chart of the signals S1 to S6.

First, the operation when the clock signal CLK is used in the circuit shown in FIG. 1 will be described. The clock signal S1 is input to the decode circuit 3 for the address signal ADDR and the edge detection circuit 4. The edge detection circuit 4 detects a rising edge of the clock signal S1, and generates and outputs a shot pulse detection signal S3 synchronized with the rising of the clock signal S1. Delay circuit 5
Delays the detection signal S3 to generate a delayed signal S4.

The SR latch circuit 6 is set so as to output a high-level (H) signal in synchronization with the rise of the detection signal S3 input to the set signal terminal S. The SR latch circuit 6 is reset so as to output a low-level (L) signal in synchronization with the rise of the delay signal S4 input to the reset signal terminal R. As a result of the repetition of these two operations, the SR latch circuit 6
During the period set in the delay circuit 5, a control signal S5 which becomes high level (H) is generated. The latch circuit 9 outputs the control signal S5
However, a signal whose level has been inverted through the inverter INV is used as a latch signal. This latch signal is at a low level (L) during the period set in the delay circuit 5. AND circuit AND _{1 to} A
ND _n by the control signal S5, controls the opening and closing of the gate.

On the other hand, for example, the decoding circuit 3 where the address signal ADDR is input specifying the word line WL ₁ is
Supplying a signal S2 to the word line WL _1. Word line WL ₁
Signal S2 is at H level only for one clock period according to address signal ADDR. AND circuit AND _1, when the control signal S5 is at the H level, opens the gate, the signal S2 of the word line WL _1, and supplied to the word line WLC _1, when the control signal S5 has elapsed period is at H level, Close the gate. That is, the output signal S6 of the AND circuit AND ₁ is switched from the active level to the inactive level when the lapse of time set in the delay circuit 5. Since the memory cells 11, ₁ to _{11, and m} are supplied with the output signal S 6 of the AND circuit AND ₁ via the word line WLC ₁ ,
When the period set in the delay circuit 5 has elapsed, the application of the voltage is stopped.

When a voltage is applied to the memory cells 11, 1, ₁ to _{11, and m} , the Y selector 7 decodes the address signal ADDR and selects the bit line BL specified by the address signal ADDR. The sense amplifier 8 amplifies the current flowing through the bit line BL and determines it as memory cell data. Then, the latch circuit 9 holds the memory cell data during the L level period of the latch signal, and outputs the data signal DATA.
It is output as _{1 to} DATA _k .

The latch signal of the latch circuit 9 is a signal obtained by inverting the level of the output signal S5 of the SR latch circuit 6 by the inverter INV. Therefore, the period of active level signal is applied to the word line WLC _1, memory cell data is held.

The nonvolatile memory device according to the first embodiment,
FIG. 3 shows a timing chart at the time of a read operation for comparison with the conventional example shown in FIG. In the conventional example, the period in which the signal S0 applied to the memory cell selected by the input address signal ADDR is at the active level is one clock cycle (T1). Similarly, in the nonvolatile memory device of the first embodiment, the period in which the signal S6 is at the active level corresponds to the period (T
2). Therefore, in the configuration of the present invention, the period during which the read voltage is applied to the memory cell is shortened.

Next, in the nonvolatile memory device of the first embodiment, the sub-clock signal SUB in the low frequency mode
The case where CLK is used will be described. In this case, the circuit shown in FIG. 1 performs the same operation as when the clock signal CLK is used. However, the cycle of the address signal ADDR is longer than when the clock signal CLK is used. However,
After the read voltage is applied to the memory cell, the period required for the sense amplifier 8 to determine the memory cell data does not change. Therefore, while the read voltage of the word line BL specified by the address signal ADDR is active,
The period set in the delay circuit 5 remains as it is.

As in FIG. 3, sub clock signal SUBC
FIG. 4 shows a comparison between the nonvolatile memory device of the present invention and the conventional example when LK is used. As shown in the figure, in the conventional example, the period during which the signal S0 is active is one clock cycle (T1 '). On the other hand, the period in which the signal S6 is active remains the period (T2) set in the delay circuit. Therefore, for example, if the warranty period of a product is limited due to the read disturb phenomenon at the time of using the low frequency mode, when the product is configured according to the present invention, the warranty period is extended to (T1 '/ T2) times. It is possible.

FIG. 5 is a circuit diagram of a nonvolatile memory device according to a second embodiment of the present invention. In the present embodiment, the memory cells ₁ 1, 1 _{to 1 n, m} to the connected word in response to the address signal - read control circuit for controlling a signal supplied to the word line _WLC 1 _{~WLC n} is, the word line control Circuit 10 and NOR
It is composed of a circuit NOR.

FIG. 6 is a configuration diagram of the word line control circuit 10. The word line WL is branched, and one of the word lines WL is an AND circuit AN.
D, and the other is the delay circuit 5 and the inverter INV
Are input to the same AND circuit AND. A signal obtained by decoding the address signal ADDR is applied to the word line WL, and the word line control circuit 10 receives the signal.
Generates a signal that is at a high level (H) for a period set in the delay circuit 5 by the configuration of FIG.

As a delay time of the delay circuit 5, a predetermined period is added to a maximum value of a period required for determining each memory cell data, and a period shorter than a period of an address signal is set in advance. By this setting, after the sense amplifier 8 is established a data output, the read control circuit, the read voltage of the word line WLC ₁ ~WLC _n address signal ADDR specifies nonactive.

The operation of the circuit shown in FIG. 5 will be described. Decoding circuit 3 decodes an address signal ADDR, a particular word line, for example, selects the WL _1. Word line WL
₁ is connected to the word line control circuit 10, and the word line control circuit 10 outputs a signal S7 which becomes high level (H) only for a period set in the delay circuit 5 therein. Signal S7 is supplied to the word line WLC _1, the word line WLC
₁ is active only during a period set in the delay circuit 5, during which a read voltage is applied to the memory cells 11, 1, ₁ to _{11, m} .

The signal S7 is also supplied to a low-level latch circuit 9 via a NOR circuit NOR. Signal S7
Is at the active level, the NOR circuit NOR outputs a low level (L) signal. Therefore, the output signal of the NOR circuit NOR becomes the latch signal of the low-level latch circuit 9, and
Holds memory cell data.

[0054]

As described above, according to the present invention,
After the data output of the memory cell is determined, it is possible to prevent the read voltage from being continuously applied. The application period of the read voltage to the memory cell can be shortened as compared with the related art, and access to the memory cell is reduced by the shortened period. Therefore, it is possible to provide a non-volatile memory device in which the occurrence of a read disturb phenomenon that can occur during reading is suppressed, and reading defects are reduced.

In particular, the rate at which the period during which the read voltage is applied is reduced is remarkable when the low frequency mode is used. For example, an application program that waits at low power in a microcomputer having a built-in flash memory according to the configuration of the present invention is less likely to cause a read disturb phenomenon, and can reduce data retention failure of the flash memory.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a nonvolatile memory device according to a first embodiment of the present invention.

FIG. 2 is a timing chart of each signal in a circuit of the nonvolatile memory device according to the first embodiment of the present invention.

FIG. 3 is a timing chart for comparing the nonvolatile memory device according to the first embodiment of the present invention with a conventional example.
(When using a clock signal)

FIG. 4 is a timing chart for comparing the nonvolatile memory device according to the first embodiment of the present invention with a conventional example.
(When using sub clock signal)

FIG. 5 is a circuit diagram of a nonvolatile memory device according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram of a word line control circuit included in a nonvolatile memory device according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram of an example of a conventional nonvolatile memory device.

FIG. 8 is a timing chart of each signal in a circuit as an example of a conventional nonvolatile memory device. (When using a clock signal)

FIG. 9 is a timing chart of each signal in a circuit of an example of a conventional nonvolatile memory device. (When using sub clock signal)

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory cell 2 Selector 3 Decoding circuit 4 Edge detection circuit 5 Delay circuit 6 SR latch circuit 7 Y selector 8 Sense amplifier 9 Latch circuit 10 Word line control circuit

Claims (14)

[Claims] 1. A memory arranged in a matrix, each having a floating gate, a control gate, and a current path, and outputting data according to a charge charged in the floating gate and a voltage applied to the control gate. Cell (1), a plurality of word lines (WLC) connected to the control gates of the memory cells in a corresponding row, and a plurality of bit lines (BL) connected to the sources or drains of the memory cells in a corresponding column. ), A sense amplifier (8) that is electrically connected to the bit line and determines the data output of the memory cell; receives an address signal that changes every predetermined period, and activates the word line specified by the address signal. Level voltage is applied, and after the sense amplifier determines the data output, and after applying the active level voltage, the predetermined period A read control circuit for setting the voltage of the word line to a non-active level before a lapse of time. 2. The read control circuit according to claim 1, further comprising a circuit for switching the voltage of the word line from an active level to a non-active level when a predetermined period has elapsed since the address signal was changed. The nonvolatile memory device according to claim 1. 3. A read control circuit comprising: a decode circuit (3) for decoding and outputting the address signal in response to a clock signal (S1); and an output signal of the decode circuit via the word line. And output control means for applying the voltage to the control gate of the memory cell and stopping the application to the word line when the predetermined period has elapsed.
3. The nonvolatile memory device according to claim 1. 4. The output control means generates, from the output of the decode circuit, a signal which becomes an active level in synchronization with a clock signal and becomes an inactive level after a lapse of the predetermined period, and outputs the signal to the word line. 4. The non-volatile memory device according to claim 3, further comprising a means (4, 5, 6, AND) for applying. 5. The control signal generation means (4) for generating a control signal (S5) which becomes an active level in response to a rise of a clock signal and becomes inactive after a lapse of the predetermined period. A first input terminal receiving the output of the decoding circuit, a second input terminal receiving the control signal, an output terminal connected to the word line, and responding to the control signal. The nonvolatile memory device according to claim 3, further comprising: a gate circuit that opens and closes a gate. 6. An edge detection circuit for receiving a clock signal synchronized with a change in the address signal, detecting an edge of the clock signal, and outputting a detection signal; And a delay circuit for delaying the detection signal of (a), outputting an active-level signal in response to the detection signal from the edge detection circuit, and outputting an inactive-level signal in response to the output signal of the delay circuit. The nonvolatile memory device according to claim 5, further comprising: a circuit. 7. The output control means includes: a delay circuit for delaying an output signal of the decode circuit; a logic circuit for calculating a difference between an output signal of the decode circuit and an output signal of the delay circuit, and applying the difference to the word line. Circuit and
The nonvolatile memory device according to claim 3, further comprising: 8. The logic circuit comprises: an inverter for inverting the level of an output signal from the delay circuit; and an AND circuit for obtaining a logical product of an output signal of the inverter and an output signal of the decode circuit. The nonvolatile memory device according to claim 7, wherein: 9. The semiconductor device according to claim 5, further comprising a latch circuit (9) for latching an output of said sense amplifier in response to a level change of said control signal (S5) to an inactive level. 7. The nonvolatile memory device according to item 6. 10. A NOR gate for generating a level inversion signal of a logical sum of output signals of the plurality of logic circuits, wherein the output control means responds to a level change of an output signal of the NOR gate to an active level. The nonvolatile memory device according to claim 7, further comprising a latch circuit that latches an output of the sense amplifier. 11. A first address signal that changes every first predetermined period and a second address signal that changes every second predetermined period different from the first predetermined period, and one of them is selected. The nonvolatile memory device according to claim 1, further comprising: a unit that outputs the address signal to the read control circuit. 12. Receiving a first address signal changing every first predetermined period and a second address signal changing every second predetermined period longer than the first predetermined period, and selecting one of them. Means for outputting to the read control circuit as the address signal, wherein the read control circuit operates at least during a period in which the second address signal is selected and output. The nonvolatile memory device according to claim 11, wherein 13. A memory arranged in a matrix, each having a floating gate, a control gate, and a current path, and outputting data in accordance with a charge charged in the floating gate and a voltage applied to the control gate. Cell (1), a plurality of word lines (WLC) connected to the control gates of the memory cells in a corresponding row, and a plurality of bit lines (BL) connected to the sources or drains of the memory cells in a corresponding column. ), A sense amplifier (8) electrically connected to the bit line to determine the data output of the memory cell, and a latch circuit connected to the sense amplifier to latch and output the output of the sense amplifier ( 9) a decoding circuit (3) for receiving an address signal, decoding the address signal, and outputting a decoded signal; A voltage is applied to the memory cell via a word line, and after the sense amplifier determines the data output, the latch circuit latches the output of the sense amplifier and sets the voltage of the word line to a non-active level. A non-volatile memory device, comprising: a control circuit. 14. A method of driving a memory cell having a floating gate and a control gate, wherein a read disturb phenomenon occurs by applying a voltage to the control gate, wherein an address signal which changes every predetermined period is decoded. To the control gate of the memory cell selected by the address signal,
Applying the active level voltage, reading the stored data from the memory cell to which the active level voltage is applied to the control gate, determining and outputting the signal level of the read data, latching the output signal, and latching the output signal After that, before decoding the next address signal, and before the predetermined period elapses from the application of the active level voltage, the active level signal applied to the control gate of the memory cell is switched to the non-active level. A method for driving a nonvolatile memory.