JP2001296507A - Electrode substrate for display device and test method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce costs necessary for inspecting a pixel part of a p- SiTFT-LCD and driver circuits. SOLUTION: A test circuit 11 is formed, comprising a test pattern generation part 6 which is connected with at least either the pixel part 3 or the driver circuit part 4 formed on an LCD substrate 1 and generates a test pattern for inspecting an electric response of the pixel part 3 or the driver circuit part 4, an expected value data output part 9 for outputting an expected value data expected as a normal response of the pixel part 3 or the driver circuit part 4, and a data comparison part for comparing the output data from the pixel part 3 or the driver circuit part 4 with the expected value data outputted from the expected data value output part 9 and outputting the data concerning the present or absence of electric failure of the pixel part 3 or the driver circuit part 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an electrode substrate for a display device used in an active matrix type liquid crystal display device and a test method therefor.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device in which a TFT (thin film transistor) is arranged as a switching element for each pixel constituting a display screen has no crosstalk between adjacent pixels and is suitable for high definition. From
Attention has been paid to realizing higher image quality, larger size, and color imaging of display screens. In recent years, development of a p-Si TFT-LCD (liquid crystal display device) in which a driver circuit is built in using a p-Si (polysilicon) TFT on a glass substrate has been advanced.

In such an LCD, it is necessary to test a driver circuit itself and a pixel portion through the driver circuit by inputting a test pattern from an input / output terminal formed on a glass substrate. The logic signal, etc., which becomes the test pattern described above, has been manually created by using a software tool for creating the test pattern.

[0004]

Incidentally, the above test pattern is not only a very complicated pattern depending on the contents of the inspection, but also a plurality of types must be prepared. Sometimes it took a long time. Further, since the created test pattern is input from the input / output terminal, a tester requires a pattern generator, a pattern memory, and the like.However, when performing a complicated inspection, a large-scale tester must be prepared. Therefore, there is a problem that the cost of the tester increases as a result.

In the near future, if a higher-definition product is demanded from the market, there is a possibility that the number of input signals may be diversified, and it may be necessary to perform testing with various types of patterns. Is expected to become even larger.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an electrode substrate for a display device and a test method for the same, which can reduce costs required for inspection of a pixel portion and a driver circuit of a p-Si TFT-LCD.

[0007]

In order to achieve the above-mentioned object, according to the present invention, a plurality of first wirings and a plurality of second wirings, which intersect each other, are provided on a main surface. On / off control is performed by a pixel signal arranged at an intersection and a gate signal supplied to the first wiring, and when the second wiring is turned on, conduction is provided between the second wiring and the pixel electrode. A pixel portion including a plurality of switch elements for writing a supplied data signal to the pixel electrode, and a first driver circuit for supplying a gate signal to the switch element;
And a driver circuit portion including a second driver circuit for supplying a data signal to the second wiring, the display device electrode substrate being formed on the electrode substrate for a display device, wherein A test pattern generator for generating a test pattern for inspecting an electrical response of the pixel unit or the driver circuit unit, and expected value data expected as a normal response of the pixel unit or the driver circuit unit An expected value data output unit, the output data from the pixel unit or the driver circuit unit, and the expected value data output from the expected value data output unit are compared, and the electric power of the pixel unit or the driver circuit unit is compared. A test circuit comprising a data comparison section for outputting data on the presence or absence of a target failure is formed.

In a preferred embodiment, a test pattern generating section, an expected value data output section, and a data comparing section constituting the test circuit are formed simultaneously with the same process as forming the pixel section and the driver circuit section. I do.

In a preferred embodiment, the test pattern generator, the expected value data output unit, and the data comparison unit constituting the test circuit are separated from the substrate after the inspection is completed (or during the manufacturing).

According to a fourth aspect of the present invention, there is provided an electrode substrate for a display device according to the first aspect, wherein the test circuit is used to generate a test pattern and analyze an input and output result. By performing the test, the presence or absence of an electrical defect in the pixel portion or the driver circuit portion is inspected.

In the above-mentioned invention, it is possible to judge the presence or absence of an electrical failure in a circuit or wiring simply by supplying the minimum system input required for inspection from the tester to the internal circuit for test, so that a complicated test is performed. Even if the inspection requires a pattern, there is no need to prepare a plurality of such patterns, and the waiting time until the pattern is completed can be eliminated. In addition, since a pattern generator or pattern memory for inputting the created test pattern is not required, even when performing a complicated inspection, there is no need to prepare a large-scale tester, and the cost of the tester can be reduced. Can be.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an electrode substrate for a display device and a test method therefor according to the present invention will be described with reference to p-SiTFT-L.
An embodiment when applied to a CD substrate (hereinafter, LCD substrate) will be described.

FIG. 1 is a schematic block diagram showing a circuit configuration of an LCD substrate according to this embodiment. Usually LCD
Although a plurality of substrates are formed on a large glass substrate, an example in which one LCD substrate 1 is formed on a glass substrate as shown in FIG.

The circuits formed on the LCD substrate 1 can be broadly divided into a device section 2 and a test circuit 11.

The device section 2 inputs a pixel section 3, a driver circuit section 4 for driving the pixel section 3, a power supply and a logic signal necessary for the operation of the driver circuit section 4, and the like. And an input / output terminal 5 for inputting and outputting data to and from the test circuit 11.

The pixel section 3 is turned on / off by a plurality of scanning lines and a plurality of signal lines crossing each other, a pixel electrode disposed at each intersection of these two lines, and a gate signal supplied to the scanning lines. And a switch element (none of which is shown) composed of a plurality of TFTs that conducts between the signal line and the pixel electrode when turned on and writes a data signal supplied to the signal line to the pixel electrode. .

The driver circuit section 4 includes a scanning line driver circuit for supplying a gate signal for controlling on / off of the switch element and a signal line driver circuit for supplying a data signal to the signal line (neither is shown). It is composed of

Around the device section 2, a pixel section 3 is provided.
A test pattern generator 6 for generating a test pattern for inspecting an electrical response of the driver circuit unit 4;
The data output from the test circuit input / output terminal 7 and the device unit 2 are converted into a format that can be compared by the data comparison unit 10.
A data output processing unit 8 to be processed; an expected value data output unit 9 that outputs expected value data expected as a normal response of the pixel unit 3 or the driver circuit unit 4; an output from the pixel unit 3 or the driver circuit unit 4 Data and expected value data output unit 9
And a data comparison unit 10 that compares the expected value data outputted from the data comparison unit 10 and outputs data (for example, a High / Low level signal) regarding the presence or absence of an electrical failure in the pixel unit 3 or the driver circuit unit 4. ing.

The test pattern generator 6, the data output processor 8, the expected value data output unit 9, and the data comparator 10 are used for testing the pixel unit 3 and the driver circuit unit 4 for electrical defects. The circuit 11 is configured.

A part of the input / output terminal 5 of the device unit 2 is connected to a test circuit input / output terminal 7 via a test pattern generation unit 6, and a power supply and a ground (GND) supplied from a tester not shown. And the like are supplied from the test circuit input / output terminal 7 to the device unit 2 and the test pattern generation unit 6. Some of the input / output terminals 5
The data output processing unit 8 is also connected to the device unit 2
Is output to the data output processing unit 8 via the input / output terminal 5 and is subjected to predetermined conversion and processing by the data output processing unit 8 before being output to the data comparison unit 10. Outputs from the data output processing unit 8 and the expected value data output unit 9 are given to the data comparison unit 10, and the data output from the data comparison unit 10 is taken out from the test circuit input / output terminal 7 to the outside.

The test pattern generating section 6, data output processing section 8, expected value data output section 9, and data comparing section 10
Can be formed in the same process as forming the pixel portion 3 and the driver circuit portion 4 and simultaneously. Therefore, the function of the LCD substrate can be improved using the same process as in the related art, and a tester (not shown) can be simplified. In addition, since it is not necessary to increase the number of new processes, productivity does not decrease.

Further, the test circuit 11 and the test circuit input / output terminal 7 do not affect the operation of the pixel section 3 and the driver circuit section 4 even if they are left on the substrate. Since the size of the outer shape of the product becomes large if is left, the outer shape of the product can be reduced by cutting off after the inspection is completed (or during the manufacturing).

Next, the operation of the test circuit 11 configured as described above will be described together with a specific circuit configuration.

First, a circuit configuration for testing the driver circuit section 4 and a test method thereof will be described.

FIG. 2 is a partial circuit configuration diagram of the driver circuit section 4 and the test circuit 11. Here, the inverter circuits 21, 24, 27,.
Will be described as a column where the inspection is sequentially performed to determine whether or not a leak failure has occurred.

In the pattern generating section 6, the data output processing section 8, the expected value data output section 9, and the data comparing section 10, the area enclosed by the broken line indicates a part of a circuit built in each section. The driver circuit unit 4 to be inspected is
Also shows an inverter circuit which is a part of the circuit.

In the inverter circuits 21, 24, and 27, reference numerals 22, 25, and 28 indicate input-side switches, and reference numerals 23, 26, and 29 indicate output-side switches. VDD indicates a power supply side potential, and VSS indicates a ground side potential.

First, a system input such as power supply and ground (GND) is supplied from a tester (not shown) to the driver circuit unit 4 and the test pattern generation unit 6 through the test circuit input / output terminal 7, respectively. Then, a D-type flip-flop (hereinafter, DFF) 31 in the test pattern generation circuit 6
To 38 are sequentially operated to turn on the input side switch 22 of the inverter circuit 21 in the driver circuit unit 4, and to write a High-level signal to the inverter circuit 21.

Here, if the electrical operation of the inverter circuit 21 is normal, a Low level signal is output to the output side. This output is output to the internal circuit 3 of the data output processing unit 8 via the output side switch 23 of the inverter circuit 21.
9, and the level is inverted to a High level signal. This signal is provided to the internal circuit 39 of the data comparison unit 10. On the other hand, from the internal circuit 40 of the expected value data output unit 9, a High-level signal that is an expected value (design value) is given to the internal circuit 41 of the data comparison unit 10. The internal circuit 41 of the data comparison unit 10 is configured by an AND circuit, and is high only when both inputs are the same, that is, when the output from the data output processing unit 8 and the output from the expected value data output unit 9 match. A level signal is output. In this case, both inputs are H
Since the signal is at the high level, the output from the data comparison unit 10 is also a signal at the high level, and it can be determined that the electrical operation of the inverter circuit 21 is normal. If the electrical operation of the inverter circuit 21 is not normal, the output side of the inverter circuit 21 is High.
The level signal is output. As a result, the output from the data comparison unit 10 becomes a Low level signal,
It can be determined that the electrical operation of the inverter circuit 21 is not normal.

Similarly, D in the test pattern generation circuit 6
As the FFs 31 to 38 sequentially operate, the remaining inverter circuits 24 and 27 of the driver circuit 4 are also inspected in order. At this time, if the electrical operations of all the inverter circuits 21, 24, 27 included in the driver circuit 4 are normal, the data comparison unit 10 always outputs H
A high-level signal is output. But,
If at least one of the inverter circuits 21, 24, and 27 has an abnormal electrical operation, the data comparison unit 10 outputs a low-level signal. Therefore, some of the signals output from the data comparison unit 10 are Low.
When the level signal is output, the electrical operation of one of the inverter circuits is not normal, and it can be easily determined that there is a problem. By using such a test circuit, it is possible to determine the presence / absence of an electrical failure in the circuit only by supplying a minimum system input required for inspection from a tester (not shown).

Next, a circuit configuration for testing the pixel portion 3 and a test method thereof will be described.

FIG. 3 is a partial circuit configuration diagram of the pixel section 3 and the test circuit 11. Here, a case will be described as an example in which the conduction failure of the switch elements S1, S2,... Constituting the pixel unit 3 and the storage capacitors Cs1, Cs2,.

Also in this example, in the pattern generation section 6, the data output processing section 8, the expected value data output section 9 and the data comparison section 10, the area indicated by the broken line indicates a part of the built-in circuit. The circuit configuration of each of the above units is shown in FIG.
However, here, for convenience, the same reference numerals are used.

Here, the configuration of the pixel portion 3 to be inspected will be briefly described. Since the configuration of each pixel constituting the pixel unit 3 is substantially the same, only a part of the configuration will be described.

In the pixel section 3, the scanning lines G1, G2,.
Are arranged so that the signal lines D1, D2,... Cross each other, and switch elements S1, S2,... Is arranged. The gate electrodes of the switch elements S are commonly connected to the scanning lines G1, G2,... For each row, and the source electrodes are connected to the signal lines D1, D2,. The drain electrodes are pixel electrodes P1, P2.
.. and the pixel electrodes P1, P2.
..Auxiliary capacitors Cs1, Cs electrically arranged in parallel with
2 are also connected. These auxiliary capacitors Cs1, C
are commonly connected to the auxiliary capacitance line 44 for each column. FIG. 3 shows a circuit configuration on an LCD substrate before being configured as an LCD panel, and includes a counter electrode disposed to face pixel electrodes P1, P2,... And a liquid crystal sandwiched between these electrodes. Layers and the like are not shown.

The scanning line driver circuit 42 is composed of a circuit including a shift register and a buffer (not shown), and one of the scanning lines G1, G2,..., Based on a control signal (clock / start signal) supplied from the outside. A gate signal is output every horizontal scanning period.

The signal line driver circuit 43 includes a shift register (S / R) 45, a data bus 46, ASWs (analog switches) 1, ASW2, and the like. The shift register 45 controls ON / OFF of ASW1, ASW2,... Based on a control signal (clock / start signal) supplied together with a data signal from the outside, and converts the data signal supplied to the data bus 46 into a predetermined signal. Are output to the signal lines D1, D2,. This data signal is supplied to a signal line D via switch elements S1, S2,...
, D2... Are written to the pixel electrodes P1, P2... And the auxiliary capacitors Cs1, Cs2.
.. Are not written).

In the actual signal line driver circuit, the circuit configuration of the data bus and the ASW differs depending on the driving method.
Here, for the sake of simplicity, the arrangement and connection of the data bus 46 and the ASW 46 are shown in a simplified manner.

In the pixel section 3 configured as described above, when inspecting the conduction failure of the switch elements S1, S2... And the leakage failure of the auxiliary capacitors Cs1, Cs2. ..Auxiliary capacitance C via
Write a test signal into s1, Cs2,..., read it again, and compare it with an expected value to determine pass / fail.

First, a system input such as power supply and ground (GND) is supplied from a tester (not shown) to the driver circuit section 4 and the test pattern generation section 6 through the test circuit input / output terminal 7, respectively. Then, the switch element 47 of the test pattern generation section 6 is turned on for a predetermined period by a control signal from the internal circuit 48, and the switch element 50 of the data output processing section 8 is turned off by a control signal from the internal circuit 51. As a result, a data signal for testing is output from the power supply 49 to the driver circuit unit 4 through the input / output terminal 5. This data signal is further supplied to the signal line D1 through the ASW1 controlled by the shift register 45. Here, the scanning line driver circuit 42 supplies the scanning line G1.
And outputs a gate signal to the switch element S for one line.
.. Are turned on only for a predetermined period (writing period). Then, during this time, the test data signal is written to the auxiliary capacitance Cs1 via the switch element S1.

Next, at the point in time when one frame period which is the same as the actual driving time has elapsed, a gate signal is outputted from the scanning line driver circuit 42 to the scanning line G1, and the switching elements S1, S2. It is turned on again. Then, the test data signal written to the auxiliary capacitance Cs1 is output from the switch element S1 to the signal line D1 again. Here, the switch element 48 of the test pattern generator 6 is turned off by the internal circuit 47 and the data output processor 8 is turned off.
Is turned on, the data signal is taken into the data output processing unit 8 through the ASW 1 controlled by the shift register 45. The read data signal is subjected to data conversion and processing by the internal circuit 52 of the data output processing unit 8 as needed, and then output to the data comparison unit 10.

On the other hand, the internal circuit 5 of the expected value data output unit 9
From 3, the data signal set as the expected value is given to the internal circuit 51 of the data comparison unit 8. The internal circuit 51 of the data comparing unit 8 compares the potential of the data signal read from the storage capacitor Cs1 with the potential of the expected data signal, and when the difference between the potentials of the two data signals is within an allowable range. Is determined to be normal, otherwise, it is determined to be abnormal. This determination result is output as a signal of a predetermined level. By performing the same test on the remaining switch elements of the pixel unit 3 in order, the conduction failure of all the switch elements S1, S2,... Included in the pixel unit 3 and leakage of the auxiliary capacitances Cs1, Cs2,. It is possible to inspect whether a defect has occurred.

Further, by extracting the potentials of the two data signals from the data comparing section 10, it is possible to individually determine the conduction failure of the switch element and the leakage failure of the auxiliary capacitance. For example, if the potential of the read data signal is zero, it can be determined that the conduction of the switch element is defective.If the potential of the read data signal is out of the allowable range, the conduction of the switch element is determined. Although it is normal, it can be determined that the auxiliary capacitor has a leak failure. By repairing defective parts based on this information,
Repair work can be made more efficient.

As is clear from the above description, according to the LCD substrate and the test method according to this embodiment, even if the test requires a complicated test pattern, it is necessary to prepare a plurality of such complicated patterns. And the waiting time until the pattern is completed can be eliminated. In addition, a pattern generator and a pattern memory for inputting the created test pattern from the input / output terminal 5 are not required.
Even when performing a complicated inspection, there is no need to prepare a large-scale tester, and the cost of the tester can be reduced.

In the conventional test method, a test pattern is input from an input / output terminal formed on a glass substrate. Specifically, a fine needle (probe) connected to a tester is connected to the device section 2. When the number is large, the cost of the probe is high, and the contact between the terminal and the probe requires very advanced technology, and the productivity is lowered. Was invited.
However, in the device section 2 of this embodiment, since a part of the signal conventionally given from the tester can be created by the test circuit 11, the number of the test input / output pins 7 can be reduced. Therefore, the cost of the probe can be reduced, and the contact between the terminal and the probe becomes easy, so that the productivity can be improved.

In the above-described embodiment, an example in which the electrical operation of the inverter circuit constituting the driver circuit section 4 is inspected, and a conduction failure of the switch element constituting the pixel section 3 and a leakage failure of the auxiliary capacitance are examined. Although an example has been described, in addition to the above, a test signal is also transmitted from the test pattern generation unit 6 to an ASW or a shift register configuring the driver circuit unit 4 or a scanning line or a signal line configuring the pixel unit 3. Inspection can be performed similarly by giving. Also in this case, it is possible to determine the presence or absence of an electrical failure in a circuit or wiring by supplying a minimum system input required for inspection from a tester (not shown).

[0047]

As described above, according to the electrode substrate for a display device and the test method thereof according to the present invention, the electric circuit and wiring can be electrically connected only by giving the minimum system input required for the inspection from the tester. Since it is possible to determine the presence or absence of defects, even if the test requires a complex test pattern, there is no need to prepare multiple types of such patterns,
The waiting time until the pattern is completed can be eliminated. In addition, since a pattern generator or pattern memory for inputting the created test pattern is not required, even when performing complicated inspections, there is no need to prepare a large-scale tester, and the cost of the tester can be reduced. it can.

Therefore, it is possible to reduce the cost required for inspection of the pixel portion and the driver circuit of the p-Si TFT-LCD.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing a circuit configuration of an LCD substrate according to an embodiment.

FIG. 2 is a partial circuit configuration diagram of a driver circuit unit and a test circuit.

FIG. 3 is a partial circuit configuration diagram of a pixel portion and a test circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... LCD board, 2 ... Device part, 3 ... Pixel part, 4 ... Driver circuit part, 5 ... Input / output terminal, 6 ... Test pattern generation part, 7 ... Test circuit input / output terminal, 8 ... Data output processing part, 9: expected value data output unit, 10: data comparison unit,
11 Test circuit

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 2G014 AA01 AB21 AC18 2H088 FA12 FA13 FA19 FA30 HA08 MA20 5C094 AA41 AA43 AA44 AA45 AA60 BA03 BA43 CA19 EA04 EA05 EB02 HA08 5G435 AA19 BB12 KK05 KK10 KK08 LL08

Claims (4)

[Claims] 1. A plurality of first wirings and a plurality of second wirings intersecting each other on a main surface, a pixel electrode disposed at each intersection of these two wirings, and a first wiring supplied to the first wirings. A pixel including a plurality of switch elements, which is controlled to be turned on / off by a gate signal that is turned on, conducts between the second wiring and the pixel electrode when on, and writes a data signal supplied to the second wiring to the pixel electrode. Device electrode substrate, comprising: a first driver circuit for supplying a gate signal to the switch element; and a second driver circuit for supplying a data signal to the second wiring. A test pattern for connecting to at least one of the pixel unit or the driver circuit unit and generating a test pattern for inspecting an electrical response of the pixel unit or the driver circuit unit; An expected value data output unit that outputs expected value data expected as a normal response of the pixel unit or the driver circuit unit; output data from the pixel unit or the driver circuit unit; A data comparison unit that compares the expected value data output from the value data output unit and outputs data regarding the presence or absence of an electrical failure in the pixel unit or the driver circuit unit. An electrode substrate for a display device, comprising: 2. The method according to claim 1, wherein the test pattern generation section, the expected value data output section, and the data comparison section are formed in the same process as forming the pixel section and the driver circuit section, and simultaneously. 2. The electrode substrate for a display device according to 1. 3. The display device electrode according to claim 1, wherein the test pattern generation unit, the expected value data output unit, and the data comparison unit are separated from the substrate after inspection is completed or during manufacturing. substrate. 4. A method of generating a test pattern and analyzing input and output results using the test circuit,
The method according to claim 1, further comprising inspecting whether the pixel portion or the driver circuit portion has an electrical defect.