JP2001290463A - Driving device for plasma display panel and plasma display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a driving device for plasma display panel capable of enhancing a contrast at the time of performing display in the so-called wide mode. SOLUTION: A luminance level detecting circuit 20 discriminates whether or not a signal component corresponding to a black band part (upper and lower non-display parts in the wide mode) in the luminance signal SL equivalent to one display picture is a signal component indicating a black display. When a display device performs display in the wide mode, a sequence control circuit 18 applies an instruction for impressing erasing pulses to a drive sequence generating circuit 16 even in an erasure period when priming pulses are impressed on the electrode group X of the black band part in the case where the device is not in the wide mode based on this discrimination result. Then the circuit 16 generates erasing pulses based on the instruction to output them to circuits corresponding to the black band part in a sustaining driver 23. Thus, the luminance of the black part in the case of performing the wide mode is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device for a PDP for driving a plasma display panel (hereinafter also referred to as "PDP") and a plasma display device, and to a technique for increasing the contrast of the PDP.

[0002]

2. Description of the Related Art (Structure of Conventional PDP) FIG. 8 shows a general surface discharge type AC PDP 21 (hereinafter simply referred to as "PDP2").
FIG. 1 is a schematic perspective view for explaining the structure of FIG. The PDP 21 is disclosed in, for example, Japanese Patent Application Laid-Open No. 10-3281.

As shown in FIG. 8, a pair of strip-shaped row electrodes (or sustain electrodes) X and row electrodes (or scan electrodes) Y are formed in parallel on a front glass substrate 102 forming a display surface. I have. Although one row electrode X and one row electrode Y are shown in FIG. 8 for the reason of the range of illustration, an electrode pair composed of both row electrodes X and Y (hereinafter “(row)”) is shown in the entire PDP 21. A plurality of pairs of electrodes are also formed. Each electrode pair X, Y corresponds to each display line. A dielectric layer 106 is formed on the front glass substrate 102 so as to cover both electrodes X and Y.
A protective layer 107 is formed thereon.

On the other hand, the front glass substrate 1
02 on the rear glass substrate 103 facing
A plurality of (three of them are shown in FIG. 8) strip-shaped column electrodes (or address electrodes) A are formed in a direction intersecting with Y. On the rear glass substrate 103, partition walls (also called “(barrier) ribs”) 110 are formed between the column electrodes A in parallel with the electrodes A. A phosphor layer 109 is formed on the inner wall surface of the substantially U-shaped groove formed by the adjacent partition 110 and the rear glass substrate 103 so as to cover the column electrode A.

In the PDP 21, one row electrode X and one row electrode Y (that is, the above-mentioned pair of electrodes X and Y) and one column electrode A
A single discharge cell or light-emitting cell is defined by the intersection of the above. FIG. 8 shows three discharge cells. Each discharge cell is address-selected in a matrix by a combination of the electrode pair (specifically, the row electrode Y) and the column electrode A. Each row electrode Y and each column electrode A are insulated so that the lighting operation and the light-off operation in each discharge cell are controlled independently between each discharge cell.

(Configuration of Conventional Plasma Display Apparatus) FIG. 9 shows a conventional plasma display apparatus 201P.
FIG. 2 is a block diagram for explaining the above. The plasma display device 201P is roughly divided into a PDP 21 and a driving device 201DP of the PDP 21.
The DP 21 is driven as follows.

First, a video signal S is supplied to a driving device 201D.
It is input to the P video signal processing circuit 11 and the sync separation circuit 12. The video signal processing circuit 11 separates the video signal S into a color signal SC and a luminance signal SL, and outputs both signals to an analog-digital conversion circuit (hereinafter, also referred to as an “A / D conversion circuit”) 13. On the other hand, the sync separation circuit 1
Reference numeral 2 extracts, from the video signal S, a vertical synchronizing signal and a horizontal synchronizing signal that serve as references for the operation of the control circuit 15, and outputs both synchronizing signals to the control circuit 15.

The A / D conversion circuit 13 converts the analog video signal S into RGB based on the color signal SC and the luminance signal SL.
Digital conversion is performed for each color, and the converted RGB signals are written into the frame memory 14 as display data. The control circuit 15 controls writing to the frame memory 14 of the A / D conversion circuit 13 and reading of RGB signals from the frame memory 14. In addition, the control circuit 15 controls the drive sequence generation circuit 16P.

The drive sequence generation circuit 16P is a PDP
21 to generate a sequence for driving the scan driver 22, the sustain driver 23, and the address driver 24.
Output to Each of the drivers 22 to 24 generates a drive pulse with the input signal and the high voltage, and outputs the drive pulse to each of the electrodes X, Y, and A. The address driver 24 reads display data for generating an address pulse for a writing period described later from the frame memory 14.

(Conventional Driving Method) Next, the present invention is applied to, for example, the above-described plasma display device 201P.
A first conventional driving method of the PDP 21 will be described. FIG.
FIG. 1 shows a configuration diagram of one field when gradation display is performed. One field refers to a time for displaying one picture or image on the screen, and is referred to as NTSC (National T
elevision System Committee) 1 field =
It is about 16.7 msec (60 Hz). The vertical direction in FIG. 10 shows the arrangement of display lines, and the horizontal direction shows the flow of time.

One field includes a plurality of subfields SF.
It consists of. FIG. 10 shows an example in which one field includes first to eighth subfields SF1 to SF8. Further, each of the subfields SF1 to SF
8 includes an erase period ET, a write period (or address period) WT, and a sustain discharge period (or sustain period) ST arranged in time series.

FIG. 11 is a timing chart for explaining a driving method in one subfield SF. Such a timing chart is described in, for example,
No. 281. 11A shows a waveform of a voltage applied to the row electrode X or a sustain driver pulse train, FIG. 11B shows a waveform of a voltage applied to the row electrode Y or a scan driver pulse train, and FIG. This is a waveform of a voltage applied to the column electrode A or a write driver pulse train.

(Erase Period ET) In the erase period ET, PD
All the discharge cells of P21 are set to the same state (erase operation). Specifically, the priming pulse 31 is applied to all the row electrodes X. At this time, the voltage VP of the priming pulse 31
p is set to be equal to or higher than the discharge starting voltage between the pair of electrodes X and Y, and discharge is formed in all the discharge cells regardless of light emission / non-light emission in the immediately preceding subfield. Priming pulse 3
For example, 1 is set to a higher voltage and a wider pulse width than a sustain discharge pulse 33 described later. The application of the priming pulse 31 causes a potential difference (= VPp) between the electrodes X and Y, and charged particles such as electrons and ions generated by the discharge are attracted to the electrodes X and Y by the electric field due to the voltage. As a result, a large amount of wall charges are generated in the protective film 107.
(See FIG. 8).

When the priming pulse 31 falls,
An electric field due to wall charges remains between the electrodes X and Y. Since the accumulated wall charges are large, this electric field is large, and discharge is started again only by the electric field. However, at this time, since no voltage is applied to the electrodes X and Y, the charged particles generated by this discharge are neutralized and disappear without being attracted to the electrodes X and Y. Thereby, the wall charges are erased.

(Write Period WT) In the succeeding write period WT, the presence or absence of wall charges in each discharge cell is controlled (write operation). Specifically, a negative scanning pulse 36 (voltage VScp (<0)) is sequentially applied (scanned) to each row electrode Y, and a voltage applied to each column electrode A is synchronized with the scanning. Application / non-application is controlled based on display data. At this time, when the display data is for causing the discharge cells to emit light in the subsequent sustain discharge period ST, a positive address pulse 38 (voltage VAp) is applied to the column electrode A belonging to the discharge cell. Thus, the potential difference between the column electrode A and the row electrode Y (= VAp−VSc)
p) to generate a write discharge, thereby forming a wall charge in the discharge cell.

(Sustain discharge period ST) After the scanning of one entire screen is completed, the driving sequence shifts to the sustain discharge period ST. In the sustain discharge period ST, a sustain discharge is generated in the discharge cells in which the wall charges have been formed in the writing period WT. Specifically, a sustain discharge pulse (or a sustain pulse) 33 is alternately or alternately applied between the electrodes X and Y.
At this time, a sustain discharge occurs only in the discharge cells in which the wall charges have been formed during the writing period WT.

The light emission amount during the sustain discharge period (accordingly, the light emission amount in the subfield) can be controlled by the number of applied sustain discharge pulses 33. Utilizing this point,
In the PDP, gradation display is performed as follows.

That is, the number of sustain discharge pulses applied in each of the subfields SF1 to SF8 is different for each subfield,
A gradation display is performed by combining the light emission amounts in the respective subfields SF1 to SF8.

For example, if light emission / non-light emission in the first subfield SF1 is defined as the least significant bit (LSB), the number of sustain discharge pulses is 1 (= 2 ⁰ ), which is the minimum unit. Second subfield SF2 and third subfield SF3
When the light emission and non-light emission are represented by the second bit and the third bit, respectively, the number of sustain discharge pulses is 2 (= 2 ¹ ) and 4 (= 2 ² ), respectively. The fourth subfield SF4 to the seventh subfield SF7 are similarly set, the eighth subfield SF8 indicates the most significant bit (MSB), and the number of sustain discharge pulses is 128 (= 2 ⁷ ).

As described above, each of the subfields SF1 to SF
The number of each sustain discharge pulse in F8 is defined by a power of two.
As a result, there is no sustain discharge light emission. Brightness level
Sustain discharge light emission from 0 to all subfields SF1 to SF8
Brightness level 255 (2⁰+2¹+2^Two+
2^Three+2^Four+2^Five+2⁶+2⁷) Up to 256 (=
2 ⁸) A gradation display is possible.

(Priming Pulse) As described above, in the first conventional driving method, the priming pulse 31 is applied to all the row electrodes X in the erasing period ET regardless of light emission or non-light emission in the immediately preceding subfield. A discharge is generated in all the discharge cells. The priming pulse has a function of generating discharge and light emission in all the discharge cells and a function of priming (seeding). For details, see
As described in Japanese Patent Application Publication No. 0-3281, if a small amount of charged particles generated by the priming pulse remain,
The next writing discharge can be reliably formed by the charged particles.

Since the priming (seeding) effect lasts for a long time, it is not always necessary to apply a priming pulse to all subfields SF1 to SF8 in one field. Here, FIGS. 12 and 13 show timing charts for explaining the second conventional driving method. 12 and 13 show only the waveform of the voltage applied to the row electrode X, FIG. 12 shows subfields SF1 to SF4, and FIG. 13 shows subfields SF5 to SF8. . As shown in FIGS. 12 and 13, in the second conventional driving method, the priming pulse 31 is applied only in three subfields SF1, SF3, and SF5 in one field. In such a driving method, the other subfields SF2, SF4, SF6
In SF6, an erasing pulse 32 is applied instead of the priming pulse 31. The erasing pulse 32 is set to, for example, the same voltage as the sustain discharge pulse 33, and has a narrower pulse width than the sustain discharge pulse 33. Therefore, according to the erase pulse 32, the priming pulse 31
Unlike this, a discharge is formed only in the discharge cells that emit light in the immediately preceding sustain discharge period ST.

By the way, the priming pulse 31 generates a discharge in all the discharge cells irrespective of light emission or non-light emission in the immediately preceding sustain discharge period, so that light emission occurs in all the discharge cells. At this time, the subfields SF1, SF3, and SF5 to which the priming pulse 31 is applied and the subfields SF2, SF4, and SF6 to SF6 to which the priming pulse 31 is not applied as in the driving method of FIGS.
By providing 8, the number of priming pulses 31 in one field can be reduced. In other words, an increase in luminance (so-called background luminance) due to light emission caused by the priming pulse 31 can be suppressed. Therefore, according to the driving methods shown in FIGS. 12 and 13, compared with the case where the priming pulse 31 is applied in all the subfields SF1 to SF8, the background luminance can be suppressed and the contrast can be improved.

However, since the priming pulse has the above-described seeding effect, the priming pulse 31 cannot be eliminated at all. Therefore, at least one discharge by the priming pulse is required in one field.

As described above, in the conventional driving method, the priming pulse 31 is applied once or a plurality of times in one field, and therefore, when the luminance level is originally zero (hereinafter referred to as "black display"). ), There is a luminance corresponding to the light emitted by the priming pulse 31.

(Drive Sequence Generating Circuit) Next, how the applied pulses in the erasing period ET, the writing period WT, and the sustain discharge period ST are generated in the driving sequence generating circuit 16P will be described. The case where the drive sequence generation circuit 16P applies a pulse to the row electrode X according to the drive method shown in FIGS. 12 and 13 will be described. FIG. 14 shows a driving sequence generation circuit 163 for a sustain driver in a conventional driving sequence generation circuit 16P.
FIG. 2 shows a block diagram for explaining P.

As shown in FIG. 14, the conventional drive sequence generation circuit 163P includes pulse generation circuits 40, 43, and 44 for the erase period, the write period, and the sustain discharge period.
Is provided. The erase period pulse generation circuit 40 includes a priming pulse generation circuit 41 and an erase pulse generation circuit 42.

Each pulse generated by each of the pulse generation circuits 41 to 44 is finally input to the changeover switch 47P, and the erase period E is changed by the changeover switch 47P.
A predetermined pulse corresponding to each of T, write period WT, and sustain discharge period ST is output to sustain driver 23.
The changeover switch 47P is controlled by a timing control circuit 48P, and the timing control circuit 48P is controlled by the control circuit 15.

As described above, in the erase period ET shown in FIGS. 12 and 13, there are subfields to which the priming pulse 31 is applied and subfields to which the erase pulse 32 is applied. For this reason, the output terminals of both the pulse generation circuits 41 and 42 are connected to the changeover switch 45, and the output of one of the pulse generation circuits 41 and 42 according to the subfield is selected by the changeover switch 45. At this time, the changeover switch 45 is connected to the timing control circuit 4.
8P.

Since the driving method during the writing period WT is the same in any subfield, during the writing period WT, the output of the pulse generation circuit 43 is output as it is via the changeover switch 47P.

As described above, in the sustain discharge period ST, the number of sustain discharge pulses 33 differs for each subfield. For this reason, the sustain discharge period pulse generation circuit 44 uses the pulse generation circuit 44a (the number of pulses n) for the first subfield SF1.
= 2 ⁰ ) to a pulse generation circuit 44h (number of pulses n = 2 ⁷ ) for the eighth subfield SF8. The output terminal of each of the pulse generation circuits 44a to 44h is connected to a changeover switch 46, and an output corresponding to each of the subfields SF1 to SF8 is selected by the changeover switch 46 and output to the changeover switch 47P.

By such control, the drive sequence generation circuit 163P generates and outputs pulses in each of the subfields SF1 to SF8 in one field.

[0033]

Recently, with the spread of VTRs and optical discs, for example, movies and the like have been increasingly enjoyed at home through these media. At this time, in a movie or the like, there are many landscape images having an aspect ratio (hereinafter, also referred to as “aspect ratio”) of, for example, 16: 9. On the other hand, for example, the aspect ratio of a general screen of a color television is 4: 3. For this reason, when viewing the above-described landscape video on a color television, a state in which non-display portions (hereinafter, also referred to as “black band portions”) exist above and below the screen (hereinafter, also referred to as “wide mode (display)”). Is displayed with. According to the wide mode, the information in the horizontal direction of the video is not lost, and the aspect ratio is not changed.

However, when the wide mode display is performed on the PDP, there is a problem that the contrast is lower than that of a CRT (Cathode Ray Tube). This is C
This is because the black band in the wide mode is brighter in the PDP than in the RT.

The present invention has been made in view of the above, and it is a first object of the present invention to provide a plasma display panel driving device and a plasma display device capable of improving the contrast of a displayed image.

It is a second object of the present invention to provide a plasma display panel driving device and a plasma display device which can realize the first object with a simple and compact structure.

[0037]

According to a first aspect of the present invention, there is provided a driving apparatus for a plasma display panel according to the first aspect of the present invention.
A plurality of strip-shaped first electrodes, a plurality of strip-shaped second electrodes intersecting the plurality of first electrodes via a discharge space, and respective intersections of the respective first electrodes and the respective second electrodes; A plasma display panel driving device for driving a plasma display panel having a plurality of discharge cells defined by: a field for each of the erasing period and a predetermined discharge cell based on an input image signal The plasma display panel is driven after being divided into a plurality of sub-fields including a writing period for performing a writing operation and a sustaining discharge period for generating a sustain discharge in the predetermined discharge cell on which the writing operation has been performed. In the driving device for a plasma display panel, the discharge cell is formed regardless of the formation or non-formation of the sustain discharge in the preceding sustain discharge period. A first pulse generation unit that generates a first pulse capable of forming a discharge in the first discharge cell, and a second pulse generator that generates a second pulse capable of forming a discharge only in the discharge cell that has generated the sustain discharge in the preceding sustain discharge period. A pulse generator, and determining whether or not the sustain discharge is not formed in all the sustain discharge periods in the one field in all the discharge cells belonging to a predetermined electrode group of the plurality of first electrodes. A black display determination unit that performs the black display determination unit based on the input image signal, wherein the black display determination unit is configured to perform at least one of the discharge cells belonging to the electrode group in at least one of the sustain discharge periods in the one field. If it is determined that a sustain discharge is to be formed, the driving device for a plasma display panel may be configured to control the electrode during at least one of the erasing periods in the one field. While outputting the first pulse, the black display determination unit does not form the sustain discharge in all the sustain discharge periods in the one field in all the discharge cells belonging to the electrode group. When it is determined, the plasma display panel driving device outputs the second pulse to the electrode group in all the erasing periods in the one field.

(2) A driving apparatus for a plasma display panel according to the second aspect of the present invention is the driving apparatus for a plasma display panel according to the first aspect, wherein the input image signal includes a luminance signal, The black display determination unit
A luminance level of the discharge cells belonging to the electrode group is detected from the luminance signal, and the determination is performed based on the luminance level.

(3) A driving apparatus for a plasma display panel according to a third aspect of the present invention is the driving apparatus for a plasma display panel according to the first aspect, wherein the input image signal is transmitted in one field. A signal conversion unit that converts the discharge data into digital data indicating light emission / non-light emission of each of the discharge cells in each of the sustain discharge periods, wherein the black display determination unit determines a luminance of the discharge cells belonging to the electrode group from the digital data. The level is detected, and the determination is made based on the luminance level.

According to a fourth aspect of the present invention, there is provided the plasma display panel driving device according to the first aspect, wherein the black display determination unit is configured to output the input image signal. It is determined whether or not includes information on the aspect ratio of the display image, and if it is determined that the included information on the aspect ratio is information on a predetermined aspect ratio, all the discharge cells belonging to the electrode group And determining that the sustain discharge is not formed in all the sustain discharge periods in the one field.

(5) The driving device for a plasma display panel according to the fifth aspect of the present invention is the driving device for a plasma display panel according to any one of the first to fourth aspects, wherein the amplitude of the second pulse is adjusted. Is smaller than the first pulse.

(6) A driving device for a plasma display panel according to a sixth aspect of the present invention is the driving device for a plasma display panel according to any one of the first to fifth aspects, wherein the electrode group comprises: A plurality of the first electrodes include a predetermined number of the first electrodes from each end of the array.

(7) In the plasma display device according to the present invention, a plurality of strip-shaped first electrodes and a plurality of strip-shaped second electrodes intersecting the plurality of first electrodes via a discharge space. And each of the first electrodes and each of the second electrodes
A plasma display panel comprising a plurality of discharge cells defined by each intersection with an electrode, and the plasma display panel driving device according to any one of claims 1 to 6. I do.

[0044]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <Point of View> In the following description, a black band portion in a wide mode is not always a black display even when the mode is not a wide mode (hereinafter also referred to as "normal display"). However, for the sake of convenience, it will be referred to as a “black belt portion”.

As described above, in the conventional driving method or the conventional plasma display device 201P, the priming pulse 31 is applied at least once during one field (see FIGS. 11 to 13). Such driving is the same even in the wide mode display.

However, in the wide mode, the black band does not contribute to the actual image display, and the discharge cells in the black band do not generate the sustain discharge during the sustain discharge period. In view of such a point, it can be said that it is not necessary to apply the priming pulse 31 for obtaining the pilot fire effect to the row electrode X in the black band portion.

Therefore, in the plasma display device according to the present invention, the drive sequence for the discharge cells in the black band during the wide mode display is different from that for the discharge cells in the portion other than the black band (hereinafter referred to as "display portion"). As a result, discharge or light emission (accordingly, background luminance) in the discharge cells in the black belt portion is reduced, and the contrast is improved as compared with the related art.

More specifically, in the case of the wide mode, the erasing pulse 32 is applied in the erasing period ET to the discharge cells in the black band portion, while, for example, the same drive sequence as in the related art is applied to the display portion. I do. That is, in the case of the wide mode, the driving in the erasing period ET is performed independently for the display portion and the black band portion.

Embodiments 1 to 3 of the present invention based on the above viewpoint will be described below. Here, Embodiments 1 to
P of the plasma display devices 201 to 203 according to No. 3
A case where the above-described PDP 21 is applied as the DP will be described. At this time, the row electrode X corresponds to the first electrode, and the column electrode A
Corresponds to the second electrode. Further, the row electrodes X of the discharge cells in the black band portion are collectively referred to as “black band electrode group X”. At this time, the electrode group X in the black band portion includes a plurality of row electrodes X.
, A predetermined number (determined from the aspect ratio of the screen of the PDP and the aspect ratio of the display image) from each end of the array. Note that a PDP having another structure may be used instead of the PDP 21. That is, (a)
A plurality of strip-shaped first electrodes; (b) a plurality of strip-shaped second electrodes intersecting the plurality of first electrodes via a discharge space; and (c).
A PDP including a plurality of discharge cells each defined by each intersection of each first electrode and each second electrode can be applied to the plasma display devices 201 to 203.

A priming pulse (first pulse)
“Pulse” refers to a pulse capable of forming a discharge in a discharge cell regardless of formation / non-formation of a sustain discharge in the preceding sustain discharge period ST. On the other hand, the erase pulse (second pulse) refers to a pulse capable of forming a discharge only in a discharge cell in which a sustain discharge has been formed in the preceding sustain discharge period ST. For example, by setting the amplitude of the erase pulse or the absolute value of the amplitude voltage to be smaller than that of the priming pulse, it is possible to reliably form and separate the above-described discharges by each pulse.

It is to be noted that the same components as those described above are denoted by the same reference numerals, and description thereof will be omitted.

<First Embodiment> FIG. 1 is a block diagram illustrating a plasma display device 201 according to a first embodiment. The plasma display device 201 is roughly classified into a PDP 21 and a PDP driving device (hereinafter, simply referred to as a driving device) 201D.

As shown in FIG. 1, the driving device 201D
The video signal processing circuit 11, the synchronization separation circuit 12, and the A /
D conversion circuit 13, frame memory 14, control circuit 1
5, a drive sequence generation circuit 16, a sequence control circuit 18, a black band luminance level detection circuit (black display determination section) 20, a scan driver 22, and a sustain driver 23.
And an address driver 24. Hereinafter, the luminance level detection circuit 20 for the black band portion is also simply referred to as the luminance level detection circuit 20.

Hereinafter, the drive sequence generation circuit 16, the sequence control circuit 18, and the luminance level detection circuit 20, which are features of the present invention, will be described in detail.

(Luminance Level Detection Circuit 20) First, the luminance level detection circuit 20 will be described. As described above, the video signal processing circuit 11 separates an input video signal (input image signal) S into a luminance signal SL and a chrominance signal SC, and outputs both signals SL and SC.

Then, the luminance level detection circuit 20 receives the luminance signal SL, and, based on the luminance signal SL, in all the discharge cells belonging to the electrode group X in the black band, all the sustain discharge periods in one field. It is determined whether a sustain discharge is not formed in or not.

That is, the luminance level detection circuit 20 generates a black signal (corresponding to a luminance level of zero) corresponding to the electrode group X or the display line group in the black band portion in the luminance signal SL for one display screen. Is determined. Specifically, the highest voltage level (corresponding to the highest luminance level) in the signal component corresponding to the black band portion is detected, and based on the detected highest voltage level, it is determined whether or not the black band portion performs black display. judge. Then, the result of the determination is output as a determination signal S20.

Here, FIGS. 2 and 3 show voltage waveform diagrams of the luminance signal SL corresponding to one display line. Note that, in each voltage waveform diagram, (two) pulses that transition to a side lower than the luminance level 0 are synchronization signals. FIG. 2 shows a luminance signal SL in the case where some display is performed instead of black display. That is, the highest voltage V in the luminance signal SL
max does not match the voltage corresponding to luminance level 0. On the other hand, in the luminance signal SL in the case of black display, the maximum voltage Vmax is equal to the voltage corresponding to the luminance level 0 as shown in FIG. Based on such a difference between the waveforms, the brightness level detection circuit 20 determines whether or not the black band is displaying black based on whether or not the maximum voltage Vmax is equal to the voltage corresponding to the brightness level 0.

(Sequence control circuit 18) The sequence control circuit 18 receives the judgment signal S20 and
When 0 indicates that the black band is a black display, a pulse applied to the row electrode X of the black band in the erasing period ET generates and outputs a control signal S18 of an instruction different from the display portion. . At this time, the sequence control circuit 18
When the black band is black, the row electrode X of the black band is displayed.
The number of a predetermined subfield in which the pulse applied to the subfield is to be changed, that is, the number of the subfield to which the priming pulse (first pulse) 31 is applied to the display portion or during normal display, is given. The control signal S18 is output during the erasing period ET of the subfield.

(Drive Sequence Generation Circuit 16) The drive sequence generation circuit 16 receives the control signal from the control circuit 15 and performs the same processing as that of the related art.
8 and the control signal from the control circuit 15, and based on both control signals, the erasing period ET of the predetermined subfield is performed.
Is changed to the erase pulse (second pulse).

FIG. 4 is a block diagram for explaining the drive sequence generation circuit 16. As shown in FIG. 4, the drive sequence generation circuit 16 includes drive sequence generation circuits 161 to 163 for an address driver, a scan driver, and a sustain driver.

The address driver drive sequence generation circuit 161 receives a control signal from the control circuit 15, generates a predetermined drive sequence based on the control signal, and outputs it to the address driver 24. The drive sequence generation circuits 162 and 163 for the scan driver and the sustain driver receive the control signal from the control circuit 15 and the control signal S18 from the sequence control circuit 18, and generate a predetermined drive sequence to generate the scan driver 22 or Maintenance driver 23
Output to

In particular, the driving sequence generating circuit 162 for the scanning driver and the driving sequence generating circuit 163 for the sustain driver have a different configuration from the conventional circuit. Here, FIG. 5 shows the sustain driver driving sequence generation circuit 16.
3 is a block diagram for explaining No. 3.

(Driving Sequence Generation Circuit 163 for Sustain Driver) As can be seen by comparing FIG. 5 with FIG.
A timing control circuit 48 and a changeover switch 47 are provided in place of the conventional timing control circuit 48P and a changeover switch 47P. In addition to this configuration, an application pulse changing circuit 49 and changeover switches 50 and 51 are provided.

More specifically, the output terminals of the priming pulse generation circuit (first pulse generation unit) 41 and the erase pulse generation circuit (second pulse generation unit) 42 are connected to a conventional circuit 163.
Like P, it is connected to the changeover switch 45 and also to the changeover switch 50. Also,
The changeover switch 51 includes the changeover switch 5
0, the output terminals of the write period pulse generation circuit 43 and the changeover switch 46 are connected.

The output terminal of the changeover switch 51 is connected to the input terminal of the circuit corresponding to the black band in the sustain driver 23 (see the signal transmission path 163A). The changeover switch 47 has the same configuration as that of the conventional changeover switch 47P and is controlled in the same manner as the conventional changeover switch 47P. It is connected to the input of the circuit (see signal transmission path 163B).

The timing control circuit 48 performs the following processing in addition to the control of the changeover switch 47 and the like, similarly to the conventional circuit 48P. That is, the control circuit 15 receives a control signal output from the control circuit 15 for switching between the time periods ET, WT, and ST arranged in time series, and applies the control signal S48 at a high level, for example, only during the erasing period ET of each subfield. Output to the change circuit 49. As will be described later, the control signal S48 may be continuously applied during each erasing period ET, or may be applied as a single pulse at the start of each erasing period ET. By the control signal S48, the applied pulse changing circuit 49 can know the erasing period ET in the driving sequence.

The applied pulse changing circuit 49 performs basically the same control as the control of the changeover switch 45 by the timing control circuit 48 (or 48P).
Perform for 0. In particular, the applied pulse changing circuit 49 receives the control signal S18 from the sequence control circuit 18 and the control signal S48 from the timing control circuit 48, and based on both control signals S18 and S48, the changeover switch 5
Control the output of 0.

With such a configuration, in the sustain driver driving sequence generation circuit 163, in the case of the wide mode,
(A) The timing control circuit 48 controls the drive sequence of the display portion in the same manner as in the related art, and (B) the drive pulse change circuit 49 controls the drive sequence of the black band portion. Hereinafter, the drive sequence for the black belt portion will be mainly described.

The changeover switch 51 is basically controlled by the timing control circuit 48 in the same manner as the changeover switch 47. That is, the changeover switch 51 selects and outputs the output of the changeover switch 50 during the erase period ET, outputs the output of the write period pulse generation circuit 43 during the write period WT, and generates the sustain discharge period pulse during the sustain discharge period ST. The output of the circuit 44 is selected and output.

The output of the changeover switch 50 is controlled by the applied pulse changing circuit 49. Specifically, the control signal S49 from the applied pulse changing circuit 49 is (a) H
When the signal is at the high level, the output of the erase pulse generating circuit 42 (ie, the erase pulse 32) is selected and output. (b) When the control signal S49 is at the Low level, for example, the output of the priming pulse generating circuit 41 (ie, priming) The pulse 31) is selected and output.

Here, the row electrode X in the display portion is applied to the above-described FIG.
The processing and operation of the drive sequence generation circuit 163 will be described by taking as an example a case where the voltage waveforms of FIGS. Note that, like the conventional drive sequence generation circuit 163P, the drive sequence generation circuit 163 applies the first, third, and fifth subfields SF1 to the row electrodes X in the display portion regardless of whether the mode is the wide mode. , SF3, SF
In each erase period ET of No. 5, a priming pulse 31 is applied, and the other subfields SF2, SF4, SF6
In each of the erase periods ET to SF8, the erase pulse 32 is applied. When the mode is not the wide mode (normal display), the drive sequence generation circuit 163 applies the priming pulse 3 to the electrode group X in the black band portion in the same manner as in the above-described display portion.
1 or erase pulse 32 is applied.

First, the luminance level detection circuit 20 determines whether or not the display image is in the wide mode, that is, whether or not the luminance signal SL for the black band is a black signal.
20 is output. The sequence control circuit 18 that has received the determination signal S20 outputs the following control signal S18 to the applied pulse changing circuit 49. That is, (a) in the case of the wide mode, the first, third, and fifth subfields SF1,
In each erase period ET of SF3 and SF5, for example, Hig
While outputting the h-level control signal S18, (b-1)
In the case of the wide mode, for example, a low-level control signal S18 is output in each of the erasing periods ET of the subfields SF2, SF4, SF6 to SF8 other than the above.
(B-2) In the case of normal display, for example, Lo in each erasing period ET of all subfields SF1 to SF8.
A w-level control signal S18 is output.

As described above, the timing control circuit 48
Is, for example, High during the erasing period ET of each subfield.
The level control signal S48 is output to the applied pulse changing circuit 49. Thus, the applied pulse changing circuit 49 takes, for example, a logical product (AND) of both control signals S18 and S48,
(A) When the operation result is High level, that is, the first, third, and fifth subfields SF in the wide mode
In each of the erasing periods ET of SF1, SF3 and SF5, the output of the changeover switch 50 is changed to a pulse of a type different from that in the normal display, that is, the erasing pulse 32. On the contrary,
(B) When the above calculation result is at the Low level, the applied pulse changing circuit 49 performs the same operation as in the normal display and the control of the changeover switch 47 by the timing control circuit 48,
The switch 50 is controlled (therefore, the switch 50 outputs the erase pulse 32).

As described above, in the case of the wide mode, the black band portion and the display portion are sequence-controlled independently in each erasing period ET, and the electrode group X in the black band portion has the erasing pulse 32 in all the subfields SF1 to SF8. Is applied. As described above, the erase pulse is applied to the preceding sustain discharge period S
Since the pulse can form a discharge only in the discharge cell in which the sustain discharge is formed in T, the erasing period in the wide mode (at the time of black display) in the black band portion (that is, in all the discharge cells belonging to the electrode group X). In ET, no discharge is formed.
Or even if a discharge is formed, it is only in the discharge cell in which the sustain discharge was formed in the first erasing period of the field immediately after switching from the normal display to the wide mode, and in the immediately preceding sustain discharge period.

Therefore, according to the driving device 201D or the plasma display device 201, the background luminance of the black band in the wide mode can be reduced as compared with the conventional driving method or the conventional plasma display device 201P. Thereby, high contrast, that is, high display quality can be obtained.

Now, the control signal S48 and the control signal S18
May be applied at least at the start of each erasing period ET, and the applied pulse changing circuit 49 controls the changeover switch 50 based on the calculation result at the start.
For example, when the control signal S48 is applied as a single pulse at the beginning of each erase period ET, the applied pulse changing circuit 49
Holds the control of the changeover switch 50 based on the calculation result at the initial time until the control signal S48 (single pulse of High level) is received in the next erasing period ET. Further, for example, when the control signal S48 is continuously applied during each erasing period ET, the operation result is retained during each erasing period ET, and while the operation result is at the High level, the applied pulse change circuit 49 is operated by the changeover switch. 50
Is set to the erase pulse 32.

Driving sequence generation circuit 1 for scanning driver
Reference numeral 62 basically has a configuration substantially equivalent to that of the sustain driver driving sequence generation circuit 163. Therefore, the configuration of FIG. 5 can be applied as the drive sequence generation circuit 162. However, since the drive sequence generation circuit 162 does not need to generate a pulse during the erasing period ET, FIG.
The part of the elements 41, 42, 45 in the middle is configured as a switch unit that switches to the ground potential or the ground electrode during the erasing period ET, for example, under the control of the timing control circuit 48 (for example, by the control signal S48). Thereby, a similar pulse can be generated.

<Second Embodiment> FIG. 6 is a block diagram illustrating a plasma display device 202 according to a second embodiment. As can be seen by comparing FIG. 6 with FIG. 1 described above, the driving device 202D of the plasma display device 202 replaces the luminance level detection circuit 20 of FIG. 1 with a subfield bit information determination circuit (black display determination unit). 1
7 is provided. Subfield bit information determination circuit 17
Receives a signal from the A / D conversion circuit (signal conversion unit) 13, executes a predetermined process described later based on the signal, and outputs the processing result to the sequence control circuit 18 as a signal S17. The other configuration is the same as that of the driving device 201D, and thus the above description will be referred to.

The difference between the two driving devices 201D and 202D lies in the types of signals used to determine the brightness or the brightness level in the displayed image. That is, the driving device 201D of the first embodiment uses the analog luminance signal SL separated from the video signal S, while
In 2D, subfield bit information (digital data) after digital conversion by the A / D conversion circuit 13 is used.

More specifically, in the driving device 202D, the A / D
The conversion circuit 13 converts the video signal S into subfield bit information indicating light emission / non-light emission of the discharge cells in the sustain discharge period ST in one field. Then, the subfield bit information determination circuit 17 detects the luminance level of the discharge cell in the black band portion from the subfield bit information, and performs the above-described determination based on the luminance level.

In the case of 8-bit gradation display, the information of the ith (1 ≦ i ≦ 8) bit counting from the LSB (including the LSB) of the signal after A / D conversion toward the MSB is This is information indicating whether or not the discharge cell emits light in the i-th subfield SFi. Here, if the bit information is “1”, it indicates light emission, and if “0”, it indicates no light emission. For example, the MSB corresponding to the eighth subfield SF8 and the MSB corresponding to the seventh subfield SF7
If each bit information of the next lower bit is “1”, it can be determined that such image information is a signal that causes bright light emission. Further, for example, when each bit information corresponding to each of the subfields SF1 to SF8 is “0”, it can be determined that such image information is a signal that causes dark (dark) light emission.

In view of the above, the subfield bit information determination circuit 17 executes the following processing. First, a signal or data after the A / D conversion of the video signal S is received from the A / D conversion circuit 13. Note that only a portion corresponding to a discharge cell in a black band portion in the signal may be received. Further, the above signal may be read from the frame memory 14.

Next, it is checked whether or not each of the subfield bit information corresponding to each of the discharge cells in the black band in the received signal is "00000000".
When the subfield bit information is “00000000” for all of the discharge cells in the black band, it is determined that the display screen (of one screen) is in the wide mode having the black band above and below. Conversely, if at least one piece of subfield bit information is not “00000000”, it is determined that the display screen (of one screen) is not in the wide mode. Similar to the luminance level detection circuit S20 in FIG. 1, the subfield bit information determination circuit 17 outputs a determination result to the sequence control circuit 18 as a determination signal S17 (corresponding to the above-described determination signal S20). If the determination signal S17 is a signal indicating that the display image is in the wide mode, the sequence control circuit 18 performs the same processing and operation as in the first embodiment.

According to the driving device 202D, the following effects can be obtained in addition to the effects of the driving device 201D described above. That is, the above-described luminance level detection circuit 20 is configured by an analog circuit, and determines the luminance signal SL of the black band portion by line, and finally determines whether or not the signal for one screen is a wide mode signal. Is determined. On the other hand, a configuration capable of performing a digital operation, for example, a microcomputer or the like can be applied as the subfield bit information determination circuit 17. Accordingly, the subfield bit information determination circuit 17 requires fewer circuit components, and the circuit 17 and the plasma display device 202 can be configured with a simple and small configuration.

<Third Embodiment> In some cases, the video signal S itself superimposes information or a signal (hereinafter also referred to as an "aspect ratio signal") for notifying the aspect ratio of the signal, for example, in a vertical period. In the third embodiment, a description will be given of a PDP driving device that controls an application pulse to a black band portion in an erasing period ET using such a video signal S.

FIG. 7 is a block diagram for explaining a plasma display device 203 according to the third embodiment. As can be seen by comparing FIG. 7 with the above-described FIG. 1, the driving device 203D of the plasma display device 203 includes:
An aspect ratio determination circuit (black display determination unit) 19 is provided in place of the luminance level detection circuit 20 in FIG.

The aspect ratio judging circuit 19 receives the video signal S, judges whether or not the video signal S has an aspect ratio signal superimposed thereon. It is determined whether or not the aspect ratio signal is a wide mode aspect ratio (whether or not the information is related to a predetermined aspect ratio). The result of the determination is output to the sequence control circuit 18 as a determination signal S19 (corresponding to the above-described determination signal S20). If the determination signal S19 is a signal indicating that the video signal S includes the aspect ratio signal and the display image is in the wide mode, the sequence control circuit 18 performs the same processing and operation as in the first embodiment. Execute. The other configuration is the same as that of the driving device 201D, and thus the above description will be referred to.

According to the driving device 203D, the following effects can be obtained in addition to the effects of the driving device 201D described above. That is, according to the aspect ratio determination circuit 17, the display image is formed by a simple process or a simple configuration of determining whether the video signal S includes an aspect ratio signal indicating the wide mode. Is in the wide mode, that is, it is determined whether or not the black band is black. Therefore, the driving device 203D and the plasma display device 203 can have a simple and small configuration.

In the first to third embodiments, in the drive sequence at the time of normal display and the drive sequence of the display portion, it is sufficient to apply the priming pulse 31 at least once in one field. Can be assured.

The above description is also valid when the respective periods ET, WT, and ST are executed in the order of the writing period WT, the sustain discharge period ST, and the erasing period ET in each subfield.

[0092]

(1) According to the first aspect of the invention, the black display determination unit does not form a sustain discharge in all sustain discharge periods in one field in all discharge cells belonging to the predetermined electrode group. (In other words, when it is determined that the screen area corresponding to the electrode group in the screen of the plasma display panel is a black display), the driving device for the plasma display panel performs all the operations in one field. A second pulse is output to the electrode group during the erasing period. At this time, the second pulse can form a discharge only in the discharge cells that have generated the sustain discharge in the preceding sustain discharge period. Therefore, in all the discharge cells belonging to the electrode group, no discharge is formed in the erasing period during black display, or even if a discharge is formed, in the first erasing period of the first field when starting black display, This is only in the discharge cells in which the sustain discharge was formed in the immediately preceding sustain discharge period. Therefore, the luminance (so-called background luminance) of the screen area corresponding to the electrode group during black display can be reduced as compared with the case where the first pulse is applied. Thereby, the contrast can be improved.

On the other hand, in the case other than black display, the first pulse is output. Therefore, by using the first pulse as the priming pulse, the writing operation can be ensured by the priming effect of the priming pulse.

(2) According to the second aspect of the invention, the same effect as the above (1) can be obtained.

(3) According to the third aspect of the invention, the black display determination section makes the above determination using the digital data obtained by converting the input image signal. For this reason, by applying a configuration capable of digital operation, for example, a microcomputer or the like, as the black display determination unit, the number of circuit components can be reduced as compared with the case of using an analog circuit. Therefore, the black display determination unit and the plasma display panel driving device can be configured in a simple and compact configuration.

(4) According to the fourth aspect of the invention, the black display determination section has a simple process or a simple configuration for determining whether or not the input image signal includes information relating to a predetermined aspect ratio. The above determination is made. For this reason, the black display determination unit and the plasma display panel driving device can have a simple and small configuration.

(5) According to the fifth aspect of the present invention, the first pulse capable of forming a discharge in the discharge cell regardless of the formation of the sustain discharge in the preceding sustain discharge period, and the first sustain discharge period Thus, the second pulse capable of forming a discharge only in the discharge cell in which the sustain discharge is formed can be reliably generated.

(6) According to the invention of claim 6, the background luminance of upper and lower non-display portions (black band portions) in so-called wide mode display can be reduced, and the contrast of the plasma display panel can be improved. .

(7) According to the seventh aspect of the present invention, it is possible to provide a plasma display device having high display quality by exhibiting any of the effects (1) to (6) in the plasma display device. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining a plasma display device according to a first embodiment.

FIG. 2 is a voltage waveform diagram illustrating an example of a luminance signal.

FIG. 3 is a voltage waveform diagram for explaining a luminance signal in the case of black display.

FIG. 4 is a block diagram for explaining a drive sequence generation circuit of the plasma display device according to the first embodiment.

FIG. 5 is a block diagram for explaining a drive sequence generation circuit of the plasma display device according to the first embodiment.

FIG. 6 is a block diagram illustrating a plasma display device according to a second embodiment.

FIG. 7 is a block diagram illustrating a plasma display device according to a third embodiment.

FIG. 8 is a schematic perspective view for explaining the structure of a surface discharge type AC plasma display panel.

FIG. 9 is a block diagram for explaining a conventional plasma display device.

FIG. 10 is a schematic diagram for explaining a gradation display method.

FIG. 11 is a timing chart for explaining a first conventional driving method.

FIG. 12 is a timing chart for explaining a second conventional driving method.

FIG. 13 is a timing chart for explaining a second conventional driving method.

FIG. 14 is a block diagram for explaining a driving sequence generation circuit of a conventional plasma display device.

[Explanation of symbols]

13 analog-digital conversion circuit (signal conversion unit),
15 control circuit, 16 drive sequence generation circuit, 17
Subfield bit information determination circuit (black display determination unit),
Reference Signs List 18 sequence control circuit, 19 aspect ratio determination circuit (black display determination section), 20 black band luminance level detection circuit (black display determination section), 21 plasma display panel, 22 scan driver, 23 sustain driver, 31
Priming pulse (first pulse), 32 erase pulse (second pulse), 40 erase period pulse generation circuit,
41 priming pulse generating circuit (first pulse generating unit), 42 erasing pulse generating circuit (second pulse generating unit), 49 applied pulse changing circuit, 50, 51 switch, 162 scan driver driving sequence generating circuit, 163 sustain driver Drive sequence generation circuit, 201-203 Plasma display device, 20
1D to 203D Driving device for plasma display panel, S video signal (input image signal), S17, S20
Determination signal, S19 determination signal, SL luminance signal, A
Column electrode (second electrode), ET erase period, SF subfield, ST sustain discharge period, X row electrode (first electrode), Y row electrode, WT write period.

Claims (7)

[Claims] 1. A plurality of strip-shaped first electrodes, a plurality of strip-shaped second electrodes intersecting with the plurality of first electrodes via a discharge space, respectively, each of the first electrodes and each of the second electrodes. And a plurality of discharge cells defined by each intersection with the plasma display panel. The plasma display panel driving device drives one field based on an erasing period and an input image signal. After dividing into a plurality of subfields including a writing period for performing a writing operation on a predetermined discharge cell and a sustaining discharge period for generating a sustaining discharge in the predetermined discharge cell on which the writing operation has been performed, the plasma In a driving device for a plasma display panel for driving a display panel, formation of the sustain discharge in the preceding sustain discharge period
A first type capable of forming a discharge in the discharge cell regardless of non-formation;
A first pulse generation unit that generates a pulse; a second pulse generation unit that generates a second pulse capable of forming a discharge only in the discharge cell that has generated the sustain discharge in the preceding sustain discharge period; The determination as to whether or not the sustain discharge is formed in all the sustain discharge periods in the one field in all the discharge cells belonging to a predetermined electrode group among the first electrodes is based on the input image signal. And a black display determination unit that performs the black display determination unit, wherein the black display determination unit
At least one of the discharge cells
When it is determined that the sustain discharge is formed in the two sustain discharge periods, the driving device for a plasma display panel includes the first discharge device.
While outputting the first pulse to the electrode group in at least one of the erasing periods in a field, the black display determination unit determines that all the discharge cells belonging to the electrode group are in the one field. When it is determined that the sustain discharge is not formed in all the sustain discharge periods, the driving device for a plasma display panel performs
A driving device for a plasma display panel, wherein the second pulse is output to the electrode group during all the erasing periods in a field. 2. The driving device for a plasma display panel according to claim 1, wherein the input image signal includes a luminance signal, and the black display determination unit determines the discharge cell belonging to the electrode group from the luminance signal. Wherein the luminance level is detected and the determination is made based on the luminance level. 3. The driving device for a plasma display panel according to claim 1, wherein the input image signal is a digital signal indicating light emission / non-light emission of each of the discharge cells in each of the sustain discharge periods in the one field. A signal conversion unit that converts the data into data; wherein the black display determination unit detects a luminance level of the discharge cells belonging to the electrode group from the digital data, and performs the determination based on the luminance level. A driving device for a plasma display panel. 4. The driving device for a plasma display panel according to claim 1, wherein the black display determination unit determines whether or not the input image signal includes information of an aspect ratio of a display image, and includes the information. When it is determined that the information on the aspect ratio is information on a predetermined aspect ratio, the sustain discharge is formed in all the sustain discharge periods in the one field by all the discharge cells belonging to the electrode group. A driving device for a plasma display panel, characterized in that it is determined not to be performed. 5. The plasma display panel driving device according to claim 1, wherein the amplitude of the second pulse is smaller than that of the first pulse. Drive. 6. The driving device for a plasma display panel according to claim 1, wherein the electrode group includes a predetermined number of the electrodes from each end of an array in the plurality of first electrodes. Including a first electrode,
Drive device for plasma display panel. 7. A plurality of strip-shaped first electrodes, a plurality of strip-shaped second electrodes intersecting with the plurality of first electrodes via a discharge space, respectively, each of the first electrodes and each of the second electrodes. And a plasma display panel comprising a plurality of discharge cells defined by each intersection with the plasma display panel, and the plasma display panel driving device according to any one of claims 1 to 6. ,
Plasma display device.