JP2001285302A - Wireless lan system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wireless LAN system to decrease traffic in wireless interval and to have possibly address filtering function with low cost, miniaturizing, and quick retrieving. SOLUTION: In a control part 20 of key station for the wireless LAN system, transmitting address is registered in an associative memory 'CAM 29' which is content addressable and the transmitting address for a transmitting packet is applied sequentially with divided into plural times by the CAM control/address filtering circuit 30. Sequential address retrieval can be performed for the CAM 29 and if it is not be registered, the indicating signal for packet abolishment sends to the Ethernet 'R' controller 25 in the wireless LAN system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wireless LAN system comprising a base station connected to a wired LAN and a slave station for transmitting and receiving data to and from the base station by radio.
A wireless LA that can reduce the amount of traffic in a wireless section and can quickly search for a registered destination address
N system.

[0002]

2. Description of the Related Art A conventional wireless LAN system will be described. In a conventional wireless LAN system, the amount of data transmission tends to increase as compared to a wired LAN due to the addition of frame configuration bits and the addition of an error correction function / encryption function and the like accompanying wireless communication.

When considering a mixed system of a wired LAN and a wireless LAN, it is desirable to incorporate an address filtering function for preventing unnecessary packets from flowing to the wireless section in order to reduce the traffic volume in the wireless section. This address filtering function is a wired LAN
, Only packets addressed to a network address registered in advance are selected, and packets not selected are discarded.

As a conventional wireless LAN system, there is a wireless data system “WL-100” sold by Nippon Telegraph and Telephone Corporation. In this system, in order to realize the address filtering function, an FFD (Forwarding and F
iltering Device: AH70 manufactured by Cameo Communication
20A).

[0005] In IEEE802.3, CSMA / CD (Carrier Sens) is used as an access method in a LAN.
e Multiple Access with Collision Detection). CSMA / CD checks whether each terminal of the network has a current signal on a common line (carrier sense).
), If there is an empty state, the packet type message is put on the bus and broadcast to each terminal device (multiple access).
) And simultaneously monitor other terminal devices, and when a certain terminal device starts transmitting, it detects this (collision dete
ction) to avoid message collision.

As a conventional example of a wireless LAN system, Japanese Patent Laid-Open Publication No. Hei 10-173665 published on June 26, 1998, “Virtual Wireless LAN System”
(Applicant: Nippon Telegraph and Telephone Corporation, Inventor: Masanori Shibayama and others). In this technology, a management server on the home network side is provided with means for managing the attributes of LAN terminals, and a destination server on the remote network side is provided with means for determining and managing the attributes of the LAN terminals. It is possible to identify a packet transmitted via a base station, and to determine whether or not to connect to a terminal and to perform communication suitable for the attribute of the terminal.

[0007]

However, the filtering LSI for realizing the above-mentioned conventional address filtering function has a feature that it can support two Ethernet ports and can manage up to 8192 addresses. High, the package size is as large as 100 pins, there are problems with low cost and miniaturization, and the address search time is 900n as standard
s, it takes 5.4 μs at the maximum, so there is also a problem in increasing the speed.

For these reasons, realizing a filtering function using this dedicated LSI is not suitable for a small-scale / low-cost system or a system requiring high-speed search.

The present invention has been made in view of the above circumstances, and provides a wireless LAN system having an address filtering function capable of reducing the traffic volume in a wireless section, being low-cost, compact, and capable of high-speed search. With the goal.

[0010]

SUMMARY OF THE INVENTION The present invention for solving the above-mentioned problems of the prior art is provided in a wireless LAN system.
The master station registers the address of the slave station that performs wireless communication in the content addressable storage device identified and searched according to the content of the data, and the destination address of the Ethernet packet received from the backbone is registered in the content addressable storage device. If it is registered, the packet is transmitted, but if it is not registered, the packet is discarded so that transmission is not performed. This speeds up the search for the destination address. In addition, unnecessary packets can be prevented from being transmitted between the master station and the slave stations, and the traffic amount in the wireless LAN can be reduced.

Further, according to the present invention, in the above-described wireless LAN system, the master station separates and sequentially inputs destination addresses of packets to be transmitted, and the destination addresses are sequentially registered in the associative storage device in accordance with the input. The search for the presence / absence is performed, and the search for the destination address can be further speeded up.

[0012]

Embodiments of the present invention will be described with reference to the drawings. Note that the function realizing means described below may be any circuit or device as long as the function can be realized, and some or all of the functions may be realized by software. is there. Further, the function realizing means may be realized by a plurality of circuits, or the plurality of function realizing means may be realized by a single circuit.

A wireless LAN system according to an embodiment of the present invention includes a master station (CM) connected to a backbone of a wired network and a slave station (U) that performs wireless communication with the CM.
M), when the CM transmits a packet to the UM, a destination address is registered in an associative storage device that is identified and searched according to data content, and the destination address of the transmitted packet is stored in the associative memory. The address data which is registered in the apparatus or is sequentially separated and input by the control means for performing search control is sequentially searched, and if not registered, the packet is discarded by the Ethernet controller.
As a result, it is possible to prevent unnecessary packets having no destination from being transmitted between the CM and the UM, and it is possible to reduce a traffic amount in the wireless LAN. In FIG. 2, the CAM 29 corresponds to the associative storage device, and the CAM control / address filtering circuit 30 corresponds to the control means for performing search control.

Next, the wireless LA according to the embodiment of the present invention
The N system will be described with reference to FIG. FIG. 1 is a configuration block diagram of a wireless LAN system according to an embodiment of the present invention. As shown in FIG. 1, a wireless LAN system according to the present embodiment (this wireless LAN system) includes a backbone 1 of a wired network, and a master station (C) connected to the backbone 1 and communicating between the wired LAN and the wireless LAN.
M) 2, a slave station (UM) 3 that performs wireless communication via the master station 2 in the service area of the master station 2, and a personal computer (PC) 4 to which the slave station 3 is connected. Have been.

Each part of the wireless LAN system will be specifically described. The backbone 1 is composed of 10Base-T or 100Base-TX Ethernet using UTP (Unshielded Twisted-Pair) cable, which is the most widely used LAN. Master station (CM: Control Modu
le) 2 is connected to a plurality of wired networks of the backbone 1 and can configure one service area with several CMs, or each can configure another service area. is there. When different service areas are configured, communication is performed between a certain CM and another CM via the network of the backbone 1. The embodiment of the present invention is characterized by the processing in the CM 2. Specific processing contents will be described later.

The child station (UM: User Module) 3 is individually connected to the PC 4 serving as a client, performs registration management for a specific CM 2, and performs wireless communication only with the registered CM 2. If the UM3 moves and departs from the service area of the currently registered CM2, the CM
Registration is deleted from 2. Then, when entering the service area of another CM2, registration is newly performed for that CM2, and wireless communication with that CM2 becomes possible. In FIG. 1, the UM 3 is connected to a personal computer (PC) having a PC card slot via a PC card interface.

The personal computer (PC) 4 has a U
It is a terminal device for transmitting and receiving data via M3. In particular, since it is a terminal for a wireless LAN, a notebook personal computer, a portable information terminal, or the like can be considered. In FIG. 1, UM
3 has a PC card interface.
No. 4 needs to have a PC card slot. In FIG. 1, three notebook computers (4a, 4b, 4
c) and UMs 3a, 3b, 3c connected to them.

The operation of the wireless LAN system will be described. When communication is performed between a plurality of UMs 3 managed by one CM 2, wireless data is not transferred directly between the UMs 3 but wireless data is transferred via the managed CM 2.
When communication is performed with the UM 3 managed by another CM 2, the communication with the UM 3 under the management is performed via the network of the backbone 1 via the CM 2 managed by itself, and via the other CM 2. Send and receive.

Next, the wireless LA according to the embodiment of the present invention
FIG. 2 shows the configuration of the master station (CM) 2 in the N system.
This will be described with reference to FIG. FIG. 2 is a configuration block diagram of a CM in the wireless LAN system according to the embodiment of the present invention. As shown in FIG. 2, the CM 2 of the wireless LAN system includes an antenna unit 11, a wireless transmission / reception unit (RF unit) 12 connected to the antenna unit 11, and a modulation / demodulation unit (IF unit) connected to the RF unit 12. 13, a transmission / reception signal forming unit (baseband control unit: BB control unit) 14 connected to the IF unit 13,
And a control unit 20 connected to the B control unit 14.

Further, the control unit 20 controls the operation of the entire CM 2 according to a control program.
essing Unit) 21 and a memory 22 for storing its control program and used as a work area of the MPU 21
, A transmission / reception buffer memory 23 used for transmitting and receiving data to and from the BB control unit 14, a PCI bus bridge 24 for performing bus conversion between an MPU local bus and a PCI bus, and an Ethernet controller 25 connected to the PCI bus. An Ethernet physical layer controller 26 connected to the Ethernet controller 25, a pulse transformer 27 and a modular jack 28 for connecting the Ethernet physical layer controller 26 to the Ethernet backbone, and a CAM for performing address search.
29, and a CAM control / address filtering circuit 30 for controlling the CAM 29.

Next, the main parts in the control unit 20 will be specifically described. The MPU 21 executes processing in the control unit 20 by a program stored in the memory 22.
In particular, a process of outputting the received data stored in the transmission / reception buffer memory 23 from the BB control unit 14 to the Ethernet backbone, or storing transmission data in the transmission / reception buffer memory 23 for transmitting data input from the Ethernet backbone to the UM3. And so on.
The MPU 21, the memory 22, the transmission / reception buffer memory 2
3. The PCI bus bridge 24 and the CAM control / address filtering circuit 30 are connected to each other via an MPU local bus interface.

The memory 22 includes a nonvolatile memory for storing program codes and stored data, and a RAM used as a work area of the MPU 21. The transmission / reception buffer memory 23 is a memory for temporarily storing transmission / reception data between the control unit 20 and the BB control unit 14.

[0023] PCI (Peripheral Component Interconn)
ect) The bus bridge 24 is a circuit for connecting the Ethernet controller 25 to the MPU local bus interface, and is unnecessary when the Ethernet controller 25 can be directly connected to the MPU local bus. That is, when the Ethernet controller 25 has a PCI local bus as a bus interface, the PCI bus bridge 24 is required as shown in FIG.

As the Ethernet controller 25, one having a function of selectively discarding received packets under external control is used. The discarding of the packet in the Ethernet controller 25 is performed based on the packet input from the PCI bus bridge 24 and the Ethernet physical layer controller 2.
6 is performed on the packet inputted from the terminal 6. An example of such an Ethernet controller 25 is AMD
Am79C971 manufactured by the company. Note that, in the embodiment of the present invention, the CAM control / address filtering circuit 30 shown in FIG.

The Ethernet physical layer controller 26
Ethernet controller 25 and MII (Media Indepe
ndent Interface), connected via pulse transformer 2
7 as a network medium.

The pulse transformer 27 converts a bit input from the Ethernet physical layer controller 26 into a pulse signal and outputs the pulse signal to the Ethernet backbone via the RJ45 modular jack 28, and from the Ethernet backbone via the RJ45 modular jack 28. The input pulse signal is converted into bits and output to the Ethernet physical layer controller 26. The RJ45 modular jack 28 connects the 10Base-T or 100Base-TX Ethernet backbone and the control unit 20 of the CM.

CAM (Content-Addressable Memory) 2
Reference numeral 9 denotes an associative storage device in which the storage location of the target data is identified not by its address or name, but by its contents (part of the data contents or designated search conditions). . This is also called a content address memory. Usually, associating the entire storage device is expensive, so this configuration is applied to only a part of the storage device. The associative storage device is applied to a database search for processing large-capacity data at high speed, and performs high-speed memory access using a dedicated processor. As a specific example, IBM
In Table Lookasid Buffer
An address in the real memory corresponding to the program address is obtained by a high-speed associative memory type access using a device called an e-buffer. ”P14
81).

In the embodiment of the present invention, a CAM applied to a database search is used for searching for a destination for discarding a packet, and an address of a transmission destination of a packet is registered in advance. Specifically, MUSIC Semiconducto
The rs device CAM device MU9C3640L is used. This CAM device is for inputting 48-bit comparison data three times every 16 bits and sequentially searching for target data (registered address data), and searches for target data at high speed. Is what you can do.

The CAM control / address filtering circuit 30 accesses the CAM 29 at high speed, refers to the address registered in the CAM 29, and outputs a judgment as to whether or not there is a target address. That is, it is control means for using the CAM 29 applied to the embodiment of the present invention for address filtering.

More specifically, the CAM control / address filtering circuit 30 stores the data input via the MPU local bus and the Ethernet physical layer controller 26.
The CAM 29 refers to the CAM 29 with respect to the data input to the Ethernet controller 25 and outputs a filtering instruction to the Ethernet controller 25 so as to select only the packet addressed to the registered network address.
The specific operation of the CAM control / address filtering circuit 30 will be described later with reference to FIG.

The interface between the Ethernet controller 25 and the Ethernet physical layer controller 26 is the MII defined by IEEE802.3. An IEEE 802.3 transfer frame format shown in FIG. 3 is transferred in 4-bit units on this MII interface separately for transmission and reception, and the destination address of the received data can be determined. FIG.
FIG. 3 is a diagram illustrating an EEE802.3 transfer destination frame format and an address format.

[0032] As shown in FIG.
The transfer frame format of 2.3 includes a preamble portion having 7 octets, a frame start portion having 1 octet, a destination address portion having 6 octets, a source address portion having 6 octets, and a data length portion having 2 octets. ,
It comprises a data area part having 46 to 1500 octets and a frame check part having 4 octets.

Further, as shown in FIG.
The 802.3 address format is used for the destination address portion and the source address portion, and includes an I / G (indicating an individual address or a broadcast address) and a U / L (global management address or local management address). Show)
And an actual address of 46 bits. The addresses of the destination address portion and the source address portion are generally called MAC addresses.

Here, the destination is a destination controlled by a destination address on a transfer packet in accordance with a transfer frame format defined in IEEE802.3, which is an Ethernet standard. It is necessary to determine whether the destination address, generally called a MAC address, is addressed to the CM itself or to a UM under the CM, and it is necessary to receive a packet having a destination address that does not correspond to the CM. It is determined that there is no packet and discard control of the packet is performed. In the embodiment of the present invention, this packet discard control is realized by the CAM 29 and the CAM control / address filtering circuit 30.

As a result, unnecessary packets become CM-UM
It can be prevented from flowing into the wireless section between the wireless sections, and the traffic volume in the wireless section can be reduced. In addition, this leads to not performing unnecessary wireless output, and has an effect of reducing power consumption of the CM.

For example, in the case of a system capable of accommodating up to 80 UMs per CM, it is only necessary to manage a total of 81 addresses of 80 UMs and 1 address of the CM as destination addresses. To register and search destination addresses of this size, for example, use the MUSIC Semicond
uctors CAM device MU9C3640L can be used. The MU9C3640L is very compact in a 32-pin TQFP package, and can register addresses up to 256 entries. It has the ability to perform an address search at a maximum of 90 ns to determine whether an externally input address matches a registered address. That is, when the CAM 29 and the CAM control / address filtering circuit 30 are realized by the MU9C3640L, the circuit of the control unit 20 in the CM can be reduced in size, can be configured at low cost, and can further speed up the address search.

Next, the operation of the CAM control / address filtering circuit 30 according to the embodiment of the present invention will be described with reference to FIG. FIG. 4 is a timing chart showing signals on the MII interface from the end of the preamble section to the destination address section when receiving a packet, and the operation of the CAM control / address filtering circuit.

On the MII interface, received data is transferred from the Ethernet physical layer controller 26 to the Ethernet controller 25 in 4-bit units. Device Am79 as Ethernet controller 25
When receiving a packet, the C971 completes the preamble portion having a length of 7 octets (56 bits) and completes the 1 octet (8 bits).
When an SFD (Start Frame Delimiter: frame start portion) having a bit length is detected, SFBD (Start Frame-Byte Del.) Is detected.
imiter) Assert (enable) the signal. SFBD
Since the signal is high active, the signal rises from low to high.

The CAM control / address filtering circuit 30 is a state machine which operates using the SFBD signal as a trigger and the rising edge of the reception clock RXCLK on the MII interface as a reference timing. When the SFBD signal goes high for the first time after the start of reception, the state machine starts. RD1 (3: 0), R
D2 (3: 0) and RD3 (3: 0) are 4-bit / 3-stage shift register outputs, which are obtained by shifting the reception data RXD (3: 0) on the MII interface by the reception clock RXCLK.

The CAM device MU9C3640L has 1
Since it has a 6-bit comparison data input terminal, by latching the 4-bit / 3-stage shift register output and RXD (3: 0) at the rising edges of the fourth, eighth, and twelfth RXCLKs in FIG. The comparison data DQ (15: 0) having a 16-bit width is generated. MU9C3640L
Sets an operation mode in which the comparison data of 48 bits can be input in three times of 16 bits each. In the example of FIG. 4, "10: 32: 54: 76:
98: BA "has been received.

The comparison data DQ generated at the above timing
(15: 0), the CAM device MU9C364
The chip select signal / E (“/” indicates low active) is asserted by the fifth RXCLK so that the timing specification of 0L is satisfied (valid [assertion means falling since the chip select signal is low active). ), Deassert at the eighth (deassert means rise since the chip select signal is low active), assert (fall) at the ninth, deassert (rise) at the twelfth, thirteenth Control to de-assert (start up) at the 16th.

The write enable signal / W is asserted (falling) until the fourth RXCLK (third in the example of FIG. 4), and deasserted (rising) after the 16th RXCLK. Here, the CAM device MU9C3640
In order to use L for the comparison operation, the signal / CM of the data / command switching terminal is controlled to a high level indicating the data mode.

At such timing, the MU9C3640
When L is controlled, “10325476” is used as comparison data.
98BA "will be input. This "10
32547698BA ”is a CAM device MU as a MAC address of a CM or a UM registered under the CM.
9C8640L, the signal / MF at the match flag output terminal indicating whether or not there is a match is 3
Up to 2 from the deassertion of the chip select signal / E
It is asserted (driven to a low level) in 5 ns. As a result, it is determined that the received packet should be received, and the Am79C9 of the Ethernet controller 25 is determined.
At 71, the signal / EAR of the received packet discard control terminal
Is not asserted (this example is not shown in FIG. 4).

On the other hand, in advance, "1032547698
BA "is CM or UM MA registered under the CM
If the C address is not registered in the CAM device MU9C3640L, as shown in FIG. 4, the signal / MF at the match flag output terminal is deasserted (high level) at a maximum of 25 ns from the deassertion of the third chip select signal / E. Driven). As a result, since the received packet is not addressed to the CM or addressed to any UM under the CM, it is determined that the received packet does not need to be received. 17th RXCLK
(This example is shown in FIG. 4).

Am 79 of Ethernet controller 25
When the signal / EAR of the received packet discard control terminal is asserted at the timing shown in FIG. 4, the C971 discards the packet being received and does not perform the receiving process. As a result, it is possible to prevent unnecessary packets without a receiving party from being transmitted in the wireless section between the CM and the UM, and it is possible to reduce the traffic volume in the wireless section. In particular,
In addition to preventing the CM from transmitting a packet to the unregistered destination input from the backbone 1 wirelessly to the subordinate UM, the CM also transmits the packet to the unregistered UM in communication between the subordinate UMs. It is possible to prevent wireless transmission.

According to the wireless LAN according to the embodiment of the present invention, a high-speed address search function can be realized by using a small and inexpensive CAM. There is an effect that generation of unnecessary traffic in a section can be eliminated. Thereby, the effective throughput of the wireless LAN system can be improved.

[0047]

According to the present invention, the master station registers the address of the slave station performing the wireless communication in the content addressable memory device identified and searched according to the content of the data, and stores the address of the Ethernet packet received from the backbone. A search is performed to determine whether the destination address is registered in the associative storage device. If the destination address is registered, the packet is transmitted. If the destination address is not registered, the packet is discarded and the transmission is not performed.
Since the system is used, it is possible to speed up the search for the destination address, prevent unnecessary packets from being transmitted between the master station and the slave station, and reduce the amount of traffic in the wireless LAN.

Further, according to the present invention, in the above-described wireless LAN system, the master station separates and sequentially inputs the destination addresses of the packets to be transmitted, and the destination addresses are registered in the associative storage device at any time according to the input. Since the search for the presence or absence of the address is performed, there is an effect that the search for the transmission destination address can be further speeded up.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a wireless LAN system according to an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a CM of the wireless LAN system according to the embodiment of the present invention.

FIG. 3 is a diagram illustrating an IEEE 802.3 transfer destination frame format and an address format.

FIG. 4 is a timing chart showing signals on the MII interface from the end of the preamble section to the destination address section when receiving a packet and the operation of the CAM control / address filtering circuit.

[Explanation of symbols]

1 ... backbone, 2 ... master station (CM), 3 ... slave station (UM), 4 ... personal computer (PC),
11: an antenna unit, 12: a radio transmitting / receiving unit (RF unit),
13: Modulation / demodulation unit (IF unit), 14: Transmission / reception signal forming unit (baseband control unit: BB control unit), 20: Control unit, 21: MPU, 22: Memory, 23: Transmission / reception buffer memory, 24: PCI bus bridge , 25
... Ethernet controller, 26 ... Ethernet physical layer controller, 27 ... Pulse transformer, 28 ...
Modular jack, 29 ... CAM, 30 ... CAM control / address filtering circuit

Claims (3)

[Claims] 1. A wireless LAN system having a backbone of a wired network, a master station connected to the backbone, and a slave station for transmitting and receiving packets to and from the master station by radio, wherein the master station has data contents. The address of the slave station that performs wireless communication is registered in the associative storage device identified and searched for, and when a packet is transmitted to the slave station, the destination address of the packet is registered in the associative storage device. A wireless LAN system characterized in that it is a master station that searches whether or not the packet has been registered, and transmits the packet if registered, but discards the packet if not registered and does not transmit. 2. A master station which separates and sequentially inputs a destination address of a packet to be transmitted, and sequentially searches whether or not the destination address is registered in an associative storage device according to the input. The wireless LAN system according to claim 1, wherein: 3. A wireless LAN system having a backbone of a wired network, a master station connected to the backbone, and a slave station transmitting and receiving packets to and from the master station by radio, wherein the master station includes an antenna unit. , A wireless transmitting and receiving unit connected to the antenna unit, a modulation and demodulation unit connected to the wireless transmission and reception unit, a transmission and reception signal forming unit connected to the modulation and demodulation unit,
A master station having a control unit connected to the transmission / reception signal forming unit, wherein the control unit stores an MPU that controls an operation in the control unit according to a control program, and stores the control program as a work area of the MPU. A memory to be used, a transmission / reception buffer memory for passing transmission / reception data to / from the transmission / reception signal forming unit, an Ethernet controller for performing discard control of a packet to be transmitted in accordance with an external discard instruction, and an Ethernet physical device connected to the Ethernet controller A layer controller, a pulse transformer and a modular jack for connecting the Ethernet physical layer controller to the Ethernet backbone, a CAM storing a destination address to be identified and searched according to the content of data, Destination A Sequentially inputs to separate the less, by searching whether the destination address in sequence the CAM in accordance with the input is registered, CAM control to output a discard instruction to the Ethernet controller if not registered /
A wireless LAN system comprising a control unit having an address filtering circuit.