JP2001284810A - Wiring board and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board having a via structure and capable of solving a problem of connection reliability and coping with higher level integration, and its manufacturing method, and further provide a wiring board which can be easily manufactured by using the exsisting facilities for manufacturing of general printed wiring boards, ensure connection reliability and cope with higher level integration and has a filled via, and to provide its manufacturing method. SOLUTION: This wiring board is formed by a method wherein a wiring board in which a wiring part is formed on the surface is made a base substrate, and at least one wiring layer is laminated on the surface of the base substrate on which surface the wiring part is formed by interposing an insulating layer every one wiring layer. A via formed on the insulating layer is filled with a conductor layer. Further, a conductor layer is formed by plating.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board and a wiring forming method, and more particularly to a wiring board having a structure in which a via connecting between wirings is buried in a conductive layer, and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the advent of multimedia, miniaturization, weight reduction, high speed, and high functionality have progressed mainly in consumer devices such as mobile phones, video cameras, and personal computers, and the miniaturization of chips and chip peripheral parts has been increasing. Changes in the form and mounting method of semiconductor packages will progress. This inevitably increases the density of printed wiring boards on which chips and chip peripheral components are mounted, and as a result, printed wiring boards with high-density wiring are required. In recent years, as a corresponding technology, a manufacturing method called a build-up method has been attracting attention. In this method, an insulating layer and a wiring layer are repeatedly formed by laminating a two-layer board or a multilayer board having three or more layers having a through-hole structure as a core board as a conventional interlayer connection. Conventionally, photosensitive insulating resin is applied or laminated on one or both sides of the core substrate, and via holes for electrical interlayer connection are formed by photolithography,
Electroless plating (for example, chemical copper plating) is applied to the entire surface, and after making a circuit forming area by photolithography using a dry film, electroplating is performed to form a conventional via having a structure according to the shape of the via. Finally, wiring formation, wiring insulation, and interlayer conduction are realized by etching the electroless plating layer other than the circuit portion, and a multilayer wiring board is formed by repeating this process a plurality of times.

[0003] The conventional method by this conventional method
The formation of the via and the formation of the wiring layer will be briefly described below with reference to FIG. First, a wiring base material 610 having a first wiring portion 620 formed on one surface thereof is prepared (FIG. 6).
(A)) An insulating layer 630 of epoxy resin or the like is formed in a predetermined shape on the surface side on which the wiring is formed. (FIG. 6B) The insulating layer 630 is formed by a screen printing method, a curtain coating method, a laminating method, or the like. Next, the surface of the insulating layer 630 is treated with a permanganate chemical solution 640.
After the surface is roughened (FIG. 6C), a catalyst is applied, and the electroless plating layer 650 is disposed by electroless plating so as to cover the entire surface of the insulating layer 630. (FIG. 6
(D) As the electroless plating, the electroless nickel plating and the electroless copper plating are generally used as the base of the subsequent electrolytic plating and the power supply layer. It is formed to a thickness as small as possible. Next, on the electroless plating layer 650, according to the shape of the wiring portion to be formed,
A resist layer 660 having an opening of a predetermined shape is formed (FIG. 6E), and the provided electroless plating layer 650 is used as a power supply layer, the resist layer 660 is used as a plating resistance mask, and is formed on the electroless plating layer 650. Electroplating is performed to form an electroplating layer 670 to be a wiring portion. (FIG. 6 (f)) The electrolytic plating layer 670 is to be the second wiring portion, and usually a copper plating layer is used in terms of conductivity and cost.
Other plating layers, such as a gold plating layer, a silver plating layer, and a nickel plating layer, may be single layers, or a multilayer of these plating layers including a copper plating layer may be used. Next, after removing the resist layer 660 (FIG. 6G), an extra electroless plating layer 650 is soft-etched so as not to damage the wiring portion. (FIG. 6 (h)) Thus, the insulating layer layer 630 is formed on the first wiring portion of the wiring base 610 having the first wiring portion 620 provided on one surface thereof.
, A second wiring portion 675 (electrolytic plating layer 670 and electroless plating layer 650 thereunder) is formed. Note that soft etching refers to etching in a very short time, and in particular does not affect the wiring portion to be formed.

Further, when an external electrode portion made of a solder ball for connecting to an external circuit is provided, a flat wiring portion (also referred to as a terminal portion) separated from the via portion (connection portion 675A).
Formed. (FIG. 6 (i)) The external electrode portion made of a solder ball is formed by screen-printing a solder paste at a predetermined position and then performing reflow.

[0005] In this manner, a conventional via is formed along the shape of the via forming hole. However, the conventional via structure that conforms to the shape of the via hole may be affected by thermal stress due to unconnected disconnection or crack shape at the bottom of the via, depending on how the via hole is formed, electroless plating, and electroplating around the via hole. Disconnection occurs. In particular, via diameter reduction (50
(μm or less) and high aspect ratio (aspect ratio = 1), the throwing power of each plating solution is further deteriorated. Therefore, a structure that can secure the connection reliability of these plating solutions has been required. Further, in the conventional via structure formed in this way, it is necessary to draw out the terminal to a flat place different from the via part at the time of connection between wiring layers or chip connection, etc. Routing
Because of the complexity, it is disadvantageous for higher density.

[0006]

As described above, in the conventional wiring board having the conventional via structure, the conventional via has a problem in connection reliability and a further problem due to its shape. There is a problem that it is difficult to deal with densification. The present invention provides a wiring substrate having a via structure, which can solve the problem of connection reliability and can cope with further higher density, and a method of manufacturing the same. What you want to do. Further, the present invention provides a wiring board having a filling via, which can be easily manufactured using existing facilities for manufacturing a general printed wiring board, can secure connection reliability, and can cope with further densification, and a manufacturing method thereof. What you want to do. In particular, an object of the present invention is to provide a manufacturing method capable of manufacturing such a wiring board by using an inexpensive dry film resist even in the case of forming an ultrafine pattern of L / S = 30/30 μm or less.

[0007]

According to the present invention, there is provided a wiring substrate having a wiring substrate having a wiring portion formed on a surface as a base substrate, and a wiring layer having one layer formed on the surface of the base substrate having the wiring portion formed thereon. A wiring board formed by laminating at least one wiring layer via an insulating layer every time, wherein a via formed in the insulating layer is embedded in a conductive layer. . In the above, the conductor layer is formed by plating. Further, in the above, the base substrate is a wiring substrate in which wiring portions are formed on both surfaces thereof and through holes for connecting the wiring portions on both surfaces are provided. This is used as a core substrate, and the wiring portion of the base substrate is formed. The wiring board is further formed by laminating one or more wiring layers on each of the two surfaces with an insulating layer interposed between the wiring layers.
Further, in the above, a structure in which vias embedded in a conductor layer formed in the other insulating layer are stacked immediately above vias embedded in a conductor layer formed in one of the adjacent insulating layers. It has a certain via-on-via structure. Further, in the above, a via formed in the outermost insulating layer and embedded in the conductor layer is used as a terminal portion (pad).

According to the method of manufacturing a wiring board of the present invention, a wiring board having a wiring portion formed on a surface is used as a base substrate, and the wiring board is further insulated for each wiring layer on the surface of the base substrate on which the wiring portion is formed. Manufacture of a wiring board for manufacturing a wiring board formed by laminating one or more wiring layers via layers and in which a via formed in each insulating layer is embedded with a conductor layer A method for sequentially forming (a) an insulating layer on a surface of a substrate on which a wiring is to be formed on which a wiring is to be formed, and (b) an insulating layer forming step of: Irradiating the via formation region with a short-wavelength laser to open the insulating layer, forming a via hole forming step for forming a via forming hole, and (c) covering the entire surface of the insulating layer. An electroless plating step of providing an electroless plating layer by electroless plating; On the solution plating layer, matching the wiring including the via portion forming a first resist layer forming step of forming a first resist layer having an opening of a predetermined shape,
(E) a first electrolytic plating step of performing electrolytic plating on the electroless plating layer using the electroless plating layer provided as a plating mask with the first resist layer as a power supply layer;
(F) a second resist layer forming step of forming a second resist layer in which only the conductive layer forming region to be filled in the via portion to be formed is opened after peeling and removing the first resist layer;
(G) a second plating step in which electrolytic plating is performed using the second resist layer as a plating mask and the electroless plating layer as a power supply layer, and the inside of the via is filled with a conductive layer made of the electrolytic plating layer; h) After the second resist layer is peeled and removed, etching is performed, and an etching step of etching and removing the exposed extra electroless plating layer is performed so as not to damage the wiring portion including the via portion. ) To (h) are repeated according to the number of wiring layers to be laminated.

[0009]

The wiring board according to the present invention is a wiring board having a via structure by being configured as described above. The wiring board can solve the problem of connection reliability and can cope with further densification. A substrate can be provided. Furthermore,
It is possible to provide a wiring board having a filling via, which can be easily manufactured using existing facilities for manufacturing a general printed wiring board, can secure connection reliability, and can cope with higher density. Specifically, a wiring board having a wiring portion formed on the surface is used as a base substrate, and a wiring layer is further formed on the surface of the base substrate, on which the wiring portion is formed, via an insulating layer for each wiring layer. A wiring board formed by laminating one or more layers, wherein the via formed in the insulating layer is embedded with a conductive layer, and further, the conductive layer is formed by plating; Have achieved.

The wiring board having a wiring portion formed on the surface is not particularly limited. The wiring board is formed with wiring portions on both sides of a base substrate and provided with through holes for connecting the wiring portions on both surfaces. Wiring board. The via in the wiring board of the present invention is a filled via in which a conductive layer is filled in the via, directly above the via embedded with the conductive layer formed in one of the adjacent insulating layers, and in the other insulating layer. A via-on-via structure in which vias embedded in the formed conductor layer are stacked can be provided, and the degree of freedom of wiring can be increased as compared with the case of a conventional via. Also, vias (filled vias) formed in the outermost insulating layer and embedded in the conductor layer can be used as terminal portions (pads) (this is also referred to as a pad-on-via structure). As described above, there is no need to form a terminal portion in another place, wiring can be easily routed, and high density can be accommodated.

The method of manufacturing a wiring board according to the present invention, which is configured as described above, is a wiring board having a via structure, and can solve the problem of connection reliability, and can further increase the density. It is an object of the present invention to provide a method of manufacturing a wiring board for manufacturing a compatible wiring board. Furthermore, it is possible to provide a method of manufacturing a wiring board having a filling via, which can be easily manufactured using existing facilities for manufacturing a general printed wiring board, can secure connection reliability, and can respond to further densification. And In particular, even in the case of forming an ultrafine pattern with L / S = 30/30 μm or less, it is possible to manufacture such a wiring board by using an inexpensive dry film resist.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to the drawings. FIG. 1A is a sectional view of a characteristic portion of a first example of an embodiment of a wiring board according to the present invention, and FIG. 1B is a characteristic of a second example of an embodiment of the wiring substrate of the present invention. FIG. 1C is a cross-sectional view of a characteristic portion of a modification of the second example, and FIG. 2 is a part of a process of an example of an embodiment of a method of manufacturing a wiring board according to the present invention. FIG. 3 is a process diagram showing a process subsequent to FIG. 2, and FIG. 4 is a process diagram showing a part of a process of an example of an embodiment of a method of manufacturing a wiring board according to the present invention. FIG. 5 is a process diagram showing a process following FIG. still,
1 to 5, the wiring portion and the via portion appear to be formed only on one surface of the base substrate 110, but the characteristic portion of the manufactured wiring board or the characteristic portion of the manufactured wiring board. Only the state at the position is shown. Actually, wiring portions and via portions are formed or formed on both surfaces of the base substrate 110. 1 to 5,
110 is a base material, 120 is a wiring portion, 125 is a through hole, 130 is an insulating layer, 135 is a hole (for forming a via), 140 is an electroless plating layer, 150 and 155 are a resist layer, and 160 is an electrolytic plating layer. 165 is a land, 170
Is an electrolytic plating layer (for filling), 180 is a wiring portion, 185
Is a via portion (also called a filled via portion), 230 is an insulating layer, 2
35 and 235A are holes for forming vias; 240 is an electroless plating layer; 250 and 255 are resist layers; 260 is an electrolytic plating layer; 270 is an electrolytic plating layer (for filling); 287 is a via-on-via (via portion), and 290 is a solder resist.

An embodiment of a wiring board according to the present invention will be described. First, a first example of an embodiment of a wiring board of the present invention will be described with reference to FIG. In the wiring board of the first example, a wiring board of a structure in which wiring layers 120 are provided on both surfaces of a base substrate 110 and wiring portions of both surfaces are connected by through holes 125 is used as a core substrate, and wiring of the base substrate is performed. The insulating layer 130 is further provided on both sides on which the portions are formed.
A wiring board formed by laminating one wiring layer between the wirings (wiring 160 and wiring 1) formed on the insulating layer 130.
The via 185 connecting the substrate 20) is embedded with an electroplating layer (a conductor layer) 170 formed by plating.

As a double-sided wiring substrate serving as a core substrate, the base substrate 110 is made of a flexible film-shaped material such as an acrylic resin, an epoxy resin, or a polyimide, or a base material for a printed circuit board such as a glass epoxy or a BT resin. In addition, those having a wiring layer formed on both sides thereof can be applied, and a double-sided wiring board formed by a conventional method can be applied. Examples of the insulating layer 130 include an epoxy-based material, and a material made of polyimide is preferable in terms of insulation and stability. There is no limitation. Examples of the electroless plating layer 140 include an electroless nickel plating layer and an electroless copper plating layer. As the electrolytic plating layer 160, which is to be a wiring portion, usually a copper plating layer is used in terms of conductivity and cost, but other plating layers such as a gold plating layer, a silver plating layer, and a nickel plating layer, Or, including the copper plating layer,
These plating layers may be formed in multiple layers. As the electrolytic plating layer 170, the same as the electrolytic plating layer 160 can be used.

Next, a second embodiment of the wiring board according to the present invention will be described with reference to FIG. The wiring board of the second example is a wiring board formed by laminating one wiring layer on both sides of the core board using the wiring board of the first example and further interposing an insulating layer 230 therebetween. The via holes 285 and 287 formed in the insulating layer 230 are filled with an electroplated layer (conductor layer) 270 formed by plating. The via 287 is further provided on the via 185 provided in the insulating layer 130 shown in FIG.
Stacked vias (fill-type vias)
This is a via-on-via structure. The insulating layer 230, the electroless plating layer 240, and the electrolytic plating layers 260 and 270 are respectively the insulating layer 130 and the electroless plating layer 140 of the first example.
The same material as the electrolytic plating layers 160 and 170 can be applied.

As a modification of the second example, a second wiring board is used, and as shown in FIG.
The outermost surface of the substrate 87 is a terminal surface, an opening is formed so as to expose only the terminal surface, and both surfaces of the substrate of the second example are covered with solder resist. Further, when used as a substrate for a semiconductor device, a structure may be employed in which external electrodes made of solder balls are provided on terminal surfaces. Another, second
As a modification of the example shown in FIG. 1, a via 185 shown in FIG.
There is also a via-on-via structure in which a via 285 as shown in FIG. Similarly, as a modified example of the first example, the first wiring board is used, and the via portion 185 is used.
The outermost surface of the substrate is a terminal surface, an opening is formed so that only the terminal surface is exposed, and both surface portions of the substrate of the first example are covered with solder resist. One having a structure provided with an electrode is exemplified.

Next, an embodiment of a method of manufacturing a wiring board according to the present invention will be described. First, one example of a method of manufacturing a wiring board according to the first example of the embodiment shown in FIG.
It will be described based on. A wiring board is prepared by providing wiring on both sides of the base substrate 110 and providing through holes 125 for connecting both-side wiring (FIG. 2A). A layer 130 is formed. (FIG. 2 (b)) A flexible film-shaped material such as acrylic resin, epoxy resin, polyimide, glass epoxy, or BT
A base material for a printed circuit board such as resin is used as a base material 1
10, and a wiring board having a wiring layer formed on both surfaces thereof can be applied. The insulating layer 130 is formed by a lamination method using an insulating film, screen printing, curtain coating, or the like. As the insulating layer 130, a layer made of polyimide is preferable in terms of insulation and stability,
It is not limited to this. Next, in the via formation region, UV
Irradiating a short wavelength laser such as a YAG laser to the insulating layer 1
A through hole (hole 135) is opened in 30. (FIG. 2 (c)) Next, a catalyst is applied to the entire surface on both sides to form an electroless plating layer as a base layer and a power supply layer for the subsequent electrolytic plating. (FIG. 2 (d)) As the electroless plating, electroless copper plating and electroless nickel plating are generally used. The electroless plating is formed to a thickness that can function as an underlayer and a power supply layer. Note that, if necessary, prior to the electroless plating, a surface roughening process for roughening the surface of the insulating layer 130 is performed. Examples of the surface roughening treatment include a method using a chemical solution treatment and a wet blast method in which water containing abrasive grains is blown.

Next, after a resist layer 150 is provided on the entire surface of both sides (FIG. 2E), exposure and development are performed using a pattern plate having a predetermined shape in accordance with the wiring shape to be formed, and an opening is formed in a predetermined shape. Is formed. (Figure 2
(F) The resist layer 150 is not particularly limited as long as it has plating resistance and good processability. From the viewpoint of workability, a dry film resist is preferable.

Next, using the electroless plating layer as a power supply layer,
Electroplating is performed, and a conventional via having a shape along the hole 135 and a wiring are formed by the electrolytic plating layer. (FIG. 2 (g)) The electrolytic plating layer 160 is to be a wiring portion, and is usually used by forming a copper plating layer by electrolytic copper plating in terms of conductivity and cost. Depending on the case, other plating layer single layer, such as gold plating layer, silver plating layer, nickel plating layer, or copper plating layer, these plating layers are multilayered,
Electroplating may be formed. Next, the resist layer 150
After stripping and removing (FIG. 2 (h)), both sides are again covered with a resist 155 to partially perform electrolytic plating for filling a hole of a via portion (conventional via) with a conductive layer (FIG. i)) Using a predetermined pattern plate, exposing and developing to open only a predetermined region. (FIG. 3 (j)) Similarly to the resist layer 150, the resist layer 155 is not particularly limited as long as it has plating resistance and good processability. From the viewpoint of workability, a dry film resist is preferable. Next, electrolytic plating is performed to form a resist layer 15
The electrolytic plating layer 170 is embedded in the via portion exposed from the opening of No. 5. (FIG. 3 (k)) Also here, electrolytic copper plating is usually applied as electrolytic plating. The inside of the conventional via (hole 13)
The conductive layer (electrolytic plating layer 170) formed in a post shape on the land 165 by filling 5) is also referred to as a filled via post or simply a post.

Next, after the resist layer 155 is peeled off (FIG. 3 (l)), the exposed electroless plating layer 140 is removed.
Is removed by etching without damaging the wiring section 180 and the via section 185. (FIG. 3 (m)) Such etching is also called soft etching or flash etching. In this way, FIG.
The wiring board of the first example shown in FIG.

Next, FIGS. 4 and 5 show an example of a method of manufacturing the wiring board of the second example shown in FIG. 1B using the wiring board of the first example shown in FIG. It will be described based on the following. First, a wiring board of the first example shown in FIG.
(A)) Then, in the same manner as in the method of manufacturing the wiring board of the first example shown in FIGS. 2 and 3, the via forming portion and the wiring forming portion (not shown) are opened, and the insulating layer 230 is formed. After forming on both surfaces (FIG. 4B), electroless plating is performed on the entire surface to form an electroless plating layer 240. (FIG. 4C) Next, in the same manner as in the manufacturing method shown in FIGS. 2 and 3, the via forming portion is opened, a resist layer 250 is formed on both surfaces, electrolytic plating is performed, and the hole of the opening is formed. A conventional via having a shape along the 235 shape and a wiring are formed. (FIG. 4D) Here, the region for forming the via-on-via shown in FIG. 1B is not opened, but may be opened in some cases.

Next, after removing and removing the resist 250 (FIG. 4E), a via portion (conventional via) is formed.
In order to partially fill the hole with a conductive layer and partially perform electrolytic plating for forming a via-on-via shown in FIG. 1B, both surfaces are again covered with a resist 255, and a predetermined pattern plate is used. Exposure and development are performed to open only a predetermined area. (FIG. 4F) Further, electrolytic plating is performed to bury the electrolytic plating layer 270 in the via portion exposed from the opening of the resist layer 255 (FIG. 5G), and then the resist 255 is peeled off. 5
(H)) The exposed electroless plating layer is removed by etching without damaging the wiring portions (not shown) and the via portions 185 and 185A. (FIG. 5 (i)) Both steps can be performed in the same manner as the manufacturing steps of FIGS. Thus, the wiring board of the second example shown in FIG. 1B is manufactured.

Further, an opening is provided by plate making so that the entire surface of the wiring board of the second example is covered with a solder resist and only the terminal surface is exposed (FIG. 5 (j)). The wiring board shown is formed. The wiring board shown in FIG. 1C has a pad-on-via structure in which a terminal portion (pad) is provided on a via.

[0024]

(Embodiment 1) Embodiment 1 is an example in which the wiring board of the first example shown in FIG. 1A is manufactured by the steps shown in FIGS. This will be described with reference to FIGS. First, the wiring layers 12 are formed on both sides of the base substrate 110 as follows.
0, and a base substrate having a structure in which wiring portions on both surfaces were connected by through holes 125 was produced, and this was used as a core substrate. (FIG. 2 (a))

A base substrate (double-sided wiring substrate) was manufactured according to the process shown in FIG. Base material 71 made of BT resin
Penetration for forming a through-hole of 0.3 mmφ by drilling on a 0.3 mm-thick laminated plate (BT resin CCL-HL832, manufactured by Mitsubishi Gas Chemical Co., Ltd.) having 18 μm-thick copper foil 720 laminated on both sides After forming a hole (also referred to as a through-hole prepared hole) 730 (FIG. 7B), the inside is washed by immersing in a permanganic acid roughening treatment solution (manufactured by Shipley),
An electroless copper plating layer 740 is formed in a thickness of 0.3 μm by a manufacturing method according to Shipley Co., Ltd. to form a through-hole (a prepared through-hole) 730.
The inside was made conductive. (FIG. 7 (c)) Next, using the electroless copper plating layer 740 as a power supply layer, in a copper sulfate plating bath having the following composition at a current density of 2 A / dm ² ,
The energization was performed for 5 minutes to form an electrolytic plating layer 750 made of a copper plating film having a thickness of 20 μm. (60 ppm as C1) (Fig. 7 (d)) <a copper sulfate plating bath composition (bath temperature _{25 ℃)> CuS0 4 · 5H} 2 O 75g / l H 2 S0 4 180g / l HCl 0.15ml / l Cu-Board HA MU 10 ml / l (manufactured by Ebara Ujilight Co., Ltd.) Then, after pickling and drying, a commercially available dry film resist (Sanfu Auto AQ255, Asahi Kasei Corp.)
8) is laminated, and the circuit wiring (land size length L
Using a photomask for forming a digital circuit having a size of 1.5 mm × width W of 0.5 mm and a wiring pitch of 1 mm, exposure was performed under the following conditions, development, washing with water, and drying to form a resist layer 760 having a predetermined shape. (FIG. 7 (e)) <Exposure conditions> Contact exposure machine TN800CL manufactured by Ono Sokki Co., Ltd. Exposure amount: 80 mJ / cm ² Next, using resist layer 760 as an etching resistant mask, 45 Baume ferric chloride was used from both sides The unmasked portions were spray-etched to form wiring portions on both surfaces. (FIG. 7 (f)) The resist layer 760 was peeled off with caustic soda, washed with water and dried to produce a base substrate provided with wiring 780 on both sides and through holes 785. (FIG. 7 (g))

An insulating layer 130 was formed on both sides of the base substrate thus manufactured under the following conditions.
(FIG. 2 (b)) After the surface of the wiring is roughened (etch bond CZ-8100 manufactured by Mec Co., Ltd.) in order to improve the adhesion, an epoxy-based insulating resin film (manufactured by Ajinomoto Fine Techno Co., Ltd., A
BF-45SH) was laminated under pressure using a vacuum laminator (MLVP500, manufactured by Meiki Seisakusho Co., Ltd.) under the following conditions. Layer 130
Was formed. <Vacuum lamination conditions> Warm skin 90 ° C Vacuum degree 0.3 mmHg Pressure at pressurization 2.0 kg / cm ² Vacuum evacuation time 30 sec Pressurization 30 sec

Next, in the via formation region of the insulating layer 130,
The insulating layer 130 was irradiated with UV-YAG laser to form a through hole (hole 135). (FIG. 2 (c)) For connection of the first layer and the second layer having a diameter (top diameter) of 0.05 mm using a UV-YAGLAZER drill device (Model 5100, manufactured by ESI) under the following processing conditions. Via formation holes (also referred to as pilot holes) 135 were formed. <LASER processing conditions> HOLE size 50 μm power 300 mW Drill type trepane Z offset 0.5 mm Rep rate 11.111 kHz

Next, after the base material is treated with permanganate to roughen the resin on the surface of the insulating layer 130 and the surface of the via-forming hole 135 (also referred to as a hole), the electroless plating layer is formed by electroless copper plating. 140 was formed into a film having a thickness of 0.3 μm to make it conductive. (FIG. 2 (d)) <Electroless copper plating conditions> Conditioner 5min Soft etching 1min Pickling 0.5min Pre-dip 1min Catalyst 5min Accelerator 7min Electroless copper unplating 20min

Next, after annealing at 120 ° C. for 1 hour, pickling, and drying, a dry film resist (Sunfort AQ2558, manufactured by Asahi Kasei Corporation) was laminated on both sides (FIG. 2E), and a base substrate was formed. As in the case of the wiring formation, exposure was performed using a photomask for forming circuit wirings, development, washing with water, and drying were performed to form a resist layer 150 having a predetermined shape. (FIG. 2 (f))

After being pickled as a pretreatment for plating, a current was applied for 25 minutes at a current density of 4 A / dm ² in a copper sulfate plating bath, and 20 μm was applied to circuit wiring portions and vias (including lands).
Thick copper plating was selectively formed to form a wiring portion. (FIG. 2 (g)) At this stage, a conventional via has been formed.

Then, the resist layer 150 was peeled off with caustic soda, pickled, washed with water and dried (FIG. 2 (h)).
Further, a dry film resist is laminated on both sides (FIG. 2 (i)), and a predetermined pattern plate (photomask)
Exposure, development, washing with water, and drying were carried out to form a resist layer 155 in which only the upper peripheral portion of the conventional via was selectively opened. (FIG. 3 (j))

Then, after pickling as a plating pretreatment,
Using the resist layer 155 as a plating mask, a current is applied at a current density of 4 A / dm 2 for 35 minutes in a copper sulfate plating bath to fill the inside of the conventional via (hole 135) and further increase the thickness by 30 μm on the land 165. The copper plating layer 170 was selectively formed in a post shape. (FIG. 3 (k)) As described above, the inside of the conventional via (hole 135) is filled, and the conductive layer (electrolytic plating layer 170) formed in a post shape on the land 165 is filled. Also called a via post, or simply a post.

Next, the resist layer 155 is peeled off with caustic soda (FIG. 3 (l)), and the entire surface is spray-etched with a dilute ferric chloride solution to remove the unnecessary electroless plating layer 140 other than the wiring portion. Then, a wiring board in which a wiring portion and a via portion were formed was manufactured. (FIG. 3 (m)) Thus, the wiring board shown in FIG. 1 (a) was produced.

Example 2 In Example 2, the wiring substrate shown in FIG. 1 manufactured in Example 1 was used, and the wiring substrate shown in FIG. It was produced by As in the case of the first embodiment, the green layer 230 is laminated under vacuum pressure on the wiring board (FIG. 4A) obtained in the first embodiment, and the insulating layer 230 is filled to form a via-on-via. In the upper region of the via post and the newly provided via portion region, a hole (a lower hole) for forming a via is formed by opening with a UV-YAG laser (FIG. 4B), and then the green layer 2 is formed.
The surface of No. 30 and the surface of the via-forming hole (prepared hole) are treated with permanganic acid, roughened, and electroless plated layer 250 is formed to a thickness of 0.3 μm by electroless copper plating. did. (FIG. 4 (c)) Next, after annealing, pickling and drying at 120 ° C. for 1 hour, a dry film resist was laminated on both sides in the same manner as in Example 1 to obtain a predetermined wiring forming pattern. Exposure using a plate (photomask), development, washing with water,
After drying, only the new via formation region was opened to form a resist layer 250. (FIG. 4 (d))

Next, in the same manner as in Example 1, pickling was performed as a plating pretreatment, and the current density was changed to 4 A in a copper sulfate plating bath.
/ Dm ² for 25 minutes to selectively form a 20 μm thick copper plating on the wiring portion including the via portion. (FIG. 4
(E)) Next, after the resist 250 is peeled off with caustic soda, pickled, washed with water, and dried, a dry film resist is further laminated on both sides thereof, and exposed using a predetermined pattern plate (photomask). After developing, washing and drying,
A resist layer 25 in which only a portion where a filled via post is to be formed is selectively opened in an upper region of a filled via post for forming a via-on via and a newly provided via portion region.
5 was formed. (FIG. 4 (f)) Next, after pickling as pretreatment for plating, the current density was 4 A / dm ^{2 in a} copper sulfate plating bath in the same manner as in Example 1.
For 10 minutes to form a filled via post made of copper plating with a thickness of 10 μm (FIG. 4 (g)). Further, the resist 255 is peeled off with caustic soda (FIG. 4 (h)), and the entire surface is diluted with chlorine. Spray etching was performed with a ferric liquid to remove unnecessary portions of the electroless plating layer 240 made of an electroless copper plating layer other than the wiring portion, thereby forming vias 285 and 287 of the present invention. Reference numeral 287 denotes a structure in which vias embedded in the conductor layer (plated layer) formed in the insulating layer 230 are stacked immediately above vias embedded in the conductor layer (plated layer) formed in the insulating layer 130. Beer on beer. Then
The surface wiring portion including the via surface was trimmed. Thus, the wiring substrate shown in FIG. 1B was manufactured.

Example 3 In Example 3, the wiring board shown in FIG. 1B obtained in Example 2 was used, and only the terminal surface was opened and covered with a solder resist. Was obtained. Under the conditions shown below, the wiring board shown in FIG. 1B was covered with a solder resist with only the terminal surface portion opened to obtain the wiring board shown in FIG. 1C. (FIG. 5 (j)) A solder resist (AUS9 manufactured by Taiyo Ink Mfg. Co., Ltd.) was applied to the wiring board shown in FIG. 1 (b) obtained in Example 2 by a screen printing machine (MT manufactured by Microtech Co., Ltd., MT). -15
0), and a solder resist film was formed under the following conditions. <Solder resist film formation conditions> After applying the first surface <First time> After applying hot air circulating oven at 80 ° C for 15 minutes Second applying after <First time> Applying hot air circulating oven at 80 ° C for 25 minutes First applying <Second time> ＞ After hot air circulation type oven 80 ℃, 30 minutes

Next, exposure is performed using a pattern plate (photomask) having a predetermined shape, development with a sodium carbonate solution, washing with water, post-curing at 150 ° C. for 60 minutes, and 1 hour.
Exposure was performed at 00 mJ / cm 2 to cure the solder resist coating, and only the terminal surface was opened and covered with the solder resist to obtain a wiring board shown in FIG. 1C. (FIG. 5
(J) <Exposure conditions> Contact exposure machine TN800CL manufactured by Ono Sokki Co., Ltd. Exposure amount 500 mJ / cm ²

The tests shown in Table 1 were performed on a part (test piece) of the wiring board obtained in Example 3 to examine the connection reliability and the change in appearance of the test.
The rate of change in conduction resistance was 10% or less, and there was no abnormality in appearance and via portions, and both were good.

[0039]

[Table 1]

[0040]

As described above, the present invention relates to a wiring board having a via structure, which can solve the problem of connection reliability and can cope with further densification, and its manufacture. The method can be provided. Further, the present invention provides a wiring board having a filling via, which can be easily manufactured using existing facilities for manufacturing a general printed wiring board, can secure connection reliability, and can cope with further densification, and a manufacturing method thereof. Was made possible. More specifically, in the multilayer wiring board according to the present invention, not only the via connection reliability is clearly improved as compared with the conventional via structure, but also via-on vias and pad-on-vias in which terminal portions (pads) are provided on vias are realized. There is no need to pull out the flip-chip connection pads, and the plane space for forming the wiring can be widened. As a result, it has become possible to provide a multilayer wiring board that can respond to high density.

[Brief description of the drawings]

FIG. 1A is a sectional view of a characteristic portion of a first example of an embodiment of a wiring board of the present invention, and FIG. 1B is a second view of a second embodiment of the wiring board of the present invention. FIG. 1C is a cross-sectional view of a characteristic portion of a modification of the second example.

FIG. 2 shows a first embodiment of a method of manufacturing a wiring board according to the present invention;
Process diagram showing a part of the process of the example

FIG. 3 is a process drawing showing a step following FIG. 2;

FIG. 4 shows a first embodiment of a method of manufacturing a wiring board according to the present invention;
Process diagram showing a part of the process of the example

FIG. 5 is a process chart showing a step following FIG. 4;

FIG. 6 is a process cross-sectional view illustrating a manufacturing process of a base substrate.

FIG. 7 is a process sectional view showing the formation of a conventional via and the formation of a wiring layer by a conventional method.

[Explanation of symbols]

 Reference Signs List 110 base substrate 120 wiring section 125 through hole 130 insulating layer 135 hole (for forming via) 140 electroless plating layer 150, 155 resist layer 160 electrolytic plating layer 170 (for filling) electrolytic plating layer 180 wiring section 185 via section 230 (insulating layer 235, 235A for via formation) Hole 240 Electroless plating layer 250, 255 Resist layer 260 Electroplating layer 270 Electroplating layer (for filling) 285 Via section (also called filling via section) 287) Via-on-via (via) 290 Solder resist

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (6)

[Claims] A wiring substrate having a wiring portion formed on a surface thereof is used as a base substrate, and a wiring layer is further formed on the surface of the base substrate on which the wiring portion is formed, further via an insulating layer for each wiring layer. 1
A wiring board formed by laminating at least two layers, wherein a via formed in the insulating layer is embedded in a conductor layer. 2. The wiring board according to claim 1, wherein the conductive layer is formed by plating. 3. The base substrate according to claim 1, wherein the base substrate has a wiring portion formed on both surfaces thereof, and a through-hole for connecting the wiring portions on both surfaces is provided. On both sides of the substrate on which the wiring portion is formed, further via an insulating layer for each wiring layer,
A wiring board, which is a wiring board formed by laminating one or more wiring layers. 4. The semiconductor device according to claim 1, wherein the conductive layer formed on the other insulating layer is buried directly above the via buried with the conductive layer formed on one of the adjacent insulating layers. A wiring board having a via-on-via structure in which vias are stacked. 5. The wiring board according to claim 1, wherein a via formed in the outermost insulating layer and embedded in the conductor layer is used as a terminal portion (pad). 6. A wiring substrate having a wiring portion formed on a surface thereof is used as a base substrate, and a wiring layer is further formed on the surface of the base substrate on which the wiring portion is formed, further via an insulating layer for each wiring layer. 1
A method for manufacturing a wiring board in which a wiring board formed by laminating layers or more, and a via formed in each insulating layer is embedded with a conductive layer, and
(A) an insulating layer forming step of laminating and forming an insulating layer on a surface of a substrate on which a wiring is to be formed, on a surface on which the wiring is to be formed;
A via-hole forming step of irradiating a via-forming region of the laminated insulating layer with a short-wavelength laser to open the insulating layer and form a hole for forming a via; An electroless plating step of arranging an electroless plating layer by electroless plating so as to cover the entire surface, and (d) a predetermined shape adapted to the wiring including a via portion to be formed on the electroless plating layer. A first resist layer forming step of forming a first resist layer having an opening of (e), and (e) using an electroless plating layer provided with the first resist layer as a plating mask as a power supply layer,
A first electrolytic plating step in which electrolytic plating is performed on the electroless plating layer, and (f) after peeling and removing the first resist layer, only the filled conductive layer forming region of the via portion to be formed is opened. A second resist layer forming step of forming a second resist layer, and (g) performing electrolytic plating using the second resist layer as a plating mask, the electroless plating layer as a power supply layer, and electrolyzing the inside of the via. A second plating step of filling with a conductive layer composed of a plating layer; and (h) etching after removing and removing the second resist layer so as not to damage the wiring portion including the via portion. A series of steps (a) to (c) in which an etching step of etching and removing the electroless plating layer is performed.
A method for manufacturing a wiring board, wherein the step (h) is repeated according to the number of wiring layers to be laminated.