JP2001283600A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an EEPROM to which power consumption during standby is reduced even if only a (n) channel MOS transistor a threshold value of which is low as Vpp system Tr. is used, and power source voltage is reduced, and a manufacturing cost is reduced. SOLUTION: An EEPROM is provided with a memory cell array 1 in which memory cells having FETMOS structure and being electrically rewritable are arranged in a matrix state on a semiconductor substrate, an erasion mechanism applying an erasing voltage to a memory cell and performing erasion, a write-in mechanism applying write-in voltage to a memory cell and performing write-in, and a block selecting circuit 7 selecting a memory cell block consisting of plural memory cell groups. MOS transistors to which erasion and write-in voltage are applied in a circuit constituting erasion and write-in mechanism are in a slight inversion state or a complete inversion state under the condition that substrate bias voltage, gate voltage and source voltage are all 0 V, and all the block selecting circuits are in block selection state during standby.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, an electrically rewritable nonvolatile semiconductor memory device (EEPROM), and an EEPROM for writing / erasing a memory cell by a tunnel current.
Regarding OM.

[0002]

2. Description of the Related Art As one type of EEPROM, a NAND cell type EEPROM capable of high integration is known. In this method, a plurality of memory cells are connected in series in such a manner that their sources and drains are shared between adjacent ones, and connected to a bit line as one unit. The memory cell usually has an FETMOS structure in which a charge storage layer (floating gate) and a control gate are stacked. The memory cell array has p
It is integrally formed in a mold substrate or a p-type well. The drain side of the NAND cell is connected to a bit line via a selection gate, and the source side is also connected to a common source line via a selection gate. The control gates of the memory cells are arranged continuously in the row direction to form word lines.

The operation of this NAND cell type EEPROM is as follows. Data writing is performed sequentially from the memory cell located farthest from the bit line. A high voltage VppW (= about 18 V) is applied to the control gate of the selected memory cell, and the intermediate voltage Vpp is applied to the control gate and the drain-side select gate of the memory cell on the bit line side.
m10 (= about 10 V) is applied, and 0 V or intermediate voltage Vm8 (= about 8 V) is applied to the bit line according to data.

When 0 V is applied to the bit line, the potential is transferred to the drain of the selected memory cell, and electrons are injected into the charge storage layer. As a result, the threshold value of the selected memory cell shifts in the positive direction. This state is set to, for example, “0”. When Vm8 is applied to the bit line, electron injection does not occur effectively, so the threshold value does not change,
Stay negative. This state is "1" in the erase state. Data writing is performed simultaneously on the memory cells sharing the control gate.

Data erasure is performed simultaneously for all memory cells in the selected NAND cell in block units. That is, all control gates in the selected NAND cell block are set to 0V, and the p-type well is set to 20V.
At this time, the selection gate, bit line, and source line are also set to 20 V with respect to the high voltage applied to the p-type well. As a result, in all the memory cells in the selected NAND cell block, electrons in the charge storage layer are emitted to the p-type well, and the threshold value shifts in the negative direction. All control gates of the memory cells in the non-erased NAND cell block are set to 20V. The high voltage required for writing and erasing is internally generated by a booster circuit.

In data reading, the control gate of the selected memory cell is set to 0 V, the control gates of the other memory cells and the selection gate are set to the power supply potential Vcc (for example, 3 V), and whether or not a current flows in the selected memory cell is determined. This is performed by detecting For this reason, the threshold value of the memory cell after writing must be lower than Vcc.

In such a NAND cell type EEPROM, in order to handle a wide range of voltages from 0 V to Vpp (up to 20 V), for example, a transistor (hereinafter referred to as a Vm Tr. 0V)
A high-withstand-voltage transistor (hereinafter referred to as a Vpp-type Tr.) That handles voltages in the range of up to Vpp is required. This is V
A circuit to which only a voltage of 10 m or less is applied is a Vm-system Tr. And the circuit area is suppressed, and only the transistor to which Vpp is applied is a Vpp Tr.
This is because

However, this type of apparatus has the following problems. That is, Vpp Tr. When each of n-channel and p-channel MOS transistors is used, there is a problem that the types of transistors increase and the manufacturing cost increases. In addition, Vpp Tr. For example, when a circuit is formed only with n-channel MOS transistors, there has been a problem that the power supply voltage cannot be reduced due to a decrease in voltage transfer efficiency due to the threshold value of the transistor.
Furthermore, Vpp Tr. For example, if a circuit is configured with an n-channel MOS transistor having a low threshold value, the current consumption during standby increases due to the leakage current of the transistor, or the high voltage Vpp that should be boosted from the power supply voltage cannot be boosted. There was a problem.

Further, since the writing voltage and the erasing voltage are generated internally by a booster circuit, they are vulnerable to manufacturing variations.
There has been such a problem that the variation in the threshold value of the memory cell after writing must be within a predetermined range.

[0010]

As described above, the conventional N
In an AND cell type EEPROM, a Vpp Tr. As n
When each of the channel and p-channel MOS transistors is used, there is a problem that the types of transistors increase and the manufacturing cost increases. In addition, Vpp Tr. For example, when a circuit is constituted only by n-channel MOS transistors, there has been a problem that the power supply voltage cannot be reduced due to a reduction in voltage transfer efficiency due to the threshold voltage of the transistors. Furthermore, Vpp Tr. For example, if a circuit is configured with an n-channel MOS transistor having a low threshold value, the current consumption during standby increases due to the leakage current of the transistor, or the high voltage Vpp that should be boosted from the power supply voltage cannot be boosted. There was a problem. In addition, there are problems that the write voltage and the erase voltage are internally generated by a booster circuit, so that they are vulnerable to manufacturing variations, and that the threshold variations after writing of the memory cells must be within a predetermined range. Was.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a Vpp Tr. Therefore, even if the circuit is constituted only by n-channel MOS transistors having a low threshold value, the power consumption during standby can be reduced, and the high voltage Vpp can be sufficiently boosted. An object of the present invention is to provide a semiconductor memory device capable of reducing manufacturing cost and the like.

[0012]

SUMMARY OF THE INVENTION A NAND according to the present invention
The cell type EEPROM is a Vpp Tr. For example, only an n-channel MOS transistor having a low threshold value is used. From the standpoint of voltage transfer efficiency, a Vpp Tr. That transfers a high voltage for erasing and writing. Are all n-channel MOS transistors having a low threshold value, for example. In order to suppress the leak current, all the block selection circuits are set to the selected state during standby. In addition, Vpp Tr. A voltage transfer circuit in which two are connected in series;
A bias circuit connected to the connection portion and activated to apply a bias for suppressing leakage when voltage is not transferred constitutes a switching circuit, and this bias circuit is used during standby to reduce current consumption during standby. Is deactivated.

Further, a threshold distribution after writing is measured, a writing voltage is adjusted from a threshold value equal to or higher than a predetermined distribution frequency, and a threshold value separated from the threshold value by a predetermined value or more is determined. To rescue memory cells.

That is, according to the present invention (claims 1 and 2), electrically rewritable memory cells each having a charge storage layer and a control gate laminated on a semiconductor layer are arranged in a matrix. A memory cell array, erasing means for erasing data in the memory cell, writing means for writing data in the memory cell, voltage adjusting means for adjusting a writing voltage (or erasing voltage), In a nonvolatile semiconductor memory device provided with threshold value detecting means for measuring a threshold value, data is erased (or written) in a predetermined number or more of memory cells, and thereafter, the data is erased (or written). Writing (or erasing) is performed on the written memory cell, the threshold value of the written (or erased) memory cell is detected, and the threshold distribution is measured. And wherein the adjusting cloth power than the write voltage from the threshold (or erase voltage).

According to the present invention (claims 3 and 4), electrically rewritable memory cells each having a charge storage layer and a control gate laminated on a semiconductor layer are arranged in a matrix. A memory cell array, erasing means for erasing data of the memory cell, writing means for writing data to the memory cell, threshold value detecting means for measuring a threshold value of the memory cell, In a nonvolatile semiconductor memory device including a redundant memory cell for relieving a defective memory cell, data is erased (or written) in a predetermined number or more of memory cells, and then the erased (or written) memory is erased. The cell is written (or erased), the threshold value of the written (or erased) memory cell is detected, and the threshold distribution is measured. Characterized by repairing the memory cell having the above threshold apart predetermined value or more from the threshold.

In the present invention, the Vpp Tr. A low-cost, low-power-consumption, NAND-cell EEPROM that operates efficiently even at low power supply voltage by reducing leakage current despite using only n-channel MOS transistors having a low threshold value Can be realized.

Further, by adjusting the write voltage and relieving the memory cell in accordance with the original characteristics of the memory cell,
A highly reliable NAND cell type EEPROM can be realized.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a NAND cell type EEPROM according to the first embodiment of the present invention. Main bit line control circuits 2A, 2B for controlling bit lines for memory cell arrays 1A, 1B divided into two, respectively.
2B and sub-bit line control circuits 3A and 3B. The memory cell array 1 is provided with a data latch and sense amplifier 4 that operates as a sense amplifier during reading and as a write data latch circuit during writing. The main and sub bit line control circuits 2A, 2B, 3A,
3B and the data latch / sense amplifier 4 are controlled by a column control circuit 5.

The block selection circuits 7A and 7B for receiving the output of the block address buffer 8 and selecting a block, and the word line control circuits 6A and 6B for controlling the word lines of the selected block are provided to the memory cell arrays 1A and 1B. Each is provided. Block selection circuits 7A, 7B
And the word line control circuits 6A and 6B are controlled by a row control circuit 9.

In order to control a cell well in which the memory cell array 1 is formed and a source line of the memory cell, a cell well control circuit 10 and a cell source control circuit 1 are provided, respectively.
1 is provided.

Vpp (〜20) required for writing / erasing
V), Vm10 (〜１０10V), Vm8 (〜8V)
The Vpp booster circuit 12, the Vm10 booster circuit 13, and the Vm8 booster circuit 14 boost the voltage from the power supply voltage Vcc (for example, 3 V).

FIG. 2A shows an n-channel MOS transistor (hereinafter, HV n-ch Tr.) Qh used in the present embodiment and having a high withstand voltage structure to which a voltage Vpp is applied. FIG.
2 (b) and (c) show the static characteristics of this transistor. As shown in FIG. 2 (a), the source and the substrate are grounded and the gate when a voltage is applied to the drain so as to operate as a pentode. Drain current Id with voltage Vg as a parameter
Is shown. The threshold value Vt is defined as shown in FIG. The threshold value of this HV n-ch Tr. Qh is lower than that of the enhancement type transistor.
As shown in (c), even when the gate voltage Vg is 0 V, the gate voltage Vg is not cut off and is in a weak inversion state. Although the threshold value Vt may be negative, it is desirable that the threshold value Vt be positive and the gate voltage Vg be 0 V to be in a weak inversion state.

The substrate bias voltage may be applied as appropriate in accordance with the operation, but is preferably grounded.

FIG. 3A shows a switching circuit constituted by HV n-ch Tr. Qh. HV n-ch Tr. Q
h1 and Qh2 are connected at node N1, and both gate voltages are V1. The bias circuit 15 is connected to the node N1. Hereinafter, the substrate bias of the n-channel MOS transistor is 0 V unless otherwise specified.

The drain voltage Vin of the HV n-ch Tr.
When transferring to the source voltage Vout of the n-ch Tr. Qh2, the voltage V1 is set to Vin + Vt (sub = Vin) or more. Vt (su
b = Vsub) is the HV n-ch when the substrate bias is -Vsub.
This shows the threshold of Tr. At this time, the bias circuit 1
5 is in an inactive state, so as not to affect the node N1.

When the voltages Vin and Vout are electrically cut off, V1 is set to a sufficiently low voltage (for example, 0 V) and the node N
1 is applied with a predetermined sufficiently high voltage by the bias circuit 15 in an activated state. If the voltage Vin or Vout is a predetermined sufficiently high voltage, the HV n-ch Tr. Qh1 or Qh2
Is cut off, and the voltages Vin and Vout are electrically cut off. Also, while this switching circuit is on standby,
The bias circuit 15 is also deactivated.

FIG. 3B shows a more specific circuit of this switching circuit, and a specific operation example of this embodiment will be described. HV n-ch Tr. Qh1 and Qh2 are connected in series.
The bias circuit composed of n-ch Tr.
Connected to. The power supply Vbias of the bias circuit is, for example, a power supply voltage Vcc (up to 3 V). Voltage Vin is boosted potential Vpp
(Up to 20 V), and when this is transferred to Vout, the voltage V1 is set to Vpp + Vt (sub = Vpp) or more. Also,
The control voltage V2 of the bias circuit is set to, for example, 0V. If the HV n-ch Tr. Qh is in a cut-off state with the source and drain at Vcc, the substrate bias, and the gate at 0 V, the voltage Vin is transferred only to Vout.

When the control voltage V2 of the bias circuit is, for example, Vcc
However, due to the back bias effect, Vbi
It is sufficient that no charge is transferred to as.

When the voltage Vin is the boosted potential Vpp (up to 20 V) and the voltage Vout is electrically cut off, the voltage V1 is set to, for example, 0V. The voltage V2 is, for example, Vcc. If the voltage of the node N1 transferred by the HV n-ch Tr. Qh3 is Vn1, the source and drain are Vn1, the substrate bias and the gate are 0V, and if the HV n-ch Tr. The n-ch Tr. Qh1 is cut off, and the voltage Vpp input to Vin is electrically cut off from Vout.

For example, the NAND cell type EE of this embodiment
PROM is waiting (all circuits are waiting), FIG. 3 (b)
The switching circuit shown in FIG. 3 is also in a standby state when the voltage V1 is, for example, 0V. If the voltage Vout is 0 V, and the voltage V2 is, for example, Vcc, the voltage Vbias, for example, V
cc leaks to Vout. Therefore, while the switching circuit is on standby, the voltage V2 is set to 0 V, for example, and the bias circuit 15 is deactivated. This allows Vbias to Vout
Leakage current is significantly reduced. Standby Vin is Vcc
There is a leakage current from Vin to Vout because the voltage V2 is almost the same level.
It is much less than the leakage current from bias to Vout.

FIG. 3C shows a modification of the switching circuit. HV n-ch Tr. An enhancement type p-channel MOS transistor (hereinafter referred to as p-channel MOS transistor) between Qh3 and voltage Vbias.
ch Tr.) Qp1 is connected in series, and the bias circuit 15 is configured with the HV n-ch Tr. Qh3. This p-ch Tr. Does not have a high breakdown voltage structure. The gate voltage is V3. During standby, the voltage V3 is set to, for example, Vcc, and the voltage Vbias is changed to Vou.
Cut off leakage current to t. During non-standby (during activation), V3 is set to, for example, 0V. In this switching circuit, during standby, the voltage V2 may be, for example, Vcc.

The switching circuit shown in FIG. 3 is composed of HV n-ch Tr.
When transferring the high voltage Vpp applied to in, there are advantages such as the potential of the voltage V1 can be kept low and the withstand voltage of the gate insulating film can be lowered.

FIG. 4 shows a specific configuration of the memory cell array 1. Memory cells M1 to M16 are connected in series, and one end is connected to a depletion type selection transistor S1.
The other end is connected to a bit line BL via an enhancement type selection transistor S2, and the other end is connected to a common source line Vsource via a depletion type selection transistor S3 and an enhancement type selection transistor S4 to form a NAND cell unit NCU1.

The gate electrodes of the memory cells M1 to M16 are connected to control gates CG1 to CG16, respectively.
Shared by AND-type cell units. NAND adjacent to NAND cell unit NCU1 sharing control gate
The cell unit NCU2 differs in the type of the selection transistor S1. This is the same for the selection transistors S2 to S4. That is, the selection transistor S1 sharing one selection gate, for example, SGD1, is alternately provided with a depletion type and an enhancement type.

The NAND type cell units NCU1 and NCU2 which are alternately arranged share the bit line BL with one adjacent set. Further, a block is constituted by NAND type cell units sharing control gates CG1 to CG16 and selection gates SGD1, SGD2, SGS1, SGS2. The memory cell M and the selection transistor S are of an n-channel type, and this memory cell array has a dedicated p-type well C
Formed on -p-well.

FIG. 5 specifically shows the word line control circuit 6 and the block selection circuit 7 shown in FIG. 1 together with the memory cell array shown in FIG.

HV n-ch Tr. Qh20 to Qh24 to enhancement type n-channel MOS transistor (hereinafter referred to as n-ch T
r.) Qn4 forms a selection gate control circuit for controlling a selection gate, for example, SGD1. The n-ch Tr. Qn does not have a high breakdown voltage structure. The circuit composed of the HV n-ch Tr. Qh21 to Qh23 has the same configuration as the switching circuit composed of the HV n-ch Tr. Qh1 to Qh3 shown in FIG. HV n-ch Tr.
Qh25 forms a control gate control circuit for controlling a control gate, for example, CG1. 4 select gate control circuits and 1
The six control gate control circuits constitute a word line control circuit 6 for controlling a word line of one cell block.

Each word line control circuit 6 uses the output N2 of the block selection circuit 7 as a block selection signal to control the control gates SGD1, SGD2, SGS1, and SGS1 of the selected block.
The common voltages VSGD1, VSGD2, VSGS1, VSGS common to each block are supplied to the SGS2 and the control gates CG1 to CG16.
2 and the voltages VCG1 to VCG16 are selectively transferred and applied.

The block selection circuit 7 is roughly composed of two circuits. One is p-ch Tr. Qp2-5, n-ch Tr.
Qn1-3, fuse F1, inverters I1, I2, NO
This is a block address decoder composed of R gates G1 and G2. When the fuse F is blown, or when at least one of the block address signals RA, RB and RC is "L", the decoder activation inversion signal RDEN
When BB is "L", the output N of the block address decoder
3 becomes "L" and the block is not selected. At this time, the sub-decoder activation inversion signal RDENBBD becomes “L”.
Then, the signal φ becomes “H”.

The other is a voltage conversion circuit comprising a NAND gate G3, an inverter I3, and HV n-ch Tr. When the node N3 becomes "H" and the block is selected, and the signal RNGRD oscillates, the output N2 of the block selection circuit becomes the voltage VppRW + Vt (sub = VppRW). At the time of standby, all the block selection circuits 7 output the voltage Vpp
In order to prevent a leak current from RW, the signal RDENBB is set to "H" and the node N3 is set to "H" to enter a block selection state.

In order for the voltage conversion circuit to operate normally,
It is desirable that Vt (sub = VppRW) of HV n-ch Tr. Qh be Vcc or less. It is desirable that the HV n-ch Tr. Qh has a substrate bias of 0 V, a source voltage and a gate voltage of Vcc, and is in an extremely weak inversion state or cutoff state.

FIG. 6 shows a specific configuration of the main bit line control circuit 2, the sub bit line control circuit 3, and the data latch and sense amplifier 4 shown in FIG.

The main bit line control circuit 2A includes an n-ch Tr.
4 is connected to the data latch and sense amplifier 4 when the signal SA, which is the gate electrode of FIG. n-ch Tr.Qn15,
16 charges the gate electrode of the depletion type n-channel MOS transistor Qd1 when the verify signal VRFYA becomes "H" in accordance with the data stored in the data latch and sense amplifier 4. If the channel of the depletion type n-channel MOS transistor is formed at the same time when the channel of the depletion type selection transistor in the memory cell array is formed, it can be formed without increasing the number of manufacturing steps. Alternatively, instead of the depletion type n-channel MOS transistor, a MOS capacitor may be formed by HV n-ch Tr. Qh.

When the signal SR is "H" and the signal SS1 or SS2
Becomes "H" and the bit line BL of the memory cell array 1A is
1 or BL2 and the main bit line control circuit 2 are selectively connected. Therefore, n-ch Tr.Qn17,19,20 and HV n-ch Tr.Qn
h28 and h29 are provided. n-ch Tr. Qn18 is signal RST
Resets the bit line at "H".

The main bit line control circuit 2B has the same circuit configuration as the main bit line control circuit 2A, but corresponds to the signal SB and the signal VRFYA corresponding to the bit lines BL3 and BL4 of the cell array 1B. Signal VRFYB is set as a control signal.

The data latch and sense amplifier 4 is an n-ch T
A flip-flop FF composed of r.Qn11 to 13 and p-ch Tr.Qp6 to 8 and an n-ch Tr.Qn10
And n-ch Trs Qn21 and Qn22 as column selection gates and a NOR circuit G4 as a column address decoder.

The signals φN and φp are “H” and “L”, respectively.
, The flip-flop FF is activated, and is deactivated by “L” and “H”, respectively. When the signal .phi.E becomes "H", the two terminals of the flip-flop FF are equalized. The voltage VBITH is a power supply voltage of the flip-flop FF. The column address inversion signal CADDBn (n =
1, 2, 3) are all "L", the column address decoder activation inversion signal CENBB is "L", the column selection gate is "ON", and the flip-flop FF is connected to the data input / output lines IOA, IOB. .

The sub-bit line control circuit 3A includes an HV n-ch Tr.
A bit line selection gate composed of Qh26, 27 and n-ch Tr. Qn5, 6; an n-ch Tr. Qn7 for resetting the bit line; and an n-ch Tr for transferring voltage VA to the bit line. .Qn8, an n-ch Tr. Qn9 which is a bit line potential detection circuit, and fuses F2,3 for relieving defective bit lines.

The bit lines BL1 or BL2 are selectively connected to the sub-bit line control circuit 3A by the signals SS1 and SS2. When the signal RSTD is "H", the bit line is reset. When the signal PRE is "H", the bit line charging voltage VA is transferred to the bit line. The output of the bit line potential detection circuit is φDT
Output as CA. In a bit line having a leak defect, the fuse F2,3 is cut.

The sub-bit line control circuit 3B has the same circuit configuration as the sub-bit line control circuit 3A. Signal φDTCB is set.

According to FIGS. 7, 8 to 13, memory cell array 1, main bit line control circuit 2, sub-bit line control circuit 3,
Data latch / sense amplifier 4, word line control circuit 6,
The operation of the block selection circuit 7 will be described. In the figure, the cell array portion is the portion of the memory cell array 1, the row decoder portion is the portion of the word line control circuit 6 and the block selection circuit 7, and the sense amplifier portion is the main bit line control circuit 2 and the sub bit line control circuit 3. It shows the part of the data latch / sense amplifier 4.

FIGS. 7 and 8 show the NAND cell unit NCU.
The timing of the read operation when 1 is selected, the control gate CG2 is selected, and the bit line BL1 is selected is shown. In this case, the bit line BL3 becomes a dummy bit line, and the bit lines BL2 and BL4 become shield lines.

First, the signal SS1 becomes "L", and the bit line BL1 is connected to the sub-bit line control circuit 3A and the bit line BL2.
Are connected to the main bit line control circuit 2A, the bit line BL3 is connected to the sub-bit line control circuit 3B, and the bit line BL4 is connected to the main bit line control circuit 2B. The signal PRE becomes "H", and the voltages VA (for example, 1.2 V) and VB (for example, 1.0 V) are charged to the bit lines BL1 and BL3, respectively. After the charging is completed, the signal PRE goes to "L", the signal SS2 goes to "L", and all the bit lines float. Signal RS
T goes low, the signal RSTD goes high, SS1 goes high, the selected bit line BL1 and the dummy bit line BL3 are connected to the main bit line control circuit 2, and the bit line B
L2,4 is connected to the sub-bit line control circuit 3 and grounded.

Only the block selection circuit 7 in which the signal RDENBB has become "L" and the block address signals RAn, RBn, RCn (AddR in FIGS. 7 and 8 are all "H") has its output N2 Becomes "H". The signal RDENBBD becomes “L” and the signal RNGR
When D oscillates, the output N2 of the block selection circuit 7 becomes Vcc
The voltage is boosted to + Vt (sub = Vcc). Also, the signal LIN
K is also boosted to Vcc + Vt (sub = Vcc) or more.

Signals VCG1,3-16, VSGD2, VSG
S2 becomes Vcc, only the selected control gate CG2 becomes 0V, and the other CG1,3 to 16 become Vcc. If the threshold value of the memory cell M is equal to or higher than 0 V, the potential of the bit line BL1 does not change. At the time of write verification, VCG2 is, for example, 0.5 V, CG2 is 0.5 V, and bit line B
The potential of L1 drops below the potential of dummy bit line BL3 when the threshold value of memory cell M is 0.5 V or less.

Signals VSGD2, VSGS2, VCG1 to
16 are all 0 V, the oscillation of the signal RNGRD stops, and the signal R
After DENBBD goes “H” and RDENBB goes “H”, the signal SR goes “L” and the selected bit line BL1
Is taken into the gate electrode of the depletion type n-channel MOS transistor Qd1, and the potential of the dummy bit line BL3 is taken into the gate electrode of the depletion type n-channel MOS transistor Qd2. Thereafter, the signal VRFYA becomes “H” only at the time of write verification,
Depletion type n channel M after writing "1"
The potential of the gate electrode of the OS transistor Qd1 is set to be higher than the potential of the gate electrode of the depression type n-channel MOS transistor Qd2.

When the signals φN and φP are “L”,
"H", then the signal .phi.E becomes "H", and the data latch and sense amplifier 4 is reset. The signals SA and SB become "H", the main bit line control circuit 2 and the data latch / sense amplifier 4 are connected, the signal .phi.P becomes "L", and the signal .phi.
The potential of the gate electrode of the transistor Qd1,2 is sensed,
The data is latched. When the signal SR becomes “H”, the sensed information is transferred to the gate of the n-ch Tr. Qn9, which is a bit line potential detection circuit, via the bit line BL.

When the writing is completed at the time of the write verify, all the dummy bit lines BL3 are at "L", so that the signal φDCTB previously charged to "H" remains at "H". Become. If the erase operation has been completed during the erase verify operation, all the selected bit lines BL1 are at "L" level, so that the signal .phi.DCTA previously charged to "H" remains at "H" level.

In this embodiment, the depletion type n
Although the potential is sensed by taking the potential of the bit line BL into the gate electrodes of the channel MOS transistors Qd1,2, FIG.
If the signal SR is controlled as shown by a chain line in FIG. 8, the bit line BL can be directly sensed.

During reading, the voltage VppRW of the block selection circuit 7 and the voltage VBIT of the data latch and sense amplifier 4
H is the power supply voltage Vcc.

FIGS. 9 and 10 show a NAND cell unit NC.
The timing of the write operation when U1 is selected, the control gate CG2 is selected, and the bit line BL1 is selected is shown.

When the signal RDENBB becomes "L", the block address AddR is determined, the signal RDENBD becomes "L", and the signal RNGRD oscillates, the output N2 of the block selection circuit becomes VppRW + Vt (sub = VppRW).

When the signal SS2 becomes "L", the selected bit line BL1 is connected to the main bit line control circuit 2A, and the unselected bit line BL2 is connected to the sub bit line control circuit 3A. Also,
The signal RST becomes "L".

Signals VSGD2, VSGS1, VCG1 to
16. The voltages Vsource and VA and the signals PRE and VRFYA become the power supply voltage Vcc. At this time, the selected bit line BL1 is
It becomes "H" for "1" write and "L" for "0" write. When the signal VRFYA goes "L" and the signal SA goes "H", the bit line BL1 and the data latch and sense amplifier 4 are connected via the main bit line control circuit 2A.

Subsequently, the voltages Vsource, VA, VBITH
Is applied to the output Vm8 (up to 8 V) of the Vm8 booster circuit 14 by the signal LI.
NK, the voltage VppRW is the output VppW of the Vpp booster circuit 12 (~
18V), the signals SS1, PRE, SA and SR are Vm10
The output of the booster circuit 13 becomes Vm10 (〜１０10 V).

The signals VSGD2, VSGS1, VC
G1,3 to 16 become Vm10. This timing is the voltage VB
The timing at which ITH is boosted to Vm8 may be the same.
Subsequently, the signal VCG2 becomes VppW, and the selected control gate CG2 becomes the write voltage VppW. At this time, the selected bit line BL1 is at Vm8 when "1" is written and at 0 V when "0" is written. The unselected bit line BL2 is connected to V
m8. As a result, the "0" -written memory cell M
, The potential VppW of the control gate CG and the channel potential 0
Electrons are injected into the charge storage layer by the potential difference of V, and the threshold value shifts in the positive direction.

In this embodiment, the voltage of the bit line BL1, the non-selected bit line BL2 and Vsource at the time of writing "1" is Vm8, but the bit lines BL1, BL2 and the source line V
The control gate CG and the channel of the memory cell M are capacitively coupled by utilizing the fact that the control gates CG1 to 16 are raised from Vcc to Vm10 or VppW by setting the source and the selection gates SGD2 and SGS1 to Vcc. To V
It may be about m8. This case is indicated by a dotted line in FIGS. 9 and 10, and is called a channel floating system.

The signal VCG2 changes from VppW to Vcc, and the selected control gate CG2 changes to Vcc. Then the signal VS
GD2, VSGS1, VCG1,3-16 are from Vm10 to Vcc
And each signal and voltage are reset to the standby state. During the write operation, the signal φN is at Vcc and φp and φE are at 0V.

FIG. 11 shows the voltages Vm8, Vm during the write operation.
This shows the operation of a write stress test of a circuit other than the memory cell array to which m10 and VppW are applied.

The operation is basically the same as the write operation, but the write voltage VppW is not applied to any control gate.
Further, the selection gates SGD1, SGD2, SGS1, S
GS2 is selected at the same time, the signals SS1 and SS2, the voltage V
A and VB are simultaneously selected. Both signals SA and SB remain "L". The reason why the signals SA and SB are “L” is to prevent the voltage stress from being applied to the memory cell array. The stress test when Vm10 is applied to the signals SA and SB is performed at the time of the erase stress test. This will be described later with reference to FIG.

The block address AddR is generated so as to select all blocks. At this time, the block in which the fuse F1 is cut in the block selection circuit 7 is not selected, but such a block may be selected by setting the signals RDENBB and RDENBD to "H".

The solid line in FIG. 11 shows the first write stress test, in which Vm10 is applied to the select gate and control gate of the memory cell array, and Vm8 is applied to the bit line and the source line. In the case of the channel floating method in the write operation described with reference to FIGS. The dashed line in FIG. 11 indicates the second write stress test, and the select gate, control gate, bit line, and source line are all at 0V. The data of the data latch and sense amplifier 4 at the time of the first write stress test is inverted at the time of the second write stress test.

FIG. 12 is a timing chart showing an erase operation. First, all the signals VCG1 to VCG16 become VECG. This VECG voltage is a voltage at which the HV n-ch Tr. Qh is cut off when the VECG is applied to the source and drain of the HV n-ch Tr. There is about 1V. Block address signals RA, R
B and RC are all “H” in the selected block (Ad in FIG. 12).
dR is shown as “H”), and any of the unselected blocks is “L” (AddR is shown as “L” in FIG. 12).

Signals RDENBB, LINK, SS1 and S
S2 becomes "L", and the bit lines and the control gates of the unselected blocks become floating. Also, the source line Vsour
ce is also in a floating state. Subsequently, the signal V
SGD1,2 and VSGS1,2 become Vcc, and the cell well Cp-well in which the memory cell array 1 is formed becomes Vcc. As a result, all bit lines BL, source lines Vsource, all selection gates SG, and control gates CG of all non-selected blocks
Is raised to almost Vcc by the potential of the cell well Cp-well. Only the control gates CG of the selected block are VECG.

Further, when the cell well Cp-well becomes the erase voltage VppE (up to 20 V), which is the output of the Vpp booster circuit 12, all the bit lines BL, the source lines Vsource, all the select gates SG, and the control gates CG of all the unselected blocks. Is raised to almost VppE by the potential of the cell well Cp-well. The potential V of the control gate CG of the selected block
Due to the potential difference between the ECG and the potential VppE of the cell well Cp-well, electrons are emitted from the charge storage layer in the memory cell M of the selected block, and the threshold value shifts in the negative direction.

After the cell well Cp-well changes from the erase voltage VppE to Vcc, each signal and voltage are reset to the standby state. During the erase operation, the voltage VppRW becomes Vcc and the signal RNG
RD is 0 V, and each signal and voltage of the sense amplifier unit is a signal S.
Except for S1 and SS2, the operation is the same as during standby.

FIG. 13 shows an operation of an erase stress test of a peripheral circuit to which an erase voltage is applied other than the memory cell array. Basically the same as the erase operation, but no block is selected. In addition, Vpp output of signals VCG1 to 16 (VppW but VppE is output in writing), which is not performed in the writing stress test, is performed, and the signal φN becomes “L” and φp becomes “H”, and the data latch and sense amplifier are used. 4 is deactivated, and the signals SA and SB become Vm10.

FIGS. 14 to 37 show the column control circuit 5, the row control circuit 9, and the cell well control circuit 1 shown in FIG.
0, among the cell source control circuit 11, and the boost circuits 12 to 14, all main circuits that handle the voltages Vm8, Vm10, and Vpp are shown.

FIG. 14A shows a specific configuration of the Vpp switch circuit 16 for switching between the write voltage / erase voltage (Vpp) and the ground potential. FIG. 14B shows an abbreviated symbol of the Vpp switch circuit. HV n-ch
Tr. Qh34 to 36, Qh37 to 39, Qh40 to 42, Qh43 to 45
Have the same configuration as the switching circuit shown in FIG. When the signal PONB is “H” and the output Vout is 0
V, when the signal PONB is at "L" and the signal RNG oscillates, the output Vout becomes a voltage higher than the write voltage / erase voltage (Vpp).
pp + Vt (sub = Vpp). FIG. 38 shows this operation timing. During standby, signal RNG is 0V, signal P
ONB is Vcc, voltage Vpp is Vcc, and Vout is 0V.
When the signal PONB becomes 0 V, Vout becomes Vcc-Vt (sub =
Vcc). When the signal RNG oscillates, the voltage Vpp
Is Vqq, Vout becomes Vqq + Vt (sub = Vqq).
When the voltage Vpp becomes Vcc and the signal PONB becomes Vcc, Vou
t becomes 0V.

FIG. 15A shows a specific configuration of the Vm switch circuit 17 for switching between the voltage Vm8 or Vm10 and the ground potential. FIG. 15B shows a schematic symbol of the Vm switch circuit. HV n-ch Tr. Qh50 〜
52, Qh53 to Qh53 each have the same configuration as the switching circuit shown in FIG. When the signal PONB is “H” and the output Vout is 0 V, and the signal PONB is “L” and the signal RNG oscillates, the output Vout becomes Vm + Vt (sub = Vm). FIG. 39 shows this operation timing. During standby, signal RNG is 0V, signal PONB is Vcc and Vout is 0
V. When the signal PONB becomes 0 V, Vout becomes Vcc-
It is about Vt (sub = Vcc). When the signal RNG oscillates, Vout becomes Vm + Vt (sub = Vm). Signal PO
When NB becomes Vcc, Vout becomes 0V.

FIG. 16A shows a specific configuration of the Vcc switch circuit 18 for switching between the power supply voltage Vcc and the ground potential. FIG. 16B shows an abbreviated symbol of the Vcc switch circuit. When the signal PONB is "H" and the output Vout is 0V, and the signal PONB is "L" and the signal RNG oscillates, the output Vout becomes about Vcc + 2Vt (sub = Vcc). FIG. 40 shows this operation timing. During standby, the signal RNG is 0V, the signal PONB is Vcc, and Vout is 0V. When the signal PONB becomes 0 V, Vout becomes Vcc
-Vt (sub = Vcc). When the signal RNG oscillates, Vout becomes about Vcc + 2Vt (sub = Vcc). When the signal PONB becomes Vcc, Vout becomes 0V.

FIG. 17A shows a specific configuration of the Vpp-Vcc switch circuit 19 for switching between the write voltage / erase voltage and the power supply voltage Vcc potential. FIG.
(B) shows an abbreviated symbol of the Vpp-Vcc switch circuit. When the signal EVCCB is "L" and the signal EVPP is "L", the output Vout becomes Vcc. When the signal EVCCB is "H" and the signal EVPP is "H" and the signal RNG oscillates, the output Vout becomes Vpp. FIG. 41 shows the operation timing. During standby, signal RNG is 0V, signal EV
CCB and EVPP are 0V, and Vout is floating about Vcc. When the signal RNG oscillates, Vout becomes Vcc
Becomes The signal EVCCB becomes Vcc, and then the signal EVP
When P becomes Vcc, Vout becomes Vpp. When the signal EVPP becomes 0V and subsequently the signal EVCCB becomes 0V, V
out becomes Vcc.

In this circuit, HV n-ch Tr. Qh63, 64, 70,
If 71,72,78,79 are depletion types with lower threshold values, the stability will increase. At this time, the depletion type high breakdown voltage n-channel MOS transistor has a gate voltage of Vcc, a source voltage of Vcc, and a drain voltage of Vc.
c, When the substrate voltage is 0 V, the state is inverted, and the gate voltage is 0
It is desirable that V, the source voltage be Vcc, the drain voltage be Vcc, and the substrate voltage be 0 V so that the substrate is cut off.
When the depletion type is used, the input signal RNG of the NAND circuits G8 and G9 is set to 0 V without need. Further, using the above-described depletion type high withstand voltage n-channel MOS transistor Qhd1,2, FIG.
It may be as follows. In the circuit shown in FIG. 61, the number of transistors used is small and the circuit area can be reduced.

HV nc of the block selection circuit 7 shown in FIG.
h Tr.
The gates 4 and 5 may be used as the signal RDENBBD. The HV n-ch Tr. Qh30,31,32,3 in FIGS.
3,46,47,48,56,57,58 are depletion type high breakdown voltage n-channel MOS transistors Qhd,
The gates of Qh30, 31, 46, 47, 56, 57 may be set to the signal PONB.

FIG. 18 shows a signal VCGn (n = 1 to 16).
2 shows a specific configuration of the control gate driver that outputs the control gate driver. The HV n-ch Trs Qh95 to Qh97 and Qh98 to Qh100 each have the same configuration as the switching circuit shown in FIG. FIG. 42 shows the operation timing. During standby, signals RNG, CGVGL, CGVCC, CGVM,
CGVPP and WPn are 0V. WPn (n = 1 to 1
6) respectively correspond to the outputs VCGn (n = 1 to 16), and WPnB is an inverted signal thereof. During standby, signals CG0V and CGTR are Vcc and voltage VPCCG1.
, VPPCG2 is Vcc, and the voltage VGL is 0V. Therefore, the output VCGn is 0V.

At the time of reading or the like, the signal CG0V becomes 0V
As a result, the signals CGVGL and CGVCC become Vcc.
At this time, if WPn is Vcc, voltage VGL is output. VGL is 0 V at the time of reading, a verify voltage (up to 0.5 V) at the time of write verification, and about 0 V to Vcc at the time of a test operation for measuring a threshold value of a memory cell. W
When Pn is 0 V, the output VCGn becomes Vcc.

At the time of writing or the like, the signal CG0V becomes 0
V and CGTR become 0 V, and CGVCC becomes Vcc. First, Vcc is output. Thereafter, the signal CGVCC becomes 0 V, the signals CGVPP and CGVM become Vcc, and the voltage V
PPCG1,2 becomes VppW. At this time, the signal WPn becomes V
When cc is VppW, VppW is output. When WPn is 0 V, VppW is output.
m10 is output. When the voltage VPPCG2 returns to Vcc,
When WPn is Vcc, the output is Vcc. After this VPP
CG1 returns to Vcc. Subsequently, the signal CGVPP becomes 0V,
CGVM becomes 0V. When the signal CGVCC is set to Vcc again, the output becomes Vcc when WPn is 0V. Signal CG
VCC becomes 0V, CG0V and CGTR become Vcc, and the output returns to 0V.

At the time of erasing or the like, the signal CG0V is 0 V, W
Pn all become Vcc, and the voltage VGL is output when the signal CVGL becomes Vcc. The voltage VGL is VECG (~
1V).

The HV n-ch Tr. Qh94 is connected to the above-described depletion type high withstand voltage n-channel MOS transistor Qh94.
It may be hd.

FIG. 19 shows signals VSGXn (X = D, S,
3 shows a specific configuration of a selection gate driver that outputs (n = 1, 2). HV n-ch Tr.
It has the same configuration as the switching circuit shown in FIG. FIG. 43 shows the operation timing. During standby, signals RNG, SGGND, SGVCC, SGVM, WSXn
Is 0V. The signal WSXn (X = D, S, n = 1,
2) corresponds to the output VSGXn (X = D, S, n = 1, 2), and WSXnB is an inverted signal thereof. Signal S
G0V is Vcc.

At the time of reading or the like, the signal SG0V becomes 0V
When signals SGGND and SGVCC become Vcc,
When the signal WSXn is at Vcc, Vcc is output, and WSXn is output.
Is 0V, the output is 0V. At the time of writing or the like, the signal SG0V becomes 0V and the signal WSXn becomes 0V.
In this case, 0 V is output by the signal SGGND which becomes Vcc. When signal WSXn is at Vcc, SGVCC is at Vcc.
Vcc is output when the signal is cc, and Vm10 is output when the signal SGVM is Vcc. At the time of erasing or the like, the signals WSXn are all at Vcc, and all VSGXn are at Vcc.

FIG. 20 shows the voltage VPPCGn (n = 1,
2 shows a circuit for controlling (2). Signal CDVPPn
(N = 1, 2) and CDVCCnB (n = 1, 2) correspond to the output VPPCGn (n = 1, 2), respectively.
When the signals CDVPPn and CDVCCnB are 0V, the output is Vc
c, when CDVPPn and CDVCCnB are at Vcc and signal RNG
When oscillates, Vpp is output.

FIG. 21 shows a circuit for controlling the voltage VppRW. When the signals RWVPP and RWVCCB are 0 V and the output is Vcc, the signals RWVPP and RWVCCB are Vcc and the signal RNG
When oscillates, Vpp is output.

FIG. 22 shows a specific configuration of a circuit for outputting a signal LINK. FIG. 44 shows this operation timing. During standby, signals RNG, LK0V, LK
BT and LKVCCB are 0V, and signals LKTR and LKVP
PB is Vcc, and voltages VPPLK1,2 are Vcc. Therefore, the output becomes Vcc.

At the time of reading or the like, the signal LKTR becomes 0 V
The signal LKVCCB becomes Vcc, and the signal LKBT
Becomes Vcc, the output LINK is boosted from Vcc and Vcc +
becomes α. α is equal to or lower than Vcc. At the time of writing,
Signal LKTR is 0V, LKVCCB is Vcc, LKVPP
B becomes 0V, the voltage VPPLK1,2 becomes VppW, and the output LINK becomes VppW. When the voltage VPPLK2 is V
cc, and the output LINK becomes Vcc. At the time of erasing or the like, the signals LKVCCB and LK0V become Vcc, and the output LINK becomes 0V.

The HV n-ch Tr. Qh108, 109 may be the above-described depletion type high breakdown voltage n-channel MOS transistor Qhd.

FIG. 23 shows the voltage VPPLKn (n = 1,
2 shows a circuit for controlling (2). Signal LKVPPn
(N = 1, 2) and LKVCCnB (n = 1, 2) respectively correspond to the output VPPLKn (n = 1, 2).
When the signals LKVPPn and LKVCCnB are 0 V, the output is Vc
c, LKVPPn and LKVCCnB are Vcc and the signal RNG
When oscillates, Vpp is output.

FIG. 24 shows a voltage VPCPWn (n = 1,
2 shows a circuit for controlling (2). Signal CPVPPn
(N = 1, 2) and CPVCCnB (n = 1, 2) correspond to the output VPPCPWn (n = 1, 2), respectively. When the signals CPVPPn and CPVCCnB are 0 V, the output is Vcc, and the signals CCPPPn and CPVCCnB are Vcc, and the signal RN is output.
When G oscillates, Vpp is output.

FIG. 25 shows a specific configuration of a circuit for outputting the voltage Cp-well. HV n-ch Tr. Qh115 ~ 11
7 has the same configuration as the switching circuit shown in FIG. FIG. 45 shows the operation timing. During standby, the signals RNGE, READ, MVTD are at 0V, and the signals CPW0V, CPW3VB, CPWTR, CPWVPP
B is Vcc, and the voltages VPPCPW1,2 are Vcc. Therefore, the output becomes 0V.

At the time of reading, etc., the output Cp-well is 0
However, when the signal MVTD becomes Vcc, the voltage VPW is output. The voltage VPW is 0 V to Vcc and is used during a test operation for measuring a negative threshold value of the memory cell M. At the time of erasing or the like, the signals CPW0V, CPW3VB, CPW
TR and CPWVPPB become 0V, and the voltage VPPCP
W1 and W2 become VppE, and VppE is output. Voltage V
PPCPW2 becomes Vcc, Cp-well becomes Vcc, and signals CPW0V, CPW3VB, CPWTR, CP
WVPPB becomes Vcc and becomes 0V.

The HV n-ch Tr. Qh114 is connected to the above-described depletion type high withstand voltage n-channel MOS transistor Qh114.
It may be hd.

FIG. 26 shows a specific configuration of a circuit for outputting the voltage Vsource. HV n-ch Tr. Qh120 ~ 122
Has the same configuration as the switching circuit shown in FIG. FIG. 46 shows the operation timing. During standby, signals RNG, READ, and MVTD are at 0 V and signal C
S0V, CSTR, CS3VB, CSVVCCB, CSV
M8B is Vcc. Therefore, the output becomes 0V.

At the time of reading or the like, the output Vsource is 0 V
However, when the signal MVTD becomes Vcc, a voltage VPW is output. The voltage VPW is 0 V to Vcc and is used during a test operation for measuring a negative threshold value of the memory cell M. At the time of writing or the like, the signal CS0V becomes 0V and CS3V
When B and CSVVCCB become 0V, Vcc is output.
Thereafter, when the signal CSVVCCB becomes Vcc and CSTR and CSVM8B become 0V, Vm8 is output. At the time of erasing or the like, the signals CS0V, CS3VB, and CSTR become 0.
V, and the output Vsource becomes floating. At this time, the potential changes according to the voltage Cp-well.

The HV n-ch Tr. Qh118 is connected to the depletion type n-channel MOS transistor Q
It may be hd.

FIG. 27 shows a specific configuration of a circuit for outputting signal SX (X = A, B). HV n-ch Tr. Q
h127 to 129 have the same configuration as the switching circuit shown in FIG. FIG. 47 shows the operation timing. During standby, signals RNG, SABTRB, SAB3V,
SABBT, SAB10V and CELLX are at 0V, and the signal SAB0V is at Vcc. Therefore, the output becomes 0V. The signal CELLX (X = A, B) is the output SX (X = A, B)
It corresponds to.

At the time of reading or the like, the signal SAB0V becomes 0
When V and SAB3V become Vcc and CELLA and CELLB both become Vcc, and subsequently, the signals SABTRB and SABBT become Vcc, the output becomes Vcc + α. α is equal to or lower than Vcc. At the time of writing or the like, when the signal SAB0V becomes 0V, the signal SAB3V becomes Vcc, and then the signal SABTRB becomes Vcc and the SAB10V becomes Vcc, the signal CEL
When LX is Vcc, the output is Vm10 + Vcc-Vt (sub = V
m10).

The HV n-ch Tr. Qh123, 124 may be the above-mentioned depletion type high breakdown voltage n-channel MOS transistor Qhd.

FIG. 28 shows a specific configuration of a circuit for outputting the signal SSn (n = 1, 2). FIG. 48 shows the operation timing. During standby, signals RNG, S
SRSTB, SSGND, SSBT, SSVCC, SS
10V and SBLn are 0V. Therefore, the output becomes Vcc. The signal SBLn (n = 1, 2) is output SSn (n =
1, 2). The signal SBLnB is an inverted signal thereof.

At the time of reading, when the signal SSRSTB becomes Vcc and SSGND becomes Vcc and SSBT becomes Vcc, the output is boosted to Vcc + α when the signal SBLn is Vcc. α is equal to or lower than Vcc. When the signal SBLn is 0V, the output is 0V. At the time of writing, the signal SS
When RSTB and SSGND become Vcc and signal SS10V becomes Vcc, when signal SBLn is Vcc, Vm10 + V
It is about cc-Vt (sub = Vm10). When the signal SBLn is 0
In the case of V, 0 V is output. At the time of erasing or the like, the signals SSRSTB and SSGND become Vcc, and SBL1, SBL
BL2 becomes 0V and both outputs SS1 and SS2 become 0V.
V.

FIG. 29 shows a specific configuration of a circuit for controlling voltage VBITH. FIG. 49 shows the operation timing. During standby, signals RNG and NW8V are 0
At V, the signal NW8VDB is at Vcc. Therefore, the output is V
cc. When the signal NW8V becomes Vcc and NW8VDB becomes 0V, the voltage VBITH becomes Vm8.

The HV n-ch Tr. Qh138 is connected to the above-described depletion type high withstand voltage n-channel MOS transistor Qh138.
It may be hd.

FIG. 30 shows a specific configuration of a circuit for outputting voltage VX (X = A, B). HV n-ch Tr. Q
h144 to 146 have the same configuration as the switching circuit shown in FIG. FIG. 50 shows the operation timing. During standby, signals RNG, VABRSTB, VAB0
V, VABL, VABH, VAB8V, PRCX are 0V
And both the voltages VHL and VHH are 0V. Therefore, the output becomes 0V. The signal PRCX (X = A, B) is the output V
X (X = A, B). The signal PRCXB is P
This is an inverted signal of RCX.

At the time of reading or the like, the signal VABRSTB
Is Vcc, VABL and VABH are Vcc, and PRCX is Vcc
In this case, the voltage VHH is output. Signal PRCX is 0V
In this case, the voltage VHL is output. At the time of writing or the like, the signal VABRSTB becomes Vcc. When the signal PRCX is 0V, the output is 0V because the signal VAB0V becomes Vcc. When the signal PRCX is Vcc, the signal VA
When BH and the voltage VHH become Vcc, the output becomes Vcc, and when the signal VAB8V becomes Vcc, the output becomes Vm8.

FIG. 31 shows a specific configuration of a circuit for outputting signal PRE. HV n-chTr. Qh151 to Qh153 have the same configuration as the switching circuit shown in FIG. FIG. 51 shows the operation timing. During standby, signals RNG, PREBT, PRE10V are 0V,
Signals PR0V and PRTR are at Vcc. Therefore the output is 0
V.

At the time of reading or the like, the signal PR0V becomes 0
When V and PRTR become 0V and the signal PRBT becomes Vcc, the output becomes Vcc + α. α is equal to or lower than Vcc. At the time of writing or the like, when the signal PR0V becomes 0V and the signal PRTR becomes 0V, and subsequently the signal PR10V becomes Vcc,
The output is about Vm10 + Vcc-Vt (sub = Vm10).

The HV n-ch Tr. Qh147, 148 may be the above-described depletion type high breakdown voltage n-channel MOS transistor Qhd.

FIG. 32 shows a specific configuration of a circuit for outputting signal SR. FIG. 52 shows the operation timing. During standby, signals RNG, SR0V, SRB
T and SRVCCB are at 0 V, and signal SR10VB is at Vcc. Therefore, the output becomes Vcc.

At the time of reading or the like, when the signal SRVCCB becomes Vcc and the signal SRBT becomes Vcc, the output becomes Vcc.
+ Α. α is equal to or lower than Vcc. Then SR0V becomes V
When it becomes cc, the output becomes 0V. At the time of writing or the like, the signal SRVCCB becomes Vcc, and then the signal SR10V
When B becomes 0 V, the output becomes Vm10 + Vcc-Vt (sub = V
m10).

FIG. 33 shows a specific configuration of a circuit for outputting signal φE. FIG. 53 shows the operation timing. During standby, the signals FIETRB and FIEBT are at 0V, and the signal FIE3VB is at Vcc. Therefore, the output becomes 0V.

At the time of reading or the like, when the signal FIE3VB becomes 0 V, the signal FIERB becomes Vcc, and subsequently, when the signal FIEBT becomes Vcc, the output becomes Vcc + α.
α is equal to or lower than Vcc. The HV n-ch Tr. Qh162, Qh163 may be the depletion type high withstand voltage n-channel MOS transistor Qhd described above.

FIG. 34 shows a signal VRFYX (X = A, B).
2 shows a specific configuration of a circuit that outputs the data. FIG. 54 shows this operation timing. During standby, signal VR3
V, VRTRB, VRBT, and PRCX are 0V. Therefore, the output becomes 0V. The signal PRCX (X = A, B) corresponds to the output VRFYX (X = A, B). Signal P
RCXB is an inverted signal of PRCX.

At the time of reading or the like, the signal VR3V becomes Vcc
And the signal VRTRB becomes Vcc.
When the RBT becomes Vcc, the output becomes Vcc + α when the signal PRCX is Vcc. α is equal to or lower than Vcc. Signal PRC
When X is 0V, the output is 0V.

The HV n-ch Tr. Qh164, 165 may be the depletion type high breakdown voltage n-channel MOS transistor Qhd.

FIG. 35A specifically shows a booster cell used in a booster circuit. When the signal PRST becomes sufficiently high, the boost cell is reset. Signal PRST
Is 0 V, the signal φ is 0 V, and the signal φB becomes Vcc,
The input voltage Vin is transferred to Vout. Thereafter, the signal φ becomes Vcc and the voltage Vout is boosted. FIG. 35B is an abbreviated symbol of the booster cell 20.

The HV n-ch Tr. Qh166, 169, 170, 172 may be the depletion type high breakdown voltage n-channel MOS transistor Qhd.

FIG. 36 shows a specific configuration of the booster circuit. Vpp booster circuit 12, Vm10 booster circuit 13, Vm8
The booster circuit 14 is also the circuit shown in FIG. 36, but differs in the number n of the booster cells 20. When the boosting potential is low, the number of boosting cells may be small. Although the output is VPUMP in FIG. 36, the Vpp booster circuit 1
2, Vm10 booster circuit 13 and Vm8 booster circuit 14,
Vpp, Vm10, and Vm8, respectively. When the signal PRSTB is at Vcc, the booster circuit is reset. When the signal PRSTB is 0
V and the signals φ1 to 4 oscillate, the output VPUMP
Is boosted.

The HV n-ch Tr. Qh173, 174, 176, 178 may be the depletion type high breakdown voltage n-channel MOS transistor Qhd. The gates of Qh174 and Qh174 are preferably set to the signal PRSTB.

FIG. 37 shows a specific configuration of the boosted potential limiter circuit. The boost potential limiters connected to the outputs of the Vpp booster circuit 12, the Vm10 booster circuit 13, and the Vm8 booster circuit 14 are the circuits shown in FIG. 37, but the connections of the switches SW are different. Although the output is VPUMP in FIG. 37, the Vpp booster circuit 12, Vm10
For the booster circuit 13 and the Vm8 booster circuit 14,
pp, Vm10 and Vm8. The signal PRSTB is at Vcc, and the output VPUMP is at Vcc.

The signal EXV is normally 0 V. When Vpp, Vm10, and Vm8 are supplied from the outside during the test operation, EXV
V becomes Vcc. When the signal PRSTB becomes 0 V, resistances R1 to Rn between the voltage VPUMP and the ground potential cause
A voltage proportional to VPUMP is input to the voltage comparator 21 via the switch SW. This voltage is equal to the reference voltage Vre
When the voltage Vref is higher, an “L” level voltage is applied to the gate electrode of the n-ch Tr. Qn35 by the voltage comparator, and when the voltage Vref is lower, the gate electrode of the n-ch Tr. The voltage of "H" level is applied by the voltage comparator to lower the potential of VPUMP. In this limiter circuit, voltage trimming can be performed in response to manufacturing variations by changing the connection of the switch SW after manufacturing. FIG.
Indicates the timing of this step-up operation. FIG.
FIG. 56 shows an example in which the output Vpp of the Vpp booster circuit is boosted corresponding to 5 in FIG.

The HV n-ch Tr. Qh181 is connected to the depletion type n-channel MOS transistor Q
It may be hd. The gate of Qh181 should be a signal PRSTB.

FIG. 57 shows a specific configuration of a circuit for controlling the voltage Vdd. During standby, the signal CESB is Vcc
The voltage Vdd is disconnected from the power supply voltage Vcc. If not waiting, the signal CESB becomes 0V and Vdd becomes Vcc.

FIG. 58 shows such a NAND type EEPR.
4 shows a threshold distribution of the memory cell M after the OM write operation. This distribution is obtained when “0” is written to all the memory cells M at the same write voltage and the same write time. Actual writing is performed while repeating the write operation and the bit-by-bit verify operation.
The threshold distribution width of the memory cell M becomes narrower. However, in order to fall within a predetermined distribution range within a predetermined write time, the distribution as shown in FIG. 58 must also be within the predetermined range. Distant bits) need to be replaced by redundant cells. If the write voltage deviates from the set value, trimming must be performed. Therefore, a threshold range having a distribution frequency equal to or higher than an appropriate distribution frequency K is measured. The lower limit is Vt-min and the upper limit is Vt-max.

FIGS. 59 and 60 show Vt-min and Vt-max.
5 shows the write voltage VppW trimming and the method of detecting a separated bit.

First, a predetermined number or more of, for example, all memory cells are erased (P1). Write voltage VppW to initial value Vpp
W0 is set (P2), and the above-mentioned erased memory cell is written for a fixed write time TpW (P3). After the writing, the threshold distribution of the memory cell to which the above-described writing has been performed is measured, and Vth-min and Vth-max are obtained (P4). V
If t-min is 0 V or less, the write voltage is too low, and if Vt-max exceeds the power supply voltage Vcc, the write voltage is too high. If it is too low, increase the write voltage VppW by ΔVpp. If it is too high, it is better to lower it by ΔVpp. This is because the range of the threshold value that can be accurately measured is out of the range. Then, all bits are erased and the measurement is performed again. However, when VppW exceeds the upper limit VppW-max of the write voltage VppW or VppW falls below the lower limit VppW-min, the measurement is stopped and treated as a defective product. (P5, P6, P17 ~ 21) Vt-center to (V
t-max + Vt-min) / 2 (P7).

If Vt-center is higher than V2, the write voltage is too high, and if Vt-center is lower than V1, the write voltage is too low. Should be reduced by ΔVpp. This is because the value is out of the range of the threshold value that can be accurately measured. Then, all bits are erased and the measurement is performed again. However, the upper limit V of the write voltage VppW
VppW exceeding ppW-max or V below the lower limit VppW-min
If it reaches ppW, stop the measurement and treat it as defective. (P8, P9, P22 to 26) Vt-center is corrected to Vt1 in consideration of the difference between the initial value VppW0 of the write voltage and the write voltage VppW used for the measurement. For example, Vt-ce
The value obtained by correcting nter by VppW0−VppW is defined as Vt1 (P10). Then, deviation Δ of Vt1 from the optimum value Vt0
Vt is obtained (P11). If ΔVt is not a value that can be trimmed, the measurement is stopped and treated as a defective product (P1
2).

From ΔVt, write voltage trimming is performed (P13), and a memory cell M having a threshold value outside a predetermined range around Vt-center is set as a separated bit (P1).
4). If the separated bit cannot be repaired, it is treated as a defective product (P15). Finally, save the separated bits (P1
6), end.

The write voltage VppW is trimmed by, for example, ΔVt. That is, VppW immediately after manufacturing is 20
If ΔVt is 1V at V, trimming is performed so that VppW is closest to 21V. It should be noted that trimming of erase voltage and separation bits after erase can be performed in the same manner based on the threshold distribution after erase.

As described above, according to the present invention, a transistor having a high breakdown voltage structure to which a writing voltage or an erasing voltage is applied is inverted or weak when the threshold voltage is low and the gate voltage, source voltage, and substrate voltage are 0V. Only transistors in an inverted state were used. Further, it has been described that the kind of the high breakdown voltage transistor can be only one kind. In this embodiment, the high breakdown voltage transistor is n
Although a channel MOS transistor has been described as an example, a p-channel MOS transistor can be similarly implemented. Further, according to the present invention, of the threshold voltage distribution of the memory cell after the write operation without the verify operation, the threshold voltage having a predetermined distribution frequency is separated from the threshold voltage range for forming the write voltage trimming and the tail of the threshold voltage distribution. A memory cell having a different threshold value can be detected. In the present embodiment, the operation is performed based on the threshold value after writing.
For M and the like, the same operation can be performed based on the threshold value after erasing.

The nonvolatile semiconductor memory device according to the present invention is not limited to the NAND cell type EEPROM as in the above embodiment, but can be similarly applied to a NOR cell type EEPROM and the like. Further partially, DRAM, SRAM, MRO
The present invention can also be applied to various semiconductor memory devices such as M.

Further, various applications can be made in accordance with the above-mentioned gist. For example, in the switching circuits shown in FIGS. 3B and 3C, the HV n-ch Tr. Qh3 may be a depletion type n-channel MOS transistor, and the gate voltage may be fixed to, for example, 0V. At this time, the depletion type n-channel MOS transistor is desirably cut off under the condition that the substrate bias and the gate voltage are 0 V and the source voltage is Vcc, and the substrate bias and the gate voltage are 0 V and the drain voltage is Vcc. Under the conditions, the voltage transferred to the source is the substrate bias and the gate voltage is 0.
When applied to the source of HV n-ch Tr.
It is desirable that the -ch Tr. Qh be cut off.

[0142]

As described in detail above, according to the present invention, as described above, according to the present invention, a transistor having a high breakdown voltage structure to which a writing voltage or an erasing voltage is applied has a low threshold voltage and a low gate voltage. It is possible to use only a transistor which is in an inverted or weakly inverted state when the voltage, the source voltage, and the substrate voltage are 0V. Further, only one kind of the high breakdown voltage transistor can be used. Leakage current during standby, which is likely to occur due to a low threshold, can be suppressed by setting all the block selection circuits to the block selection state during standby. In addition, a switching circuit including two high-withstand-voltage transistors connected in series and having a bias circuit for biasing a voltage at a connection point between the two transistors. By deactivating the bias circuit during standby, the leakage current during standby is reduced. Can be suppressed. Thus, a semiconductor memory device that operates even at a low power supply voltage and has low manufacturing cost is realized.

Further, in the present invention, at the time of the peripheral circuit voltage stress test at the time of the erasing operation, the data storage circuit for temporarily storing the write data is inactivated, so that the stress test can be performed at a high speed. Thus, the throughput of the test process is increased, and a semiconductor memory device with low test cost can be manufactured.

In addition, of the threshold voltage distribution of the memory cell after the write operation without the verify operation, the threshold voltage having a predetermined distribution frequency is separated from the threshold voltage range for forming the write voltage trimming and the tail of the threshold voltage distribution. The memory cell having the threshold value can be detected with high accuracy. As a result, the yield can be increased and a semiconductor memory device with low manufacturing cost can be realized.

[Brief description of the drawings]

FIG. 1 is a NAND cell type EEPROM according to an embodiment;
FIG. 2 is a block diagram showing the configuration of FIG.

FIG. 2 is a view showing characteristics of a high breakdown voltage MOS transistor according to the embodiment;

FIG. 3 is a diagram showing a configuration of a switching circuit according to the embodiment.

FIG. 4 is a diagram showing a configuration of a NAND memory cell array according to the embodiment;

FIG. 5 is a diagram showing a configuration of a block selection circuit and a block control circuit according to the embodiment.

FIG. 6 is a diagram showing a configuration of a main bit line control circuit, a sub bit line control circuit, and a data latch and sense amplifier according to the embodiment.

FIG. 7 is a timing chart for explaining a read operation according to the embodiment;

FIG. 8 is a timing chart for explaining a read operation according to the embodiment;

FIG. 9 is a timing chart for explaining a write operation according to the embodiment;

FIG. 10 is a timing chart for explaining a write operation according to the embodiment;

FIG. 11 is a timing chart for explaining a write peripheral circuit stress test operation according to the embodiment;

FIG. 12 is a timing chart for explaining an erase operation according to the embodiment;

FIG. 13 is a timing chart for explaining an erase peripheral circuit stress test operation according to the embodiment;

FIG. 14 is a diagram showing a specific configuration of a control circuit according to the embodiment.

FIG. 15 is a diagram showing a specific configuration of a control circuit according to the embodiment.

FIG. 16 is a diagram showing a specific configuration of a control circuit according to the embodiment.

FIG. 17 is a diagram showing a specific configuration of a control circuit according to the embodiment.

FIG. 18 is a diagram showing a specific configuration of a control circuit according to the embodiment.

FIG. 19 is a diagram showing a specific configuration of a control circuit according to the embodiment.

FIG. 20 is a diagram showing a specific configuration of a control circuit according to the embodiment.

FIG. 21 is a diagram showing a specific configuration of a control circuit according to the embodiment.

FIG. 22 is a diagram showing a specific configuration of a control circuit according to the embodiment.

FIG. 23 is a diagram showing a specific configuration of a control circuit according to the embodiment.

FIG. 24 is a diagram showing a specific configuration of a control circuit according to the embodiment.

FIG. 25 is a diagram showing a specific configuration of a control circuit according to the embodiment.

FIG. 26 is a diagram showing a specific configuration of a control circuit according to the embodiment.

FIG. 27 is a diagram showing a specific configuration of a control circuit according to the embodiment.

FIG. 28 is a diagram showing a specific configuration of a control circuit according to the embodiment.

FIG. 29 is a diagram showing a specific configuration of a control circuit according to the embodiment.

FIG. 30 is a diagram showing a specific configuration of a control circuit according to the embodiment.

FIG. 31 is a diagram showing a specific configuration of a control circuit according to the embodiment.

FIG. 32 is a diagram showing a specific configuration of a control circuit according to the embodiment.

FIG. 33 is a view showing a specific configuration of a control circuit according to the embodiment.

FIG. 34 is a view showing a specific configuration of a control circuit according to the embodiment.

FIG. 35 is a diagram showing a specific configuration of a control circuit according to the embodiment.

FIG. 36 is a view showing a specific configuration of a control circuit according to the embodiment.

FIG. 37 is a diagram showing a specific configuration of a control circuit according to the embodiment.

FIG. 38 is a timing chart for explaining the operation of the control circuit according to the embodiment;

FIG. 39 is a timing chart for explaining the operation of the control circuit according to the embodiment;

FIG. 40 is a timing chart for explaining the operation of the control circuit according to the embodiment;

FIG. 41 is a timing chart for explaining the operation of the control circuit according to the embodiment;

FIG. 42 is a timing chart for explaining the operation of the control circuit according to the embodiment;

FIG. 43 is a timing chart for explaining the operation of the control circuit according to the embodiment;

FIG. 44 is a timing chart for explaining the operation of the control circuit according to the embodiment;

FIG. 45 is a timing chart for explaining the operation of the control circuit according to the embodiment;

FIG. 46 is a timing chart for explaining the operation of the control circuit according to the embodiment;

FIG. 47 is a timing chart for explaining the operation of the control circuit according to the embodiment;

FIG. 48 is a timing chart for explaining the operation of the control circuit according to the embodiment;

FIG. 49 is a timing chart for explaining the operation of the control circuit according to the embodiment;

FIG. 50 is a timing chart for explaining the operation of the control circuit according to the embodiment;

FIG. 51 is a timing chart for explaining the operation of the control circuit according to the embodiment;

FIG. 52 is a timing chart for explaining the operation of the control circuit according to the embodiment;

FIG. 53 is a timing chart for explaining the operation of the control circuit according to the embodiment;

FIG. 54 is a timing chart for explaining the operation of the control circuit according to the embodiment;

FIG. 55 is a timing chart for explaining the operation of the control circuit according to the embodiment;

FIG. 56 is a timing chart for explaining the operation of the control circuit according to the embodiment;

FIG. 57 is a view showing a specific configuration of a control circuit according to the embodiment;

FIG. 58 is a view showing a threshold distribution after writing of a memory cell according to the embodiment;

FIG. 59 is a view showing an algorithm of a write voltage trimming and separation bit detection method according to the embodiment;

FIG. 60 is a view showing an algorithm of a write voltage trimming and separation bit detection method according to the embodiment;

FIG. 61 is a view showing a specific configuration of a control circuit according to the embodiment;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 memory cell array 2 main bit line control circuit 3 sub-bit line control circuit 4 data latch / sense amplifier 5 column control circuit
6 Word line control circuit 7 Block select circuit 8 Block address buffer 9 Row control circuit 10 Cell well control circuit 11 Cell source control circuit 12 Vpp booster circuit 13 Vm10 booster circuit 14 V
m8 booster circuit, 15 ... bias circuit 16
... Vpp switch circuit, 17 ... Vm switch circuit
18 Vcc switch circuit 19 Vpp-Vcc switch circuit 20 Boost cell 21 Voltage comparator Qh High-voltage n-channel MOS transistor Qhd High-voltage structure depletion type n-channel M
OS transistor Qd: depletion type n-channel MOS transistor Qn: n-channel MOS transistor Qp: p-channel MOS transistor S: selection transistor M: memory cell SG: selection gate CG: control gate I: inverter circuit G: logic gate circuit R ... Resistor SW ... Switch circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11C 17/00 639Z

Claims (4)

[Claims] A memory cell array in which a charge storage layer and a control gate are stacked on a semiconductor layer and electrically rewritable memory cells are arranged in a matrix;
Erasing means for erasing data in the memory cell;
Writing means for writing data to the memory cells, write voltage adjusting means for adjusting a write voltage,
Threshold value detecting means for measuring a threshold value of the memory cell, erasing data of a predetermined number or more of memory cells,
Writing to the erased memory cell, detecting the threshold value of the written memory cell, measuring the threshold distribution, and adjusting the write voltage from the threshold value having a predetermined distribution frequency or more. A semiconductor memory device. 2. A memory cell array in which a memory cell which is formed by laminating a charge storage layer and a control gate on a semiconductor layer and which is electrically rewritable is arranged in a matrix.
Erasing means for erasing data in the memory cell;
Erasing voltage adjusting means for adjusting an erasing voltage, writing means for writing data to the memory cells, and threshold value detecting means for measuring a threshold value of the memory cells; Write to the cell, then
The erased memory cell is erased, a threshold distribution of the erased memory cell is detected, and a threshold distribution is measured. A semiconductor memory device that performs adjustment. 3. A memory cell array in which a charge storage layer and a control gate are stacked on a semiconductor layer and electrically rewritable memory cells are arranged in a matrix.
Erasing means for erasing data in the memory cell;
A write unit for writing data to the memory cell, a threshold detecting unit for measuring a threshold of the memory cell, and a redundant memory cell for relieving a defective memory cell; Erase the data in the memory cells of
Writing to the erased memory cell, detecting the threshold value of the written memory cell, measuring the threshold distribution, and deviating from the threshold having a predetermined distribution frequency or more by a predetermined value or more A memory cell having a reduced threshold value. 4. A memory cell array in which a charge storage layer and a control gate are stacked on a semiconductor layer and electrically rewritable memory cells are arranged in a matrix.
Erasing means for erasing data in the memory cell;
A write unit for writing data to the memory cell, a threshold detecting unit for measuring a threshold of the memory cell, and a redundant memory cell for relieving a defective memory cell; Write to the memory cells of
The erased memory cell is erased, the threshold value of the erased memory cell is detected, and the threshold distribution is measured. A memory cell having a reduced threshold value.