JP2001283588A - Dynamic random access memory cell, device comprising the cell, and manufacturing method for dynamic random access memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DRAM of which design size is reduced and performance is improved. SOLUTION: This device is a dynamic random access memory cell operated with read lines (r1), word lines (w1), and bit lines (b1), and comprising of a first transistor connected between a bit line and a word line, a second transistor connected between a bit line and a read-line, and a third other transistor connected between two transistors and accumulating electric charges.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a dynamic random access memory (DRAM), and more particularly to a dynamic random access memory (DRAM).
The present invention relates to a method of manufacturing a RAM cell, a DRAM memory device, and a DRAM storage device.

[0002]

2. Description of the Related Art Silicon VLSI (Very Large Scale Integrated Circuit)
The current general design of DRAMs for use a single transistor and a capacitor cell. This design produces a very small voltage difference when the cell is read due to the small amount of re-dispersed charge. Therefore,
Sense amplifiers used with memory cells must be designed to very high technical specifications. In this case, it is extremely difficult to achieve this using a polysilicon TFT (thin film transistor) because the threshold voltage greatly fluctuates.
Further, it is believed that TFT performance is limited. Thus, a common memory cell that uses polysilicon TFTs is a static RAM, rather than a dynamic RAM, and these TFTs use six transistors per cell, and thus are substantially effective for memory cells. The size must be increased.

[0003]

SUMMARY OF THE INVENTION An object of the present invention has been made in view of the above problems, and an object of the present invention is to provide a DRAM with improved performance.

[0004]

According to a first aspect of the present invention, there is provided a first transistor operating on a read line, a word line, and a bit line, and having a first transistor connected between the bit line and the word line. A dynamic random access memory cell comprising a second transistor connected between a bit line and a read line and a third transistor connected between the other two to store charges.

[0005] Preferably, the transistor of the memory cell is a thin film transistor. Preferably, the transistor of the memory cell is formed of polysilicon. More preferably, the transistor of the memory cell is formed of a p-type material.

According to a second aspect of the present invention, there is provided a dynamic random access memory device comprising a plurality of memory cells according to the first aspect of the present invention.

[0007] Preferably, the memory device further comprises a bootstrap word line driver.

Advantageously, the memory device further comprises a self-timed (self-timed) bit line driver, and more preferably, the self-time bit line driver includes a dummy bit line.

According to a third aspect of the present invention, a step of connecting a first transistor between a bit line and a word line, a step of connecting a second transistor between a bit line and a read line, A method is provided for providing a dynamic random access memory storage device comprising the steps of connecting to the first two transistors and storing charge.

Preferably, the method further comprises the step of precharging the bit lines before reading.

The method further includes providing a dummy bit line, precharging the dummy bit line with the bit line, and turning off the bit line driver when it is determined that the dummy bit line has been charged. It is more preferable to consist of

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

The circuits of FIGS. 1A and 1B provide a dynamic random access memory cell with only three transistors and no other components. As shown, the memory has a read line (rl) and a word line (w).
1) and bit lines (bl). Two of the transistors have their source or drain connected to the bit line and their gates connected to one of the word line wl and one of the read lines rl. The third transistor has its gate connected to the source or drain of one of the first and second transistors (neither is connected to the bit line) and its source or drain is the other source of the first and second transistors. Or drain (none connected to bit line)
It is connected to the. The other connection of the third transistor is
The n-type circuit of FIG. 1A is grounded. FIG.
In the p-type circuit of (B), the other connection of the third transistor is connected to Vdd. In practice, the gate of the third transistor is a capacitive storage
Used for

A polysilicon TFT can be used for any of the three transistors. Preferably, a p-type transistor is used in the configuration of the circuit of FIG. The reason is that the p-type transistor has higher stability than the n-type transistor. As a result, smaller sized transistors can be used.

In the circuits shown in FIGS. 1A and 1B, the area required for each memory cell can obviously be significantly reduced. Compared to an actual layout with a conventional six-transistor SRAM, this reduction can exceed 50%, and typically could be reduced by as much as 70%. Thus, larger memories can be used instead of conventional memories without increasing the size. Greater functionality and reduced costs.

In the circuits of FIGS. 1A and 1B, transistors are used to drive bit lines. As a result, the design of sense amplifiers used with memory cells is much less restrictive than conventional memory cells. That is, since the precharge bit line is pulled down, a considerably large voltage change is sensed by the sense amplifier. Memory cells operate by dynamically charging a node through an access transistor. An excellent zero level cannot be obtained due to the large threshold voltage of the access polysilicon p-channel TFT. Normally, the threshold voltage of a polysilicon TFT is typically in the range of 1.5 to 2.0 volts, so that charge storage is difficult. This problem can be overcome by applying the driving circuit shown in FIG.

The circuit of FIG. 2 is a bootstrap word line driver. This functions to drive the word line at a threshold voltage below 0 volts. This assures excellent 0 volt level writing to memory cells.
Of course, if the memory cell is configured using n-type transistors, the word lines will be driven at a voltage higher than 5 volts rather than at a voltage lower than 0 volts. Even if bootstrap circuit is old style NM
Even when used in conjunction with an OS circuit, this circuit is not conventionally used in polysilicon circuits.

When the "0" value of the cell is read, the bit line is slowly pulled high by the memory cell storage transistor. When the cell "1" is read, the storage of the memory cell is held off and the bit line floats. Therefore, the bit lines must be precharged to zero and discharged before each read. Care is taken to ensure that the bit lines are properly pulled low before release, regardless of manufacturing tolerances. Thus, the design must provide a maximum tolerance that results in a much slower read cycle, even if current transistors can operate faster. This problem can be avoided by applying a self-time (self-time adjustment) bit line driver. In essence, the bootstrap circuit is used to precharge the word line, and when this is done the driver is turned off and the cell can be read. However, it is important to match the timing. In particular,
The switching speed of the transistor is easy to change, so that even if the typical speed of the switching is 50 ns, before the driver is switched off, 100 n
The operation of s will be done carefully. However, this results in a memory operating speed that is probably much slower than actually needed.

In an embodiment of the present invention using p-type transistors, a dummy bit line (having the same characteristics as the other bit lines) is also provided and activated low. When this dummy bit line reaches zero, the word line driver is turned off. Thus, tracking is assured with process variations, and the memory operates as quickly as possible without unnecessarily wasting processing speed.

The operation of the circuit shown in FIG. 2 will now be described. First, assume that the output, WL, is high. When the input drops, the output pull-up transistor (10) is turned off via the first inverter stage (12). The pull-down transistor (14) is turned on. Next, when the output goes low, the pull-down transistor (14) is turned off via the second inverter stage (16) and the NOR gate (18). Thus, the output is no longer driven. At this point, after a short delay introduced by the three series connected inverters (20, 22, 24), the bottom plate of the capacitor (26) is driven low. Thus, the output is forcibly reduced to zero or less.

FIG. 3 is a circuit diagram of a self-time adjustment bit line driver suitable for use with the circuit of FIG. This driver drives the bit line via the signal BLPD. This receives the "read" signal applied to NOR gate 30 via inverter 28. NOR gate 3
0 also receives an "address" input signal. Output of NOR gate 30 to dummy bit line (to D-BL)
It is applied via an inverter stage 42 and to the NOR gate 34 via an inverter 32. NO
R gate 34 also receives an input signal (from D-BL) from the dummy bit line via inverter 36.
Signal BLPD is derived from NOR gate 34 via two serially connected inverters 38 and 40.

The basic operating requirements of the circuit shown in FIG. 3 are that the bit line must be driven low before each read cycle and then (BLPD driven low). Must be released). Thus, the BLPD is used to pull down the dummy bit line. The signal BLPD is disabled only when the dummy bit line is forced low. An inverter 36 monitors the value of the dummy bit line and satisfies the skewed pn transistor ratio to ensure a low switching threshold.

Within the scope of the present invention, there are various modifications of the embodiments described with reference to the drawings, which will be apparent to those skilled in the art.

[Brief description of the drawings]

FIG. 1A is a circuit diagram illustrating an N-type transistor circuit configuration according to an embodiment of the present invention, and FIG. 1B is a circuit diagram illustrating a P-type transistor circuit configuration according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a circuit configuration of a driver circuit to be used together with the circuit shown in FIG.

FIG. 3 is a circuit diagram showing a circuit configuration of another driver circuit used in combination with the circuit shown in FIG. 1;

[Explanation of symbols]

 Reference Signs List 10 output pull-up transistor 12 first inverter 14 pull-down transistor 16 second inverter 18 NOR gate 20, 22, 24 inverter 26 capacitor 28 inverter 30 NOR gate 32 inverter 34 NOR gate 36, 38, 40, 42 inverter

Claims (11)

[Claims] 1. A first transistor operating on a read line, a word line, and a bit line, connected between a bit line and a word line, a second transistor connected between a bit line and a read line, and other transistors. A dynamic random access memory cell comprising a third transistor connected between two transistors and storing charge. 2. The memory cell according to claim 1, wherein said transistor is a thin film transistor. 3. The memory cell according to claim 1, wherein said transistor is formed of polysilicon. 4. The memory cell according to claim 1, wherein said transistor is formed from a p-type material. 5. A dynamic random access memory device comprising a plurality of memory cells according to claim 1. 6. The memory device according to claim 5, further comprising a bootstrap word line driver. 7. The memory device according to claim 5, further comprising a self-timed bit line driver. 8. The memory device according to claim 7, wherein said automatic time adjustment bit line driver includes a dummy bit line. 9. A method for connecting a first transistor between a bit line and a word line, a method for connecting a second transistor between the bit line and a read line, and a method for connecting a third transistor to the first two transistors. A method for manufacturing a dynamic random access memory storage device, comprising: 10. The method of claim 9, further comprising the step of precharging the bit lines prior to reading. 11. Providing a dummy bit line;
The method of claim 11, further comprising: precharging the dummy bit line with the bit line; and turning off the bit line driver when the dummy bit line is determined to be charged.