JP2001282711A - Data transfer controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the capacity of a buffer memory device. SOLUTION: This device has a data size acquiring means 17 for acquiring data size from a peripheral device 3, required buffer memory number calculating means 11 for calculating the number of buffer memories required for transferring data on the basis of the data size acquired thereby, predictive securable buffer memory number calculating means 12 for calculating the predictive number of securable buffer memories showing the predictive number of securable buffer memories on the basis of the performance difference of data transfer between an information processor 2 and the peripheral device 3 and buffer memory securing means 13 for securing the buffer memories when the predictive number of securable buffer memories calculated thereby reaches the number of required buffer memories calculated by the required buffer memory number calculating means 11, and parallel transfers a plurality of data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control device for reading image data from a peripheral device in units of one image based on a data transfer request from an information processing device such as a host computer and transferring the read image data to the information processing device. .

[0002]

2. Description of the Related Art In a data transfer control device of this type, data is output in a predetermined data amount unit, that is, when transferring data from a peripheral device which cannot stop outputting a predetermined data amount in the middle. There is a disadvantage that a part of the data may be lost due to a delay in the timing of acquiring the data from the transfer performance and processing status of the information processing apparatus and the transfer environment. In order to solve this drawback, a data transfer control device described in Japanese Patent Application Laid-Open No. Hei 3-13195 has been proposed. The data transfer control device described in Japanese Patent Application Laid-Open No. HEI 3-13195 is a system for mutually transmitting and receiving data between a first control device and a second control device via a buffer memory. A two-sided buffer memory that can be connected to any of the two control devices and that can be read and written between the devices, and a switch that alternately connects these buffer memories to the two control devices so as to have a reciprocal relationship to each other. And means.

[0003]

However, in the data transfer control device described in Japanese Patent Application Laid-Open No. Hei 3-13195, two buffer memories are required as the buffer memory device, so that the buffer memory device has a large capacity. There is a problem that becomes. An object of the present invention is to solve such a problem. That is, an object of the present invention is to provide a data transfer control device capable of reducing the capacity of a buffer memory device.

[0004]

According to a first aspect of the present invention, there is provided an apparatus for controlling writing and reading of data to and from a plurality of buffer memories based on a data transfer request from an information processing apparatus. A data transfer control device that reads data from a peripheral device in units of a predetermined data amount and transfers the data to the information processing device, wherein the data size obtaining device obtains a data size from the peripheral device; A required buffer memory number calculating means for calculating the number of required buffer memories required for the data transfer based on the data size obtained by the method, and a performance difference between the data transfer performance of the information processing device and the peripheral device. Calculates the estimated number of buffer memory that can be allocated by calculating the estimated number of buffer memory that can be allocated. A measurement calculation unit, and the buffer memory when the predicted number of buffer memory securable calculated by the buffer memory reservable predicted number calculation unit reaches the number of the required buffer memory calculated by the required buffer memory number calculation unit. And a buffer memory securing means for securing a plurality of data, and transferring a plurality of data in parallel. The invention according to claim 2 is the data transfer control device according to claim 1, wherein the buffer memory to be reserved is written from the peripheral device to the buffer memory without being released by the buffer memory reservable predicted number calculating means. When unread data that cannot be read is generated, the buffer memory that rewrites the buffer memory for writing the unread data while reading the data already written to the buffer memory from the buffer memory and transferring the data to the information processing device is re-secured. Means, retransmission request means for requesting the peripheral device to retransmit the unread data when the buffer memory is reallocated by the buffer memory reallocating means, and the unread requesting retransmission by the retransmission request means. Having retransmission data writing means for writing data to the buffer memory. And butterflies.

According to a third aspect of the present invention, there is provided the data transfer control device according to any one of the first and second aspects, wherein the buffer memory reservable predicted number calculating means comprises: Input processing time measuring means for measuring an input processing time required for writing data for each
The input performance holding unit that holds the minimum value of the input processing time as the input performance, and the input processing time from the input processing time measuring unit is compared with the input processing time held by the input performance holding unit. A minimum value selection unit that selects a minimum value and holds the input performance holding unit as the input performance, and an output processing time measurement unit that measures an output processing time required for reading data for each of the buffer memories;
Output performance holding means for holding an average value of the output processing time as output performance; and the new output processing based on the output processing time from the output processing time measuring means and the output performance from the output performance holding means. An average value calculating means for calculating an average value of time and holding the output performance holding means as the output performance, and a performance ratio based on the output performance from the output performance holding means and the input performance from the input performance holding means. , A performance ratio holding unit that holds the performance ratio from the performance ratio calculation unit, information indicating a correspondence relationship between a performance ratio and a predicted number of buffer memory securable units, and the performance ratio holding unit. And a buffer memory reservable predicted number output means for obtaining and outputting a buffer memory reservable predicted number based on the performance ratio from

[0006]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a data transfer control device according to one embodiment of the present invention. FIG. 2 is a block diagram showing a control unit of the data transfer control device shown in FIG. As shown in FIG. 1, a data transfer control device 1 includes an information processing device 2 such as a host computer.
And the peripheral device 3. The peripheral device 3
The data is output in a predetermined data amount unit. The data transfer control device 1 reads a plurality of data from the peripheral device 3 in parallel in a predetermined data amount unit based on a data transfer request from the information processing device 1 and transfers the data to the information processing device 2 in parallel. The data transfer control device 1 includes a control unit 4
, A buffer memory device 5, and switching control units 6, 7
And input / output control units 8 and 9. The control unit 4
It is connected to a buffer memory device 5, switching control units 6 and 7, and input / output control units 8 and 9. The switching controllers 6 and 7 are connected to the buffer memory device 5. The input / output control unit 8 is connected between the switching control unit 6 and the information processing device 2. The input / output control unit 9 includes the peripheral device 3
And the switching control unit 7. Control unit 4
Is a buffer memory device 5 and switching control units 6 and 7
And the input / output control units 8 and 9 are controlled. The control unit 4 determines that C
It is composed of a PU and a memory. The buffer memory device 5 temporarily stores data to be transferred.
The switching controllers 6 and 7 arbitrate the interface for each buffer memory of the buffer memory device 5. The input / output control unit 8 sends and receives commands and data to and from the information processing device 2. The input / output control unit 9 sends and receives commands and data to and from the peripheral device 3.

As shown in FIG. 2, the control unit 4 comprises a data size obtaining means 10 and a necessary buffer memory number calculating means 1.
1, a buffer memory allocable predicted number calculating means 12,
It has a buffer memory securing unit 13, a buffer memory re-securing unit 14, a retransmission request unit 15, and a retransmission data writing unit 16. The required buffer memory number calculation unit 11 is connected to the data size acquisition unit 10.
The buffer memory securing means 13 is connected to the required buffer memory number calculating means 11 and the buffer memory reservable predicted number calculating means 12. Buffer memory re-securing means 1
4 is connected to the buffer memory securing means 13. The retransmission request unit 15 is connected to the buffer memory re-securing unit 14. The retransmission data writing unit 16 is connected to the retransmission request unit 15. The data size obtaining unit 10 obtains a data size from the peripheral device 3 via the input / output control unit 9. The required buffer memory number calculation means 11 calculates the number of required buffer memories required for data transfer based on the data size acquired by the data size acquisition means 10. The buffer memory reservable predicted number calculating means 12 calculates the buffer memory reservable predicted number indicating the buffer memory reservable predicted number based on the data transfer performance difference between the information processing device 2 and the peripheral device 3. The buffer memory reserving means 13 is adapted to renew the buffer memory when the predicted buffer memory reservable number calculated by the buffer memory reservable predicted number calculating means 14 reaches the required buffer memory number calculated by the required buffer memory number calculating means 11. Secure. The buffer memory re-securing means 14 stores the unread data that cannot be written from the peripheral device 3 into the buffer memory without releasing the buffer memory to be reserved by the buffer memory reservable predicted number calculating means 13. While the written data is read from the buffer memory and transferred to the information processing device 2, the buffer memory for writing the unread data is re-secured. The retransmission request unit 15 requests the peripheral device 3 to retransmit unread data when the buffer memory is reallocated by the buffer memory reallocating unit 14. The retransmission data writing unit writes the unread data requested to be retransmitted by the retransmission request unit 15 to the buffer memory. In the control unit 4, the CPU executes the operations of the above-described units based on a program stored in the memory.

FIG. 3 is a block diagram showing the buffer memory device 5 of the data transfer control device 1 shown in FIG. As shown in FIG. 3, the buffer memory device 5 includes six buffer memories BM0, BM1, BM2, BM3, BM4, and BM.
5, six secure flags A and six active flags B
And six direction flags C. Each of the buffer memories BM0 to BM5 has the same capacity. The reservation flag A indicates reservation or release for each of the buffer memories BM0 to BM5. When the reservation flag A is 1, it indicates that the control unit 4 has reserved the buffer memories BM0 to BM5. When the securing flag A is 0, it indicates that the control unit 4 has released each of the buffer memories BM0 to BM5. The active flag B is stored in each of the buffer memories BM0 to BM5.
Indicates whether or not is active. When the active flag B = 1, it indicates that each of the buffer memories BM0 to BM5 is active. When the active flag B = 0, it indicates that the buffer memories BM0 to BM5 are not active (standby). The direction flag C indicates the direction of writing or reading data to or from each of the buffer memories BM0 to BM5. When the direction flag C = 0, it indicates the direction of data writing to each of the buffer memories BM0 to BM5. When the direction flag C = 1, the direction of reading data from each of the buffer memories BM0 to BM5 is indicated. Here, a combination of the reservation flag A, the active flag B, and the direction flag C is used as a buffer status flag (A, B, C). Buffer status flags (A, B,
C) = (0,0,0) indicates release of the buffer memory.
The buffer status flag (A, B, C) = (1, 0, 0) indicates that the buffer memory is waiting to write data. The buffer status flag (A, B, C) = (1, 0, 1) indicates that the buffer memory is waiting to read data. The buffer status flag (A, B, C) = (1, 1, 0) indicates that data is being written to the buffer memory. The buffer status flag (A, B, C) = (1, 1, 1) indicates that data is being read from the buffer memory.

Next, a first embodiment of the present invention will be described in detail with reference to the drawings. Here, it is assumed that the buffer memory capacity (buffer memory size) of each of the buffer memories BM0 to BM5 is 200 KB, the performance ratio is 2.0 (see FIG. 9), and the data capacity is 800 KB. FIG. 4 is a diagram illustrating one state of data transfer in the buffer memory device 5 of the data transfer control device 1. FIG. 5 is a diagram for explaining another state of data transfer in the buffer memory device 5 of the data transfer control device 1. FIG. 6 is a diagram for explaining another state of data transfer in the buffer memory device 5 of the data transfer control device 1. FIG. 7 is a flowchart for explaining a process of writing one data by the data transfer control device 1. FIG. 8 is a flowchart for explaining the reading process of the data transfer control device 1. Next, a process of writing one data by the data transfer control device 1 will be described with reference to FIG. FIG.
As shown in (1), when the data transfer control device 1 performs the writing process, if the information processing device 2 instructs the transfer of the page 1 and the page 2 as the data request in the step 101, the control unit 4 performs the process in the step 101. Acquires the data size from the peripheral device 3 and then calculates the required number of buffer memories corresponding to the data size acquired in step 102. In this case, the number of required buffer memories is E,
Assuming that the data amount of one page is F and the capacity of one buffer memory is G, the required buffer memory number E
Is obtained by the following equation (1). E = F ÷ G (rounded up below the decimal point) (1) For page 1, the required buffer memory number E is “4”. Next, in step 103, the estimated number of buffer memory reservables is calculated by equations (2) and (3). This calculation method will be described later in detail. Next, in step 104, the control unit 4 determines whether or not the estimated number of buffer memories that can be secured ≧ the number of necessary buffer memories. The control unit 4 waits until the predicted number of buffer memory securable ≧ the required number of buffer memories. When it is determined in step 104 that the number of buffers that can be reserved is equal to or greater than the required number of buffer memories, in step 105, the control unit 4 reserves a buffer memory area. In the case of page 1 data transfer processing, the predicted number of buffer memories that can be secured is larger than the required number of buffer memories.
It is ensured that M0 to BM3 are waiting for writing.

Next, at step 106, the control unit 4 performs a writing process and goes to step 107. Step 107
Then, the control unit 4 determines whether or not the writing process is waiting. If it is determined in step 107 that the process is not waiting for a write process, the operation ends. At the start and end of the write process in step 106, the control unit 4 performs a process of switching between the securing flag A, the active flag B, and the direction flag C of the memory device 5. If the writing process is waiting in step 107, it is determined in step 108 whether or not there is an unsecured buffer memory. If there is no unsecured buffer memory in step 108, the process returns to the write process in step 106. If there is an unsecured buffer memory in step 108, the control unit 4 determines in step 109 whether there is an open buffer memory. If there is an open buffer memory in step 109, the process returns to step 106. If there is no open buffer memory in step 109, the control unit 4 performs an overflow process in step 110. Next, in step 111, the control unit 4 determines whether or not the operation is to be ended, and ends the operation when the operation is to be ended. The overflow processing in step 110 will be described later in detail. next,
The reading process of the data transfer control device 1 will be described with reference to FIG. In step 201, the control unit 4 obtains information waiting for a reading process of the buffer memory from the memory device 5, and determines whether or not there is a buffer memory waiting for the reading process. If there is a buffer memory waiting to be read in step 201, the control unit 4 performs read processing in step 202 and transfers data to the information processing device 2, and then proceeds to step 203. In step 203, the control unit 4
Judge whether or not it is the end. If it is not finished in step 203, the process returns to step 202, and if it is finished in step 203, the operation is finished. At the start and end of the reading process in step 202, the control unit 4 performs a switching process of the securing flag A, the active flag B, and the direction flag C of the memory device 5. FIG. 4 is a diagram illustrating one state of data transfer of the buffer memory device 5.
FIG. 5 is a diagram for explaining another state of data transfer of the buffer memory device 5. In the example shown in FIG. 4, four buffer memories BM0 to BM3 are reserved for page 1. The buffer memory BM0 is executing the read process, the buffer memory BM1 is waiting for the read,
The buffer memory BM2 is writing, and the buffer 3
Is waiting for writing. In the example shown in FIG. 5, since the reading of the buffer memory BM0 is completed and the number of open buffers becomes three, the buffer area of the page 2 is reserved and the three buffer memories BM4 and BM of the page 1 are reserved.
5, BM0 is secured and one buffer memory cannot be secured, and the state is unsecured.

Next, the overflow processing in step 110 will be described with reference to FIG. In FIG. 5, when the writing of the data of page 2 to the buffer memory BM0 is completed without the writing to the buffer memory BM1, the remaining 200 KB of data overflows and is lost. Become. In this case, as shown in FIG. 6, an instruction for reserving a buffer memory and retransmitting data to the peripheral device 3 is performed again, and a read process is executed for the buffer memory that has already been written, and Do not enter Final 2 of untransferred data
The error recovery of the data is performed by performing the writing process to the buffer memory BM1 when 00KB comes. FIG. 9 is a block diagram showing the buffer memory reservable predicted number calculating means 12 in the control unit 4 of the data transfer control device 1. As shown in FIG. 9, the buffer memory reservable predicted number calculating unit 12 includes an input processing time measuring unit 17.
Input performance holding means 18, minimum value selecting means 19,
Output processing time measuring means 20 and output performance holding means 21
, Average value calculating means 22, and performance ratio calculating table 23
And a performance ratio calculating means 24, a performance ratio holding means 25, a buffer memory reservable predicted number calculation table 26, and a buffer memory reservable predicted number output means 27. The minimum value selecting means 19 is provided for the input processing time measuring means 17.
It is connected to the. The input performance holding unit 18 is connected to the minimum value selecting unit 19. The average value calculation means 22
It is connected to the output processing time measuring means 20. The output performance holding means 21 is connected to the average value calculating means 22. The performance ratio calculation unit 24 is connected to the input performance holding unit 18, the output performance holding unit 21, and the performance ratio calculation table 23. The performance ratio holding unit 25 is connected to the performance ratio calculation unit 24. The buffer memory reservable predicted number output unit 27 is connected to the performance ratio holding unit 25 and the buffer memory reservable predicted number calculation table 26.

The input processing time measuring means 17 measures the input processing time required for writing data for each of the buffer memories BM0 to BM5. Since the input processing time indicates the data transfer performance of the peripheral device 3, the input processing time measuring means 17 measures the data transfer performance of the peripheral device 3. The input performance holding means 18
The minimum value (input performance) of the input processing time from the minimum value selection means 19 is held. The minimum value selecting unit 19 is configured to input the processing time from the processing time measuring unit 17 and the input processing time (input performance) held by the input performance holding unit 18.
And the minimum value is selected and given to the input performance holding means 18 to be held. The output processing time measuring means 20 measures an output processing time required for reading data for each of the buffer memories BM0 to BM5. Since this output processing time indicates the data transfer performance of the information processing device 2,
This means that the output processing time measuring means 20 measures the data transfer performance of the information processing device 2. The output performance holding unit 21 holds an average value (output performance) of the output processing time. The average value calculating means 22 calculates a new average value (output performance) of the new output processing time based on the output processing time from the output processing time measuring means 20 and the average value of the output processing time from the output performance holding means 21. Output performance holding means 21
And hold it. The performance ratio calculation table 23 stores a calculated value of a performance ratio, which is a ratio between output performance and input performance, and information indicating a relationship between the calculated value of the performance ratio and a corresponding plurality of stages of performance ratios. The performance ratio calculating means 24 calculates the average value of the output processing time from the output performance holding means 21 (output performance).
And a calculated value of a performance ratio, which is a ratio between the output performance and the input performance, based on the input processing time (input performance) from the input performance holding unit 18. A conversion value of the performance ratio is calculated based on the performance ratio.
The performance ratio holding unit 25 holds the performance ratio from the performance ratio calculation unit 24. The buffer memory reservable predicted number calculation table 26 stores information on the correspondence between the performance ratio and the buffer memory reservable predicted number. The buffer memory reservable predicted number output means 27 calculates and outputs the buffer memory reservable predicted number based on the performance ratio from the performance ratio holding means 25 and the information of the buffer memory reservable predicted number table 26.

Next, a specific calculation example of the performance ratio calculating means 24 and the buffer memory securable predicted number output means 27 will be described with reference to FIGS. 10 and 11. FIG. FIG. 10 is a diagram for explaining the performance ratio calculation table 23 in the buffer memory allocable predicted number calculation means 12 of the data transfer control device 1. FIG. 11 is a diagram for explaining the buffer memory allocable predicted number table 20 in the buffer memory allocable predicted number calculation means 12 of the data transfer control device 1. As shown in FIG. 10, the performance ratio calculation table 23 includes information indicating a calculated value of a performance ratio, which is a ratio of output performance to input performance, and a relationship between the calculated value of the performance ratio and a plurality of stages of performance ratios corresponding thereto. Is stored. Performance ratio calculation means 24
Is a calculation of a performance ratio, which is a ratio between output performance and input performance, based on an average value (output performance) of output processing time from output performance holding means 21 and input processing time (input performance) from input performance holding means 18. A value is obtained, and a converted value of the performance ratio is calculated based on the calculated value of the performance ratio and the information of the performance ratio calculation table 23. As shown in FIG. 11, the buffer memory reservable predicted number calculation table 26 stores information on the correspondence between the performance ratio and the buffer memory reservable predicted number. The buffer memory reservable predicted number output means 27 obtains and outputs the buffer memory reservable predicted number based on the performance ratio from the performance ratio holding means 24 and the information of the buffer memory reservable predicted number table 26.

When estimating the number of buffer memories to be released from the number of open buffer memories and the performance ratio, the following equation 2 is used. Q = N + (N ÷ S) + ((N ÷ S) ÷ S) (2) Here, Q indicates the predicted number of buffers that can be secured, and S
Indicates the performance ratio, N indicates the current number of released buffer memories, N ÷ S indicates the secondary released number of buffer memory that occurs when data of the current released buffer memory is processed, and (N ÷ S ) ÷ S indicates the number of tertiary releases of the buffer memory that occur when processing the buffer memory of the secondary release. Therefore, the value obtained by calculating N by the following equation 3 and rounding up the calculated value after the decimal point is the value of the buffer memory allocable predicted number calculation table 26. N = (S × S × Q) ÷ ((S × S) + S + 1) (3) If the predicted number of allocable buffer memories is equal to or greater than the required number of buffer memories, a reservation process for allocating buffer memories is started.

[0015]

As described above, according to the first aspect of the present invention, there is provided the buffer memory securing means for securing the buffer memory when the predicted number of buffer memory secureable reaches the required number of buffer memories. Since a plurality of data are transferred in parallel, it is possible to set the estimated number of buffers that can be secured according to the transfer performance of the information processing device and the peripheral device, so that the capacity of the mounted buffer memory device can be reduced. Can be. According to the second aspect of the present invention, in addition to the effect of the first aspect, when unread data occurs, data already written in the buffer memory is read out from the buffer memory and transmitted to the information processing apparatus. Since unread data can be written while being transferred, data overflow processing can be performed with reduced output loss time to the information processing device. According to the invention set forth in claim 3, claim 1 or 2
In addition to the effects of the invention described in any one of the claims,
By calculating the estimated number of buffers that can be secured in the buffer memory in real time from the difference in transfer performance between the information processing device and the peripheral device and using the buffer memory appropriately, the frequency of occurrence of data overflow can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a data transfer control device according to one embodiment of the present invention.

FIG. 2 is a block diagram showing a control unit of the data transfer control device shown in FIG.

FIG. 3 is a block diagram showing a buffer memory device of the data transfer control device shown in FIG. 1;

FIG. 4 is a diagram illustrating one state of data transfer in the buffer memory device of the data transfer control device shown in FIG.

FIG. 5 is a diagram illustrating another state of data transfer in the buffer memory device of the data transfer control device shown in FIG. 1;

6 is a diagram illustrating another state of data transfer in the buffer memory device of the data transfer control device shown in FIG.

FIG. 7 is a flowchart for explaining a process of writing one data by the data transfer control device shown in FIG. 1;

FIG. 8 is a flowchart for explaining a read process of the data transfer control device shown in FIG. 1;

9 is a block diagram showing a buffer memory reservable predicted number calculating means in the control unit of the data transfer control device shown in FIG. 1;

10 is a diagram illustrating a performance ratio calculation table in a buffer memory reservable predicted number calculation unit illustrated in FIG. 9;

11 is a view for explaining a buffer memory allocable predicted number calculation table in a buffer memory allocable predicted number calculation means shown in FIG. 9;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 data transfer control device, 2 information processing device, 3 peripheral device, 4 control unit, 5 buffer memory device, 6, 7 switching control unit, 8, 9 input / output control unit, 10 data size acquisition unit, 11 required buffer memory number Calculation means, 1
2 Buffer memory reservable predicted number calculating means, 13 Buffer memory reserving means, 14 Buffer memory re-securing means, 15 Retransmission requesting means, 16 Retransmission data writing means, 17 Input processing time measuring means, 18 Input performance holding means, 19 Minimum value Selecting means, 20 output processing time measuring means, 21 output performance holding means, 22 average value calculating means, 23 performance ratio calculating table, 24 performance ratio calculating means, 25 performance ratio holding means, 26 buffer memory reservable predicted number calculating table, 27 A buffer memory allocable predicted number output means.

Claims (3)

[Claims] An information processing apparatus controls writing and reading of data to and from a plurality of buffer memories based on a data transfer request from an information processing apparatus, reads data from a peripheral device in a predetermined data amount unit, and transfers the data to the information processing apparatus. A data size control unit for obtaining a data size from the peripheral device, and a necessary buffer memory required for transferring the data based on the data size obtained by the data size obtaining unit. Buffer memory number calculating means for calculating the number of buffer memories, and a buffer memory for calculating a buffer memory allocable predicted number indicating a buffer memory allocable predicted number based on a data transfer performance difference between the information processing device and the peripheral device Means for calculating the estimated number of allocable buffers and Buffer memory securing means for securing the buffer memory when the issued buffer memory secureable predicted number reaches the number of the necessary buffer memories calculated by the required buffer memory number calculating means. A data transfer control device for transferring data in parallel. 2. The data transfer control device according to claim 1, wherein the buffer memory scheduled to be reserved is not released by the buffer memory reservable predicted number calculating means, and the unread data cannot be written from the peripheral device to the buffer memory. Buffer memory re-securing means for re-securing a buffer memory for writing the unread data while reading data already written in the buffer memory from the buffer memory and transferring the data to the information processing device when data is generated; Retransmission requesting means for requesting the peripheral device to retransmit the unread data when the buffer memory is reallocated by the buffer memory reallocating means; and transmitting the unread data requested to be retransmitted by the retransmission requesting means to the buffer. Retransmission data writing means for writing to a memory. Data transfer control device. 3. The data transfer control device according to claim 1, wherein said buffer memory reservable predicted number calculating means is required for writing data for each of said buffer memories. An input processing time measuring unit that measures an input processing time, an input performance holding unit that holds a minimum value of the input processing time as input performance, and an input processing time from the input processing time measuring unit and the input performance holding unit. The minimum value selecting means for comparing the held input processing time with the input processing time and selecting the minimum value and holding the input performance holding means as the input performance, and the output processing time required for reading data for each of the buffer memories. Output processing time measuring means for measuring; output performance holding means for holding an average value of the output processing time as output performance; An average value calculating unit that calculates an average value of the new output processing time based on the output processing time from the stage and the output performance from the output performance holding unit and holds the output performance time as the output performance in the output performance holding unit; A performance ratio calculating unit that calculates a performance ratio based on the output performance from the output performance holding unit and the input performance from the input performance holding unit, and a performance ratio that holds the performance ratio from the performance ratio calculating unit. Holding means, a buffer memory reservable prediction for obtaining and outputting a buffer memory reservable predicted number based on the information indicating the correspondence relationship between the performance ratio and the buffer memory reservable predicted number and the performance ratio from the performance ratio retaining means A data transfer control device, comprising: a number output unit.