JP2001282198A - Method for preventing malfunction of programmable display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to eliminate not only unexpected noise but also cyclic noise, and to effectively prevent backlight 24 from flickering erroneously by relatively simple configuration, in a separation type programmable display device 14 of which the display part 16 and the device body 18 are separated from each other. SOLUTION: In the case of sampling flickering signals of the backlight 24 to be inputted into the display part 16, the sampling time intervals are made to be irregular, and after it is judged that a same signal level has been maintained plural times successively, the signal level state is settled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for preventing malfunction due to noise in various types of display devices for industrial use or home use.

[0002]

2. Description of the Related Art Conventionally, this type of malfunction prevention method is generally performed by inserting a noise filter into a signal input portion while applying an electromagnetic shield to a housing housing an electronic circuit. Also, as a noise filter in a digital circuit, the level state of an input signal is sampled at a predetermined constant cycle, and when it is determined that a signal having the same level state has been input a predetermined number of times continuously, the signal state is determined. Filter devices have also been used.

[0003]

However, such a method of removing noise can prevent malfunctions to some extent in a normal sudden noise generation environment, but can cause malfunctions in factories and the like where motors are frequently used. known.

The inventor of the present invention has considered this disadvantage, and as a result, the motor generates pulse-like noise at a constant period. To take in only noise.

The present invention has been made based on such knowledge, and it is an object of the present invention to provide a malfunction preventing method capable of effectively removing not only suddenly generated noise but also periodically generated noise. .

[0006]

A method for preventing malfunction according to the present invention is shown in FIG.
The present invention is applied to a programmable display device which is connected to a predetermined external device such as 12 and enables display corresponding to a control operation performed by the external device.

Then, the level of the input signal is sampled at minute intervals, and when it is determined that the same signal state has been maintained for the set number of times, the signal state is determined, and signal processing corresponding to the determined signal state is performed. In the signal processing step, the time is set so that all the time intervals are not the same when sampling the set number of times.

The above-mentioned sampling operation is performed by interruption by a timer as shown in FIG.
Each time the interruption is performed, the interruption time of the timer can be changed.

Further, as shown in FIG.
A flip-flop group in which type flip-flops 46 are connected in series and an AND circuit 56 are provided. A signal A to be processed is input to the flip-flop group, and output from the clock signal generator 58 to the flip-flop 46 at each stage. It is also possible to apply a clock signal as it is or by dividing the clock signal C to perform a data sampling operation.

In this case, the signals output from the flip-flops 46 of the respective stages are individually input to the AND circuit 56, and signal processing corresponding to the state of the output signal B from the AND circuit 56 is performed. The generation period of the clock signal C output from the clock signal generator 58 is set to be sufficiently shorter than the generation period of the noise whose input is expected, while the clock signal C1 for driving the flip-flop 46 of each stage is The division ratios of C2 and C3 are made different from each other.

Also, as shown in FIG.
, The signal A to be processed is input in parallel to each flip-flop 46, while the clock signal can be input to the next-stage flip-flop 46 only when the output signal B from the preceding flip-flop 46 is significant. In addition, the frequency division ratio of the flip-flop 46a at the uppermost stage can be configured to be maximum.

As shown in FIG. 1, the display unit 14 has a structure in which the display unit 16 and the apparatus main body 18 are separated from each other via a relatively long connection line 28, and the display unit 16 can be installed at an arbitrary position. The display unit 16 is provided with a backlight 24 on the back side of a display 20 such as a liquid crystal display panel. It is preferably applied to a blink signal sent from the main body 18 to the backlight 24.

[0013]

As described above, according to the present invention, when the input signal is sampled, the time interval during the sampling is not constant, so that not only suddenly generated noise but also periodically generated noise can be obtained. Can be effectively removed, and malfunction of the circuit can be prevented.

Further, in a separate type programmable display device 14 in which the display section 16 and the apparatus main body 18 are separated, a backlight 24 input into the display section 16 is provided.
Erroneous blinking of the backlight 24 can be effectively prevented with a relatively simple configuration.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A malfunction prevention method according to the present invention will now be described with reference to FIG.
PLC12 specially designed for sequence control
Will be concretely described based on an example implemented on a program-type display device 14 which is connected as an external device and performs display and control corresponding to data handled therein. However, it is needless to say that the present invention can be carried out in substantially the same manner by using a general-purpose or special-purpose computer or other control device, or a device that controls the operation of various electric appliances in the home.

The programmable display device 14 includes a PLC 12
In addition, they are integrated into an operation console or the like of the target system 10 or are independently provided, and are used as an operation and display panel for the target system 10.

PLC for controlling the target system 10
Reference numeral 12 denotes a unit realized by a unit formed of a circuit for each required function such as a CPU unit and a memory unit, and by connecting the respective units in parallel so as to be able to increase or decrease as necessary. The configuration is substantially the same as that of the related art that can be changed.

The storage locations of various information input / output to / from the target system 10 are various sensors, passive components such as level gauges and limit switches, relays and motors provided on the target system to be controlled or displayed. A word device is specified for word data such as numerical values, and a bit device is specified for bit data such as on / off information. You. Further, by preliminarily setting a device address such as “D100” specific to each device in advance, data necessary for specifying a storage location by designating the device address is stored in the memory unit.

Therefore, only by specifying a device address to access an arbitrary word device or bit device in the memory unit from inside or outside of the PLC 12 and without knowing the actual address in the PLC, the correspondence of the target system 10 can be obtained. The position is controlled or data relating to the operation state can be individually taken out.

On the other hand, the programmable display device 14 includes one or a plurality of display units 16 arranged at a place where an operator should actually operate, such as the periphery of the target system 10, and a PL.
And an apparatus main body 18 disposed at a predetermined position such as near C12.

The display section 16 has a display screen using, for example, a liquid crystal display device as a display 20 disposed on the front side of a substantially rectangular main body case, and a touch panel 22 disposed in close contact with the display screen. I have. Further, a backlight 2 is provided on the back side of the display 20.
4 is provided to illuminate the display 20.

On the other hand, a display control circuit 26 is housed inside the apparatus main body 18, and the apparatus main body 18 and the display section 16 are provided.
The connection between the display unit 16 and the apparatus main body 18 is enabled by connecting them with a connection line 28 in a wired or wireless state. A display corresponding to the control state of the PLC 12 is performed on the display screen of the display 20, and at the same time, data input by a fingertip via the touch panel 22 and control of the PLC 12 are performed by the connection line 28.
To be possible through.

The display control circuit 26 is basically substantially the same as a personal computer as shown in FIG. 1, and includes a CPU 30 as a control center and a bus line 32 such as an address bus, a data bus or a control bus. Various types of memories such as a RAM 34 and a ROM 36 or a graphic controller 38 are connected via the CPU 30, and the result of data processing by the CPU 30 is developed on a video RAM 40 via the graphic controller 38.

Further, the data developed on the video RAM 40 is output from the graphic controller 38 as a video signal, input to the display unit 16 via the connection line 28, and then displayed on the display 20 in the display unit 16 for display processing. You.

Here, the display section 16 has an I-input on its signal input side.
After performing predetermined data processing on a signal input from the I / O controller 44 or the graphic controller 38 on the device main body 18 side, a signal is sent to each unit provided inside the display unit 16, Perform a predetermined operation.

The present invention has a feature in the signal processing operation in the I / O circuit 42, and the contents of the operation will be described in further detail with reference to the flowchart shown in FIG.

First, when the display section 16 is started in step 1, a predetermined initialization operation such as resetting a counter is performed in step 2, and then the main routine of step 3 is executed.

The main routine includes an operation for converting the video signal into a signal that can be displayed on the display 20, a signal output from the touch panel 22 according to a predetermined format, and a signal output from the apparatus main body 18. An operation of turning on or off the backlight 24 according to the level of the sent blink signal is included.

At the same time that the series of data processing operations in step 3 are performed as required, a timer interrupt is generated in step 4 every time the timer counts the set time, and noise removal starting in step 5 is performed. Enter the process.

The noise removal step is performed by the connection line 28
Is 10 meters or more,
In particular, when periodic noise such as generated from a motor is superimposed on a signal, the noise is prevented from being erroneously recognized as a true signal.

Then, in step 5, the signal level at that time is detected, and whether the signal level is higher or lower than a set value is compared to determine the logical level of the signal as "H" or "L", Save as current value.

Further, in step 6, it is determined whether or not the value is the same as the previously stored value. If the value is different, the process proceeds to step 7 to clear the count value, and then proceeds to the timer setting operation in step 8.

The timer setting operation is for changing the setting of the timer time for causing the timer interruption in step 4 and is characterized in that the value is changed randomly.

As a method of setting the timer time to a random value, it can be derived by calculation using a random function. Alternatively, the method is not limited to a method in which a plurality of types of timer times are stored in a memory in advance in a random arrangement state, and the stored values are sequentially read and used.

On the other hand, when it is determined in step 6 that the input state of the signal is the same as that at the time of the previous detection, the process proceeds to step 9 to determine whether the count value of the counter has reached the set number. Is determined.

The determination in this step is "YES".
If so, it is determined that the same signal state has been detected continuously for the set number of times, so the process proceeds to ST10 where the data is determined as correct. Thereafter, the process proceeds to step 7 to initialize the count value by clearing the count value, and prepare for the next level detection.

If it is determined in step 9 that the count value has not reached the set number, the process proceeds to step 11, where the count value is increased by 1, and then to step 8. By changing the timer value in step 8, the signal detection operation is continued while preventing periodic noise from being continuously detected.

In FIG. 2 described above, a method using a program has been exemplified as a method for removing the influence of periodic noise from the input signal. However, substantially the same operation can be realized by hardware. is there.

FIG. 3 shows an example of such a configuration. In this embodiment, four D-type flip-flops 46 are connected in series to form a four-stage shift register flip-flop. Group 54.

Further, while the signal A to be detected is input to the input side of the flip-flop group 54, the output signals of the flip-flops 46a, 46b, 46c, 46d at each stage are input to the AND circuit 56, and the AND circuit 56 Is used as the detection signal B.

A clock signal generator 58 for generating a clock signal C whose input is set to a time sufficiently shorter than the expected noise generation period, for example, about 1 millisecond, is provided, and a first-stage flop-flop is further provided. In 46a, the basic clock signal C having the minimum frequency division ratio is directly used as the second clock signal.
The third-stage flip-flop 46b receives the clock signal C1 having a cycle of 1/3 via the 1/3 frequency divider 60, and the third-stage flip-flop 46c receives the clock signal C1 via the 1/2 frequency divider 62.
A 1/5 clock signal C2 is applied to the fourth flip-flop 46d by the 1/5 frequency divider 64, and a 1/5 clock signal C3 is applied to the fourth stage flip-flop 46d.

With this configuration, the input signal A periodically sampled by the first-stage flip-flop 46a
Are the flip-flops 46b and 46c of the second to fourth stages.
As a result of the thinning-out at 46d, signals at a plurality of locations having different detection time intervals in the input signal A are sampled and extracted, and furthermore, it is determined that the input is correct only when all the output signal values are complete. Is done.

FIG. 4 shows still another embodiment. In this embodiment, a plurality of D-type flip-flops 46 constituting a flip-flop group 54 are connected in parallel to each other so that a plurality of data inputs are connected to each other. The input signal A can be sampled in parallel by the flip-flops 46.

On the other hand, the clock signal output from the clock signal generator 58 and further frequency-divided by the frequency divider is directly input to the uppermost flip-flop 46a, but is subsequently input to the flip-flops 46b and 46c.・ 46
For d, an output signal from the preceding flip-flop 46 and a clock signal are input via an AND circuit 66.

With this configuration, after it is determined that the preceding flip-flop 46 has detected a significant signal,
As a result of the successive determination operation of the input signal A, the flip-flop 46 at the next stage can sample at a different timing the number of times corresponding to the number of constituent stages of the flip-flop.

Further, by setting the frequency division ratio of the clock signal C3 in the uppermost flip-flop 46a to the maximum, even if the periodic noise input is continuously detected by the uppermost flip-flop 46a, Noise signal detection is prevented by at least one flip-flop after the stage.

Accordingly, not only suddenly generated noise but also periodically generated noise is blocked by the AND circuit 56, so that malfunction of the circuit is prevented.
When noise is superimposed on the screen displayed on the display 20, only extra dots or lines are generated. However, when noise is superimposed on a blink signal used for blink control of the backlight 24, In this case, the backlight 24 is frequently turned on or off, or is turned off or turned on suddenly, and the influence of malfunction due to noise is greater.

The above circuit configuration is an example,
Needless to say, the number of flip-flop stages, the frequency division ratio in the frequency divider, or the cycle of the basic clock signal C can be arbitrarily increased or decreased according to the usage environment.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example in which the present invention is applied to a programmable display device.

FIG. 2 is a flowchart illustrating an example of a signal processing procedure.

FIG. 3 is a block diagram of a main part showing a circuit configuration for realizing a signal processing procedure.

FIG. 4 is a block diagram showing another circuit configuration for realizing a signal processing procedure.

[Explanation of symbols]

 Reference Signs List 10 target system 12 PLC 14 display device 16 display unit 18 device main body 20 display 22 touch panel 24 backlight 26 display control circuit 28 connection line 30 CPU 34 RAM 38 graphic controller 40 video RAM 42 I / O circuit 44 I / O controller 46 flip-flop Group 54 flip-flop group 56 AND circuit 58 clock signal generator 60 1/3 frequency divider 62 1/2 frequency divider 64 1/5 frequency divider 66 AND circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C006 AA01 AF51 AF53 AF61 AF67 BB11 BB29 BF02 BF03 BF06 BF11 BF16 BF22 BF23 BF26 BF29 EA01 EC05 FA31 5C080 AA10 BB05 DD09 EE17 JJ02 JJ07

Claims (5)

[Claims] 1. A method for preventing a malfunction of a programmable display device connected to a predetermined external device and enabling a display corresponding to a control operation performed by the external device, wherein a level of an input signal is sampled at minute intervals. Then, when it is determined that the same signal state has been maintained for the set number of times, the signal state is determined, and the signal processing step of performing signal processing corresponding to the determined signal state is performed. A malfunction prevention method characterized in that time is set so that all time intervals are not the same during sampling. 2. The malfunction preventing method according to claim 1, wherein said sampling is performed by interruption by a timer, and the interruption time of the timer is changed every time one interruption is performed. . 3. The above-mentioned sampling comprises a flip-flop group in which a plurality of D-type flip-flops (46) are connected in series and an AND circuit (56), and a signal A to be processed is input to the flip-flop group. The clock signal C output from the clock signal generator (58) is applied to the flip-flop (46) of each stage as it is, or the clock signals C1, C2, and C3 obtained by dividing the frequency are applied to perform the data sampling operation. ,
A signal output from each stage flip-flop (46) is individually input to an AND circuit (56), and signal processing corresponding to the state of the output signal B from the AND circuit (56) is performed. While the generation period of the clock signal C output from the clock signal generator (58) is set sufficiently shorter than the generation period of the noise whose input is expected, the flip-flop (46) of each stage is driven. 2. The malfunction preventing method according to claim 1, wherein the frequency division ratios of the clock signals C1, C2, C3 are different from each other. 4. The above-mentioned sampling comprises a flip-flop group composed of a plurality of D-type flip-flops (46) and an AND circuit (56), and a signal A to be processed is supplied to each flip-flop (46). The clock signal C output from the clock signal generator (58) is directly input to the flip-flop (46) of each stage while being input in parallel.
Alternatively, the frequency-divided clock signals C1, C2, and C3 can be applied, and data sampling operations are performed at different timings in the flop flop (46) of each stage, and output from the flip-flop (46) of each stage. The signals are individually input to an AND circuit (56), and signal processing corresponding to the state of the output signal B from the AND circuit (56) is performed. The signal is output from the clock signal generator (58). The generation cycle of the clock signal C
While the input is set to be sufficiently shorter than the expected noise generation period, the division ratios of the clock signals C1, C2, and C3 for driving the flip-flops (46) of the respective stages are made different from each other, and the flip-flops ( Only when the output signal from (46) is significant, a clock signal can be input to the next-stage flip-flop (46) and the frequency division ratio in the top-stage flip-flop (46a) is maximized. The method for preventing malfunction according to claim 1. 5. The display device (14) includes a display unit (16) and a device body (18) separated from each other via a relatively long connection line (28).
The display unit (16) is provided with a backlight (24) on the back side of the display (20). The method for preventing malfunction according to any one of claims 1 to 4, wherein the method is applied to a blink signal sent from the device body (18) to the backlight (24) in the unit (16).