JP2001274670A - Output circuit for lsi - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output signal for an LSI that can automatically and properly adjust a leading time/a trailing time of an output waveform and avoid an operation defect with respect to interface timing with an external component even when an external load capacity of an output buffer circuit is increased more than an expected capacity. SOLUTION: The output circuit for the LSI is provided with an output buffer circuit 11 of a drive capability variable type having PMOS and NMOS transistors(TRs) for adjusting the drive capability and with an output buffer drive capability adjustment circuit 13 that discriminates a degree of an external load giving effect on the output buffer circuit and controls an ON/OFF state of respective TRs for adjusting the drive capability on the basis of its discrimination output by detecting a rounding leading/trailing of the output waveform of the output buffer circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit of a semiconductor integrated circuit (LSI), and more particularly, to an output buffer driving capability adjusting circuit for automatically adjusting the driving capability of an output buffer circuit.

[0002]

2. Description of the Related Art In general, the driving capability of an output buffer circuit of an LSI is determined by assuming the magnitude of a load capacitance external to the LSI connected to each output terminal (or input / output terminal) of the LSI when the LSI is mounted on a substrate. Have been.

However, if the load capacity becomes larger than expected due to the characteristics peculiar to the substrate and the characteristics of the connected components, the rising / falling of the output waveform is reduced, and the expected output characteristics cannot be obtained. There is a case where an operation defect relating to the interface timing with the interface occurs. If the buffer driving capability is set to a higher level in consideration of this, the current consumption of the LSI increases, which is not good in terms of noise.

[0004]

As described above, in the conventional output buffer circuit of the LSI, when the external load capacity becomes larger than expected, the rising / falling of the output waveform is reduced, and the expected output characteristics are obtained. There was a problem that there might not be.

The present invention has been made in order to solve the above-mentioned problem. Even when the external load capacitance of the output buffer circuit becomes larger than expected, the rise time / fall time value of the output waveform is automatically set. It is an object of the present invention to provide an output circuit of an LSI which can appropriately adjust the operation time and can avoid an operation defect relating to an interface timing with an external component.

[0006]

SUMMARY OF THE INVENTION An output circuit of an LSI according to the present invention comprises an output buffer circuit of a variable driving capacity and an output buffer circuit which detects rising / falling transitions of an output waveform of the output buffer circuit. An output buffer drive capacity adjusting circuit for determining the degree of an external load affecting the circuit and adjusting the drive capacity of the output buffer circuit based on the output of the determination.

[0007] As a specific example of the output circuit of the LSI, the output buffer circuit includes a normal buffering PMOS.
In addition to the transistor and the NMOS transistor, a PMOS transistor and an NMOS transistor for adjusting the driving capability are provided, and the output buffer driving capability adjusting circuit detects the rising / falling transition of the output waveform of the output buffer circuit. Thus, the degree of an external load affecting the output buffer circuit may be determined, and the on / off state of each transistor for adjusting the driving capability of the output buffer circuit may be controlled based on the determined output. .

In addition, the output buffer circuit includes a plurality of sets of PMOS transistors and NMOS transistors for adjusting driving capability, separately from the PMOS transistors and NMOS transistors for normal buffering. By inputting a control signal and performing control so that the numbers used simultaneously for adjusting a plurality of sets of output buffer driving capacities are different, the driving capacities may be adjusted in a plurality of stages.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings.

<First Embodiment> FIG. 1 shows an output circuit of an LSI according to a first embodiment of the present invention.

In the output circuit of FIG. 1, a signal from the internal logic circuit 10 is buffer-amplified by an output buffer circuit 11 and supplied to a load external to the LSI through an external terminal 12.

The output buffer circuit 11 includes a PMOS transistor and an NMOS transistor for adjusting driving capability, separately from a PMOS transistor and an NMOS transistor for normal buffering, and has a variable driving capability.

An output buffer drive capacity adjusting circuit (hereinafter, referred to as an adjusting circuit) 13 detects an external load which affects the output buffer circuit 11 by detecting the rising / falling of the output waveform of the output buffer circuit 11. And controlling the on / off state of each of the transistors for adjusting the driving capability based on the discriminated output, and controlling the on / off state of the output waveform by the output buffer circuit 11.
This is for adjusting the falling drive capability.

Next, the sequence of the buffer drive capability adjustment operation in the output circuit of FIG. 1 will be described.

The adjustment circuit 13 is activated by receiving a control pulse signal 16 generated from the internal logic circuit 10 during, for example, an LSI reset operation. Then, the output buffer circuit 11
Receives the signal waveform (input waveform) on the front stage of the output buffer not affected by the external load capacitance and the signal waveform (output waveform) on the rear stage of the output buffer affected by the external load capacitance, and integrates the respective signal waveforms By analyzing the characteristics, the degree of the external load capacity is comparatively analyzed. According to the result, after the reset operation is released, control signals 14 and 15 for varying the output buffer driving capability are supplied to the gates of the PMOS transistor and the NMOS transistor of the output buffer circuit 11 correspondingly, and the output buffer circuit Correct the balance of the rise time Tr / fall time Tf of the 11 output waveforms.

That is, according to the adjusting circuit 13 of the first embodiment, the signal waveform of the front stage of the output buffer not affected by the external load capacitance and the signal waveform of the rear stage of the output buffer affected by the external load capacitance are extracted. The degree of the external load capacitance is examined by analyzing the integration characteristics of the above, and the driving capability of the output buffer circuit 11 is controlled to be changed according to the result.

Therefore, even when the external load capacity becomes larger than expected, the rise time Tr / fall time Tf value of the output waveform is automatically and appropriately adjusted to prevent the operation failure relating to the interface timing with the external parts. Can be avoided.

In this case, by preparing two types of control signals, a signal connected to the PMOS transistor for adjusting the driving capability of the output buffer circuit 11 and a signal connected to the NMOS transistor for adjusting the driving capability, the rise time of the output waveform is obtained.
It is possible to correct the balance of Tr / fall time Tf.

FIG. 2 shows a circuit example of the output buffer circuit 11 having a variable driving capability in FIG.

The output buffer circuit includes a buffer circuit 20 for buffer-amplifying and outputting a signal (input signal) 2 from the internal logic circuit 10, the input signal 2 and the control signal
A NAND circuit 21 to which one of 14 and 15 is input, and a NOR circuit to which the other 15 of the input signal 2 and the control signals 14 and 15 are input
22, a PMOS transistor 23 and an NMOS transistor connected in series between the power supply node VCC and the ground node GND.
24, the output of the NAND circuit 21 is input to the gate of the PMOS transistor 23, and the NMOS transistor 24
The output of the NOR circuit 22 is input to the gate of the
A series connection node (a connection node between drains) of the transistor 23 and the NMOS transistor 24 is connected to an output node of the buffer circuit 20.

FIG. 3 shows a circuit example in which an integrating circuit is used as an example of the adjusting circuit 13 in FIG.

In FIG. 3, the integration circuits 31 and 32 receive the signal 2 at the preceding stage of the output buffer and the signal 3 at the latter stage of the output buffer, and integrate the signals. For example, as shown in FIG. And a resistance element 41 and a capacitor 42.

The sample and hold circuits 33 and 34 receive the integrated outputs 7 and 8 of the integrating circuits 31 and 32, respectively, and sample the input while receiving the control pulse signal 16 from the internal logic circuit 10. Thereafter, the data is held, and for example, as shown in FIG. 5, each is constituted by a PMOS transistor 51 for switching and a capacitor 52 for holding electric charge.

The first A / D conversion circuit 35 corresponds to the hold outputs 9, 30 of the sample and hold circuits 33 and 34, respectively.
Are input to a comparison input node (+) and a reference input node (−), the two input potentials are compared, and a signal of a different logic level is output according to the comparison result. In this case, when the potential of the comparison input node (+) is higher than the potential of the reference input node (-) (that is, the signal level of the latter stage of the output buffer is lower than the signal level of the former stage of the output buffer).
Outputs a signal of "H", and in the case of the opposite relation to the above, outputs a signal of "L".

On the other hand, the second A / D conversion circuit 36
Correspondingly, the hold outputs 9, 30 of the sample and hold circuits 33 and 34 are input to the reference input node (-) and the comparison input node (+), and both input potentials are compared. Outputs a logic level signal. In this case, when the potential of the comparison input node (+) is higher than the potential of the reference input node (-) (that is, the signal level of the output buffer rear stage is higher than the signal level of the output buffer front stage). A signal of "H" is output in the case of the opposite relation to the above. Therefore, the first A /
The output signal of the D conversion circuit 35 and the output signal of the second A / D conversion circuit 36 are complementary signals.

The RS flip-flop circuits 37 and 38 are
Complementary output signals of the A / D conversion circuits 36 and 37 are input correspondingly as a set input S, and a control pulse signal 16 from the internal logic circuit 10 is input as a reset input R. Thus, the control signals 14 and 15 are obtained.

FIG. 6 shows two examples A and B of the output buffer circuit of FIG. 2 showing a signal waveform at the front stage of the output buffer not affected by the load capacitance and a signal waveform at the rear stage of the output buffer affected by the load capacitance. Is shown.

Here, waveform example A shows a state in which the falling edge is affected by the load, and waveform example B shows a state in which the rising edge is affected by the load.

FIG. 7 shows the potential relationship when the waveform examples A and B shown in FIG. 6 pass through the integration circuits 31 and 32 in FIG. 3 and are sampled and held by the sample and hold circuits 33 and 34. I have.

Next, the operation of adjusting the driving capability of the output buffer circuit of FIG. 2 by the driving capability adjusting circuit of FIG. 3 will be described in detail with reference to FIGS. 6 and 7.

In the case of waveform example A in FIG. 6, the signal level of the output buffer preceding stage in the output buffer circuit shown in FIG. 2 is higher than the signal level of the output buffer preceding stage in both the "H" period and the "L" period. Also, since the signal level of the latter stage of the output buffer is higher, the output signals of the A / D conversion circuits 35 and 36 in FIG. 3 become "L" / "H" correspondingly, and the output from the RS flip-flop circuits 37 and 38 The corresponding control signals 14 and 15 become "L" / "H".

Therefore, in the output buffer circuit of FIG. 2, while the signal level of the preceding stage of the output buffer is "L", the output of the NAND circuit 21 becomes "H" and the PMOS transistor 23 is turned off. At this time, the NOR circuit 22 operates according to the "H" of the control signal 15, the output thereof becomes "H", and the NMOS transistor 24 is turned on. This allows
When the output level of the buffer circuit 20 is reduced (the driving capability of the NMOS transistor is increased), the output of the output buffer circuit is corrected. Note that the output of the NAND circuit 21 is also "H" while the signal level of the previous stage of the output buffer is "H".
And the PMOS transistor 23 is off.

On the other hand, in the case of the waveform example B in FIG. 6, the signal level of the output buffer before the output buffer circuit in the output buffer circuit shown in FIG. Since the signal level after the output buffer is lower than the signal level, the A / D conversion circuit 35 and the
The output signal of 36 becomes "H" / "L" correspondingly, and the control signals 14 and 15 output from the RS flip-flop circuits 37 and 38 become "H" / "L" correspondingly.

Therefore, in the output buffer circuit of FIG. 2, while the signal level of the preceding stage of the output buffer is "H", the output of the NAND circuit 21 becomes "L" and the PMOS transistor 23 is turned on. At this time, the NOR circuit 22 is controlled to be inhibited by the control signal 15 at "L", and the output "L" turns off the NMOS transistor 24. As a result, the output level of the buffer circuit 20 is raised (PM
The output of the output buffer circuit is corrected by increasing the driving capability of the OS transistor). Note that while the signal level at the previous stage of the output buffer is "L", the output of the NAND circuit 21 becomes "H" and the PMOS transistor 23 is turned off.

That is, when the output potential of the second sample and hold circuit 34 (potential to be adjusted) is high with the output of the first sample and hold circuit 33 as the reference potential, the buffer circuit 20
The drive capacity of the NMOS transistor has been increased, and conversely,
When the output potential (potential to be adjusted) of the second sample and hold circuit 34 is low with the output of the first sample and hold circuit 33 as a reference potential, an operation is performed to increase the driving capability of the PMOS transistor of the buffer circuit 20. . As a result, the Tr / Tf balance of the output waveform is automatically corrected to an appropriate value, and it is possible to avoid the operation trouble related to the timing when mounting the LSI substrate.

<Embodiment 2> FIG. 8 shows an output circuit of an LSI according to Embodiment 2 of the present invention.

In the output circuit of FIG. 8, a signal from the internal logic circuit 10 is buffer-amplified by an output buffer circuit 11 and supplied to a load external to the LSI through an external terminal 12. The output buffer circuit 11 Like the output buffer circuit 11 in FIG. 1, the output buffer circuit includes a plurality of PMOS transistors and NMOS transistors, and has a variable driving capability.

The output buffer drive capacity adjusting circuit 80 detects the degree of the external load affecting the output buffer circuit 11 by detecting the rising / falling transition of the output waveform of the output buffer circuit 11, and determines the degree. The on / off state of each transistor of the output buffer circuit 11 is controlled based on the output to adjust the drive capability of the output buffer circuit 11 for the rising / falling of the output waveform.

The output buffer circuit 11 in FIG. 8 has a configuration as shown in FIG. 2, for example.

Next, the sequence of the buffer drive capability adjustment operation in the output circuit of FIG. 8 will be described.

The output buffer drive capability adjusting circuit 80 is activated by receiving the control pulse signal 16 generated from the internal logic circuit 10 during, for example, an LSI reset operation. Then, a signal waveform (output waveform) on the subsequent stage of the output buffer affected by the external load capacitance is received, and the degree of the external load capacitance is analyzed by analyzing the differential characteristics of the signal waveform. According to the result, after the reset operation is released, the control signals 24 and 25 for changing the output buffer drive capability are changed.
A PMOS for adjusting the driving capability of the output buffer circuit 11
The output voltage is supplied to the gate of the transistor and the gate of the NMOS transistor for adjusting the driving capability, and the balance of the rise time Tr / fall time Tf of the output waveform of the output buffer circuit 11 is corrected.

That is, according to the adjusting circuit 80 of the second embodiment, the degree of the external load capacitance is determined by extracting the signal waveform at the subsequent stage of the output buffer affected by the external load capacitance and analyzing its differential characteristic. The control is performed to change the driving capability of the output buffer circuit 11 according to the result.

Therefore, even when the external load capacity becomes larger than expected, the rise time Tr / fall time Tf of the output waveform is automatically and appropriately adjusted to prevent an operation defect relating to the interface timing with external parts. Can be avoided.

FIG. 9 shows a circuit example in which a differentiating circuit is used as an example of the output buffer driving capability adjusting circuit 80 in FIG.

In FIG. 9, the differentiating circuit 90 receives the signal 3 at the stage after the output buffer and differentiates the signal. For example, as shown in FIG. 10, the differentiating circuit 90 includes a capacitor 111 and a resistance element 112.

The first pre-buffer circuit 91 receives the differentiated output 27 of the differentiating circuit 90 and receives a certain high level VI.
When H is high (the positive amplitude of the differential output is large) with reference to H, the "H" level is detected and buffered.

The second pre-buffer circuit 92 receives the differentiated output 27 of the differentiating circuit 90 and receives a certain low level VI.
When the level is low relative to L (the negative amplitude of the differential output is large), the "L" level is detected and buffered.

The first RS flip-flop circuit 93 outputs the output of the first pre-buffer circuit 91 as a set input S.
28, and the control pulse signal 16 from the internal logic circuit 10 is input as the reset input R.

The second RS flip-flop circuit 94 outputs the output of the second pre-buffer circuit 92 as a set input S.
29 is input as negative logic, and the control pulse signal 16 from the internal logic circuit 10 is input as a reset input R.

The third RS flip-flop circuit 95 receives the first RS flip-flop circuit as a set input S.
An output of the inverter 93 is inverted and input by an inverter circuit 96, a control pulse signal 16 from the internal logic circuit 10 is input as a reset input R, and an output of the control pulse signal
Becomes

The fourth RS flip-flop circuit 97 receives the second RS flip-flop circuit as a set input S.
The output of 94 is inverted and input by the inverter circuit 97, the control pulse signal 16 from the internal logic circuit 10 is input as the reset input R, and the output is the control signal 15
Becomes

FIG. 11 shows an example of the operation sequence of the drive capability adjusting circuit of FIG. 9 when the rise of the signal waveform at the subsequent stage of the output buffer is affected by the load capacitance in the output buffer circuit of FIG.

FIG. 12 shows an example of the operation sequence of the drive capability adjusting circuit of FIG. 9 in the case where the falling edge of the signal waveform at the subsequent stage of the output buffer is affected by the load capacitance in the output buffer circuit of FIG. .

Next, the internal operation of the output buffer driving capability adjusting circuit of FIG. 9 and the driving capability adjusting operation of the output buffer circuit of FIG. 2 will be specifically described with reference to FIGS.

In the output buffer drive capacity adjusting circuit shown in FIG. 9, the signal "H" detected by the first pre-buffer circuit 91 when the positive amplitude of the differential output 27 is large when the pulse signal 3 at the subsequent stage of the output buffer is inverted is large. "By the first R
The S flip-flop circuit 93 is set, and after being inverted by the inverter circuit 96, is latched by the third RS flip-flop circuit 95, and the control signal 24 as its output becomes "L". At this time, the control signal 14, which is the output of the fourth RS flip-flop circuit 97, becomes "H".

On the other hand, the second pre-buffer circuit 92 detects when the negative amplitude of the differential output 27 is large when the pulse signal 3 at the subsequent stage of the output buffer is inverted by the second pre-buffer circuit 92 and the second RS The flip-flop circuit 94 is set, and after being inverted by the inverter circuit 98, is latched by the fourth RS flip-flop circuit 97, and the control signal 15 as its output becomes "L". At this time,
The control signal 14, which is the output of the third RS flip-flop circuit 95, becomes "H".

When the amplitude of the differential output at the time of inversion of the pulse signal 3 at the subsequent stage of the output buffer is small, the detection by the first pre-buffer circuit 91 is not performed.
The output of the flip-flop circuit 93 remains “L”, and after being inverted by the inverter circuit 96, the third RS
The control signal 14 which is latched by the flip-flop circuit 95 and is the output thereof becomes "H". At this time, since the detection by the second pre-buffer circuit 92 is not performed, the output of the second RS flip-flop circuit 94 remains “L”.
, And the control signal 15 as the output thereof becomes "H".

As shown in FIG. 11, when the rising edge of the signal waveform after the output buffer is blunted, the amplitude of the differential signal at the rising edge of the signal waveform is small, and the amplitude of the differential signal at the falling edge of the signal waveform is small. growing. As a result, the control signal 14 output from the output buffer drive capability adjustment circuit in FIG. 9 becomes "H" and the control signal 15 becomes "L".

Therefore, while the signal level at the previous stage of the output buffer in FIG. 2 is "H", the output of the NAND circuit 21 is "H".
L "to turn on the PMOS transistor 23. At this time, the NOR circuit 22 is inhibited from being controlled by" L "of the control signal 25, and its output" L "causes the NMOS transistor 24 to be turned off.
Is turned off. As a result, the output level of the buffer circuit 20 is increased (the driving capability of the PMOS transistor is increased), so that the output of the buffer circuit 20 is corrected. Note that while the signal level at the previous stage of the output buffer is "L", the output of the NAND circuit 21 becomes "H" and the PMOS transistor 23 is turned off.

As shown in FIG. 12, when the falling edge of the signal waveform at the subsequent stage of the output buffer is blunted, the amplitude of the differential signal at the falling edge of the signal waveform is small, and the amplitude of the differential signal at the rising edge of the signal waveform is small. Becomes larger. As a result, the control signal 14 output from the output buffer drive capability adjustment circuit in FIG. 9 becomes "L" and the control signal 15 becomes "H".

Therefore, while the signal level at the previous stage of the output buffer in FIG. 2 is "L", the output of the NAND circuit 21 is "L".
H "to turn off the PMOS transistor 23. At this time, the NOR circuit 22 operates according to" H "of the control signal 15, the output of the NOR circuit 22 becomes" H ", and the NMOS transistor 24 is turned off. In this state, the output level of the buffer circuit 20 is reduced (the driving capability of the NMOS transistor is increased) to correct the output of the buffer circuit 20. The signal level of the previous stage of the output buffer is "H". "
During this period, the output of the NAND circuit 21 is "H", and the PMOS transistor 23 is off.

FIG. 13 shows a modification of the output buffer circuit shown in FIG.

This output buffer circuit is different from the output buffer circuit shown in FIG. 2 in that a NAND circuit 21, a NOR circuit 22,
A plurality of driving stages each including a PMOS transistor 23 and an NMOS transistor 24 are connected in parallel, and a pair of control signals are input in correspondence with each group. Parts are given the same reference numerals.

The operation of this output buffer circuit is basically the same as the operation of the output buffer circuit shown in FIG. 2, except that the number of stages simultaneously used for adjusting the output buffer driving capability among the plurality of driving stages is described. , The driving capability can be adjusted in a plurality of stages.

[0065]

As described above, according to the output circuit of the LSI of the present invention, even if the external load capacity of the output buffer circuit becomes larger than expected, the rise time / fall time value of the output waveform is automatically set. In this case, it is possible to appropriately adjust the timing and to avoid an operation defect relating to the interface timing with the external component.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an output circuit of an LSI according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a circuit example of an output buffer circuit having a variable driving capability in FIG. 1;

FIG. 3 is a diagram showing a circuit example when an integrating circuit is used as an example of the output buffer drive capability adjustment circuit in FIG. 1;

FIG. 4 is a circuit diagram showing an example of the integration circuit in FIG. 3;

FIG. 5 is a circuit diagram showing an example of the sample-and-hold circuit in FIG. 3;

FIG. 6 is a waveform chart showing two examples A and B of a signal waveform of the output buffer before hitting which is not affected by the load capacitance and a signal waveform of the latter stage of the output buffer which is affected by the load capacitance in the output buffer circuit of FIG. .

7 is a correlation diagram showing a potential relationship when the waveform examples A and B shown in FIG. 6 pass through the integration circuit in FIG. 3 and are sampled and held by a sample and hold circuit.

FIG. 8 is a block diagram showing an output circuit of an LSI according to a second embodiment of the present invention.

FIG. 9 is a diagram showing a circuit example when a differentiating circuit is used as an example of the output buffer drive capability adjusting circuit in FIG. 8;

FIG. 10 is a circuit diagram showing an example of the differential circuit shown in FIG. 9;

FIG. 11 is a waveform chart showing an example of an operation sequence of the drive capability adjustment circuit of FIG. 9 in a case where the rising edge of the signal waveform at the subsequent stage of the output buffer is affected by the load capacitance in the output buffer circuit of the second embodiment.

FIG. 12 is a waveform chart showing an example of an operation sequence of the drive capability adjustment circuit of FIG. 9 in a case where the falling edge of the signal waveform at the subsequent stage of the output buffer is affected by the load capacitance in the output buffer circuit of Embodiment 2;

FIG. 13 is a circuit diagram showing a modification of the output buffer circuit shown in FIG. 2;

[Description of Signs] 10: Internal logic circuit, 11: Output buffer circuit, 12: External terminal, 13: Output buffer drive capacity adjustment circuit.

Continued on the front page F term (reference) 5J055 AX08 AX65 AX66 BX16 CX00 DX13 DX14 DX22 DX56 DX73 DX83 EX01 EX02 EX07 EX11 EX24 EZ00 EZ01 EZ02 EZ07 EZ25 EZ32 FX18 FX31 FX39 GX01 GX02 GX04 5J056 AA04 CC13 DD DD CC39 DD DD EE11 EE15 FF07 FF08 KK01

Claims (5)

[Claims] An output buffer circuit having a variable driving capability; and a degree of an external load affecting the output buffer circuit is detected by detecting a rising / falling edge of an output waveform of the output buffer circuit. An output buffer driving capability adjusting circuit for adjusting the driving capability of the output buffer circuit based on the discrimination output. 2. The output buffer circuit according to claim 1, further comprising a PMOS transistor and an NMOS transistor for adjusting a driving capability, separately from a PMOS transistor and an NMOS transistor for normal buffering. The degree of the external load affecting the output buffer circuit is determined by detecting the rising / falling transition of the output waveform of the output buffer circuit, and the driving capability adjustment of the output buffer circuit is performed based on the determined output. Wherein the on / off state of each of the transistors is controlled. 3. The output buffer drive capacity adjustment circuit is activated by receiving a control pulse signal generated from an internal logic circuit during an LSI reset operation, and is not affected by an external load capacitance of the output buffer circuit. Receives the signal waveform of the front stage of the output buffer and the signal waveform of the rear stage of the output buffer affected by the external load capacitance, and analyzes the integration characteristics of each signal waveform to compare and analyze the degree of the external load capacitance. After the reset operation is released, two types of output buffer driving capability control signals are supplied to the gates of the PMOS transistor and the NMOS transistor for adjusting the driving capability of the output buffer circuit in response to the output buffer circuit. Rise time of output waveform of /
3. The output circuit according to claim 2, wherein the fall time balance is corrected. 4. The output buffer drive capability adjustment circuit is activated upon receiving a control pulse signal generated from an internal logic circuit during a reset operation of an LSI, and outputs the output buffer circuit affected by an external load capacitance of the output buffer circuit. After receiving the signal waveform at the latter stage of the buffer and analyzing the differential characteristics of the signal waveform, the degree of the external load capacitance is analyzed. According to the result, after the reset operation is released, two types of output buffer driving capability variable. A control signal is supplied correspondingly to the gate of a PMOS transistor and the gate of an NMOS transistor for adjusting the driving capability of the output buffer circuit, and the balance of the rise time / fall time of the output waveform of the output buffer circuit is corrected. L according to claim 2,
Output circuit of SI. 5. The output buffer circuit comprises a plurality of sets of PMOS transistors and NMOS transistors for adjusting driving capability, separately from the PMOS transistors and NMOS transistors for normal buffering. A pair of control signals are input, and a plurality of sets of output buffers are controlled so that the numbers used simultaneously for adjusting the driving capacity are different, so that the driving capacity can be adjusted in a plurality of stages. 2. The output circuit of the LSI according to 1.