JP2001274261A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having structure of preventing floating capacitance so that high frequency characteristics do not deteriorate and to provide a manufacturing method. SOLUTION: AMOS transistor formed on a silicon substrate 1 is included. An impurity diffusion layer 9 for giving potential to a well in such a way that the MOS transistor is surrounded is connected to a third metal wiring layer 14 at an upper layer through plug electrodes 11a, 11b and 11c arranged into an array form. A third metal wiring layer 14 is fixed to the ground potential (ground).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a field effect transistor or a capacitor and a method of manufacturing the same.

[0002]

2. Description of the Related Art Several GHz bands are used as transmission and reception frequencies for portable terminals and wireless LANs. L for that GHz band
Conventionally, a compound semiconductor has been used for SI. However, in recent years, MOS using silicon
The high-frequency characteristics of type transistors have been improved, and MOS transistors using this silicon are being applied to GHz-band LSIs.

A state-of-the-art silicon integrated circuit comprises a MOS transistor and about six layers of metal wiring. For example, "1998 International ELECT
ORONDEVICES Meeting TECHNICAL DIGEST 829
Pp. 832, co-authored by Igarashi et al. "Are intended for high-speed digital circuits.

Here, a conventional silicon semiconductor device structure will be described with reference to FIG. On a main surface of a silicon substrate 101 serving as a semiconductor substrate, an element isolation region 102 made of a silicon oxide film and a well region 103 made of a first conductivity type impurity (P type impurity) are formed. Further, a gate electrode 104 covered with a sidewall 106 is provided above the well region 103 with a gate insulating film 104a interposed therebetween. This gate electrode 10
4 controls the MOS transistor.

The well region 10 below the gate electrode 104
In 3, a drain diffusion layer 107 and a source diffusion layer 108 made of a high-concentration impurity diffusion layer of the second conductivity type (N-type impurity) are provided so as to sandwich the channel region 105. The gate electrode 104, the drain diffusion layer 107, and the source diffusion layer 108 form a MOS transistor.

In addition, an opening region for exposing a well region 103 is provided in a part of the element isolation region 102 arranged so as to surround the MOS transistor, and the potential of the well region 103 is fixed in the opening region. To provide a high-concentration first conductivity type impurity diffusion layer 109.

Although the main surface of the silicon substrate 101 is covered with an interlayer insulating film 110, the first conductive type impurity diffusion layer 109, the gate electrode 104, the drain diffusion layer 107 and the source diffusion layer 108 have their potentials Are connected to plug electrodes 111a, 111b, 111c.

The setting of the potential to each region and the like is performed by the gate electrode 1
04, the first metal wiring layer 112 uses a high frequency (RF)
The signal 115 is input, and the drain diffusion layer 107
High frequency (RF) signal 1 amplified by metal wiring layer 113
The third metal wiring layer 114 fixes the source region 108 and the first conductivity type impurity diffusion layer 109 to the ground potential.

[0009]

In the above-described silicon semiconductor device structure, unlike a conventional compound semiconductor formed of an insulating substrate, the silicon substrate has conductivity, so that it can be used in a high-frequency signal circuit (analog circuit). When using it, it is necessary to pay attention to the following problems.

(I) Deterioration of element characteristics due to various capacitances between substrates and finite resistance in a silicon substrate added in series with the capacitances.

(Ii) a semiconductor element adjacent to the semiconductor element;
In addition, deterioration of characteristics due to intrusion of noise from each wiring layer or signal leakage.

In a silicon device including an analog circuit, the output characteristics of the transistor device can be changed (for example, the gate width is increased) and the capacitance device can be added by changing the etching mask in the wiring step. Often done.

More specifically, an electrically isolated spare transistor element is arranged in the same structure adjacent to a transistor element connected to an external element. In this case, the output characteristics and the like are changed by connecting to an external circuit. Similarly, there is also a case where an electrically isolated spare capacitance element having the same structure is arranged adjacent to a capacitance element connected to an external element.

However, when the spare transistor element and the spare capacitance element are not used, a relatively large stray capacitance remains between the gate electrode and the substrate, etc. This may cause problems such as transmitting noise to an adjacent transistor. Further, there is a concern that generation of a stray capacitance between a wiring layer provided thereabove and the transistor element and generation of a signal loss via a resistor added in series therewith.

Accordingly, it is an object of the present invention to provide a semiconductor device having a structure for preventing generation of stray capacitance and signal loss, and a method of manufacturing the same.

[0016]

According to the present invention, there is provided a semiconductor device having a semiconductor element provided in a well region, wherein the semiconductor device is provided so as to surround the semiconductor element via an element isolation region. A first diffusion layer for fixing the potential of the well region, a plurality of plug electrodes disposed on the first diffusion layer, and a ground potential provided above the semiconductor element and connected to the plug electrode. And a wiring plate fixed to the wiring board.

In the above-described semiconductor device, since the wiring plate is fixed at the ground potential, even if a leakage signal is generated, it can be emitted to the outside through the wiring plate, and noise from outside can be reduced. On the other hand, it is possible to realize a stable circuit configuration by escaping to the wiring plate.

Further, in order to carry out the invention in a preferable state, a mesh type wiring layer in which a plurality of wirings are arranged so as to cross each other is used for the wiring plate. By using the mesh-type wiring layer for the wiring plate in this way, it is possible to reduce the capacitance between the upper and lower wirings facing each other.

In a preferred embodiment, the semiconductor element includes a gate electrode, and the well region includes a second diffusion layer serving as a source region and a third diffusion layer serving as a drain region.
An OS transistor is formed, and at least one of the gate electrode and the drain electrode has a structure which is not electrically connected to an element provided outside.

In a preferred embodiment, the semiconductor element has a capacitance element using a gate electrode of a MOS transistor as an upper electrode and a high-concentration impurity diffusion layer formed in the well region as a lower electrode. A structure is adopted in which at least one of the electrode and the lower electrode is not electrically connected to an element provided outside.

As described above, even when the semiconductor device of the present invention is applied as a spare semiconductor device, the semiconductor device according to the present invention can be discharged to the outside through the wiring plate because of the provision of the ground potential fixing device. It is possible to realize a circuit configuration with less noise that prevents generation of capacitance and signal loss.

In a method of manufacturing a semiconductor device according to the present invention, a step of forming a well region, a step of forming a semiconductor element on the well region, and a step of forming the semiconductor element with an element isolation region interposed therebetween. Forming a first diffusion layer for fixing the potential of the well region so as to surround the first diffusion layer; forming a plurality of plug electrodes on the first diffusion layer; and a wiring plate connected to the plug electrode Above the semiconductor element, and fixing the potential of the wiring plate to a ground potential.

In the semiconductor device manufactured by the above-described manufacturing method, since the potential of the wiring plate is fixed to the ground potential, even if a leakage signal occurs, it can be released to the outside through the wiring plate. Further, it is possible to realize a circuit configuration that reduces noise entering the element from the outside.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the drawings, a semiconductor device and a method for manufacturing the same according to each embodiment of the present invention will be described below.

(Embodiment 1) Referring to FIGS. 1 and 2, a MOS transistor according to Embodiment 1 and its operation and manufacturing method will be described. FIG. 1 is a cross-sectional structural view of a MOS transistor according to the present embodiment, and FIG. 2 is a schematic diagram as viewed from above. Further, in FIG. 2, only a contour of a third metal wiring layer 14 described later is shown.

(Cross-Sectional Structure of MOS Transistor) First, referring to FIGS. 1 and 2, a main surface of a silicon substrate 1 includes an element isolation region 2 and a first conductivity type impurity (P type impurity). Well region 3 is provided. A gate electrode 4 covered with a sidewall 6 is provided on a predetermined active region surrounded by the element isolation region 2 with a gate insulating film 4a interposed therebetween.

In the well region 3 below the gate electrode 4,
Second conductivity type (N-type impurity) so as to sandwich channel region 5
, A drain diffusion layer 7 and a source diffusion layer 8 made of a high-concentration impurity diffusion layer. The gate electrode 4, the drain diffusion layer 7 and the source diffusion layer 8 constitute a MOS transistor.

The well region 3 is provided so as to surround the channel region 5, the drain diffusion layer 7 and the source diffusion layer 8, and is provided so as to extend below the element isolation region 2. Also, so as to surround the element isolation region 2,
The surface of the well region 3 has an impurity concentration as high as that of the drain diffusion layer 7 and the source diffusion layer 8 and has a first conductivity type (P-type impurity) for fixing the potential of the well region 3. A diffusion layer 9 is provided. The element isolation region 2 is also formed outside the impurity diffusion layer 9.

In FIG. 2, MOS transistors each including a gate electrode 4, a drain diffusion layer 7 and a source diffusion layer 8 are arranged in parallel in a comb shape generally used in a high-frequency circuit.

The main surface of the silicon substrate 1 has an interlayer insulating film 1
0, but plug electrodes 11a, 11b, 11c for setting the potentials of the impurity diffusion layer 9, the gate electrode 4, the drain diffusion layer 7, and the source diffusion layer 8 for fixing the potential of the well region 3. Is provided.

The potentials of the respective electrodes and regions are applied to the gate electrode 4 via the first metal interconnection layer 12 of the first layer, and to the drain diffusion layer 7 and the source diffusion layer 8 of the second layer of the second layer. Via the metal wiring layer 13, the impurity diffusion layer 9 is supplied via the third metal wiring layer 14 of the third layer. Note that the gate electrode 4 and the drain diffusion layer 7 are formed on the first metal wiring layer 12.
And the second metal wiring layer 13 electrically connects to an external element.

As shown in FIG. 2, the plug electrodes 11a, 11b and 11c for supplying a potential to the impurity diffusion layer 9 are arranged in countless numbers along the active region. Third
The third metal wiring layer 14 is a MOS type transistor,
A metal plate having a size that can include the element isolation region 2 and the well region 3 is used.

A high frequency (RF) signal 15 is input to the gate electrode 4 from the first metal wiring layer 12, and an RF signal 16 amplified by the second metal wiring layer 13 is output from the drain diffusion layer 7 to the well region. An impurity diffusion layer 9 for applying a potential to 3 is fixed to a ground potential (ground) via a third metal wiring layer 14 and an upper layer wiring (not shown).

(Manufacturing Method) Next, an outline of a method of manufacturing the MOS transistor according to the first embodiment will be described with reference to FIG. First, the first surface of the silicon substrate 1
Well region 3 made of a conductive impurity (P-type impurity)
And an element isolation region 2 are formed. Next, a gate electrode 4 and a sidewall 6 are formed on a predetermined active region with a gate insulating film 4a interposed.

Next, using the gate electrode 4 and the sidewall 6 on the side wall as a mask, the channel region 5 under the gate electrode 4 is formed.
Are formed, a drain diffusion layer 7 and a source diffusion layer 8 of a high concentration impurity diffusion layer of the second conductivity type (N-type impurity) are formed. In another step, an impurity diffusion layer of the first conductivity type (P-type impurity) for fixing the potential of the well region 3 having the same high impurity concentration as the drain diffusion layer 7 and the source diffusion layer 8. 9 is formed.

Next, an interlayer insulating film 10 having a predetermined thickness is formed, and a gate electrode 4, a drain diffusion layer 7, and a source diffusion layer 8 are formed.
After forming the plug electrode 11a in contact with the impurity diffusion layer 9, the first metal wiring layer 12 patterned into a predetermined shape is formed. Further, similarly, an interlayer insulating film 10 having a predetermined thickness is formed, a plug electrode 11b in contact with the drain diffusion layer 7, the source diffusion layer 8, and the impurity diffusion layer 9 is formed. The metal wiring layer 13 is formed. Further, similarly, after forming an interlayer insulating film 10 of a predetermined thickness and forming a plug electrode 11c in contact with the impurity diffusion layer 9, a size capable of including the MOS transistor, the element isolation region 2, and the well region 3 is formed. A third metal wiring layer 14 made of a metal plate is formed.

(Function / Effect) In the case of the MOS transistor having the above configuration, a predetermined DC gate bias (for example, 1.0 V) and a drain bias (for example, 1.8 V) are applied. A high-frequency signal 15 is input to the gate electrode 4, and an amplified high-frequency signal 16 is output from the drain diffusion layer 7. Usually, a high-frequency signal of several GHz is connected to an adjacent transistor that is not electrically connected or a wiring layer by a capacitance and transmits the signal. These become leakage signals and become noise in external elements.

However, in the case of the MOS transistor of this embodiment, since the third metal wiring layer 14 is fixed at the ground potential (ground), the leakage signal flows to the ground potential (ground). Therefore, emission of noise to the outside can be reduced. A similar effect can be expected for external noise.

(Embodiment 2) Next, referring to FIG.
The structure of the MOS transistor according to the second embodiment will be described. FIG. 3 shows the MO in this embodiment.
It is the schematic diagram which looked at the S-type transistor from the upper surface. Also,
3, only the outline of a mesh type plate 17 described later is shown.

(Structure of MOS Transistor) The difference from the MOS transistor in the first embodiment is that in the first embodiment, a metal plate of a size capable of including the well region 3 is used as the third metal wiring layer 14. In this embodiment, a grid-type mesh plate 17 formed by lines 17a and spaces 17b intersecting each other as shown in FIG. 4 is used, and the other configuration is the same. Therefore, the same components are denoted by the same reference numerals and description thereof will be omitted. Also,
Since the manufacturing method is also the same as that of the MOS transistor in the first embodiment, the description is omitted.

(Function / Effect) When the signal wiring layer is formed on the third metal wiring layer by using the mesh type plate 17 as the third metal wiring layer, compared with the first embodiment, It is possible to reduce the capacitance between the third metal wiring layer and the upper signal wiring layer. The present invention is not limited to the mesh type, and it is also possible to apply a slit-type third metal wiring layer composed of lines and spaces (stripes).

(Embodiment 3) Next, referring to FIG.
The structure of the MOS transistor according to the third embodiment will be described. FIG. 5 shows the MO in this embodiment.
It is the schematic diagram seen from the upper surface of the S-type transistor.

(Structure of MOS Type Transistor) The MOS type transistor in the present embodiment is next to a high-frequency signal circuit element (transistor) block 1000A having the same structure as in the first embodiment, and is provided with a spare circuit element block of the same structure. 2000A is provided. However, the spare circuit element block 2000A is connected to the floating electrode 18 in which the gate electrode 4 and the drain diffusion layer 7 are not electrically connected to an external element. The well region 3 is fixed to the ground potential (ground) with the upper third metal wiring layer 14 interposed therebetween. Note that only one of the gate electrode 4 and the drain region 7 is connected to the floating electrode 18.
May be connected.

This spare circuit element block 2000A
When changing the transistor output characteristics and the like of the adjacent high-frequency signal circuit element (transistor) block 1000A, it is assumed that the spare circuit element block 2000A is electrically connected using a mask for forming an upper metal wiring layer. The structure is exactly the same as that of the high-frequency signal circuit element (transistor) block 1000A. Therefore, it is possible to make a circuit change to obtain desired characteristics with a minimum change in the wiring layer.

The method for manufacturing the high-frequency signal circuit element (transistor) block 1000A and the spare circuit element block 2000A having the same structure are described in the first embodiment.
It can be manufactured by a method similar to that of the OS transistor.

(Operation / Effect) Here, conventionally, when the transistor of the spare circuit element block 2000A is not used, the transistor of the operating high-frequency signal circuit element (transistor) block 1000A is connected between adjacent wiring layers. And the high-frequency coupling with the substrate resistance has been a problem, however, since the third metal wiring layer 14 of the spare circuit element block 2000A is fixed to the ground potential (ground). This can reduce the occurrence of such a problem.

Since a stray capacitance exists between the third metal wiring layer 14 and the upper wiring layer, the mesh type plate used in the second embodiment,
It is also possible to apply a slit-type metal wiring layer composed of lines and spaces (stripes) to the third metal wiring layer.

(Embodiment 4) Referring to FIG. 6, a capacitance element according to a fourth embodiment, its operation and a manufacturing method will be described. FIG. 6 is a sectional structural view of the capacitor in this embodiment.

(Cross-Sectional Structure of Capacitive Element) Element Block 10
In 00B, on the main surface of the silicon substrate 1, an element isolation region 2 and a well region 3 composed of a first conductivity type impurity (P type impurity) are formed. An upper electrode 21 using a gate electrode covered with a sidewall 6 is provided on a predetermined active region surrounded by the element isolation region 2 with a capacitance insulating film 20 using a gate insulating film interposed therebetween. .

In the well region 3 below the upper electrode 21,
A lower electrode 19 of a capacitive element comprising a high-concentration second conductivity type impurity diffusion layer is provided. The well region 3 is provided so as to surround the lower electrode 19, and is provided such that its layer extends to a lower portion of the element isolation region 2. In addition, the surface of the well region 3 is surrounded by the
An impurity diffusion layer 9 as a second well region of a first conductivity type (P-type impurity) having a high impurity concentration substantially equal to that of the lower electrode 19 for fixing the potential is provided. The element isolation region 2 is also formed outside the impurity diffusion layer 9.

The main surface of the silicon substrate 1 is
0, the impurity diffusion layer 9 and the upper electrode 2
Plug electrodes 11a, 11b, 11c for setting the potentials of the first and lower electrodes 19 are provided.

The potential of each electrode and the like is applied to the upper electrode 21 via the first metal wiring layer 12 of the first layer and to the lower electrode 19 via the second metal wiring layer 13 of the second layer. Is supplied to the impurity diffusion layer 9 via the third metal wiring layer 14 of the third layer. Note that the upper electrode 21 and the lower electrode 19 are
The metal wiring layer 12 and the second metal wiring layer 13 electrically connect to an external element.

The plug electrodes 11a, 11b and 11c for supplying a potential to the impurity diffusion layer 9 are innumerably arranged in an array along the active region, similarly to the structure of the MOS transistor in the first embodiment. . The third metal wiring layer 14 of the third layer includes the capacitor, the element isolation region 2, and
A metal plate having a size that can include the well region 3 is used.

The upper electrode 21 is connected to the high-frequency signal 15 in parallel or to the input stage by the first metal wiring layer 12, and the lower electrode 19 is connected to the ground or the output stage. The impurity diffusion layer 9 is fixed to a ground potential (ground) via the third metal wiring layer 14 and upper wiring (not shown).

The sectional structure of the spare capacitive element in element block 2000B is basically the same as the sectional structure of the capacitive element in element block 1000B. The difference is that the upper electrode 21 and the lower electrode 19
Is connected to the Note that only one of the upper electrode 21 and the lower electrode 19 may be connected to the floating electrode 18.

(Manufacturing Method) Next, referring to FIG. 6, an outline of a method of manufacturing a capacitive element will be described. First, a first conductivity type impurity (P-type impurity) is formed on the main surface of the silicon substrate 1.
, A lower electrode 19 made of a second conductive type impurity (N-type impurity) having a high impurity concentration, and a lower electrode 19 having a high impurity concentration for fixing the potential of the well region 3. An impurity diffusion layer 9 of one conductivity type (P-type impurity) and an element isolation region 2 are formed. Next, on a predetermined active region, the upper electrode 21 is interposed with a capacitance insulating film 20 interposed therebetween.
And a sidewall 6 is formed.

Next, an interlayer insulating film 10 having a predetermined thickness is formed, and an upper electrode 21, a lower electrode 19 and an impurity diffusion layer 9 are formed.
After forming the plug electrode 11a in contact with the first metal wiring layer 12, a first metal wiring layer 12 patterned into a predetermined shape is formed. Further, similarly, an interlayer insulating film 10 having a predetermined thickness is formed,
After forming the plug electrode 11b in contact with the lower electrode 19 and the impurity diffusion layer 9, the second metal wiring layer 13 patterned into a predetermined shape is formed. Further, similarly, after forming an interlayer insulating film 10 of a predetermined thickness and forming a plug electrode 11c in contact with the impurity diffusion layer 9, the capacitor element, the element isolation region 2, and the well region 3 are sized. A third metal wiring layer made of a metal plate is formed.

(Action / Effect) As described above, Embodiment 3
In the case where an unused element block 2000B is provided adjacent to the element block 1000B as in the case of the above, a capacitive element circuit having desired characteristics can be obtained with a small number of changes in manufacturing steps. Further, since the penetration of noise into the upper electrode due to the stray capacitance generated between the element block 1000B and the element block 1000B can be reduced, deterioration of the capacitance element circuit characteristics can be prevented.

Since the above-described capacitance element circuit configuration has the same configuration as that of the above-described MOS transistor circuit, it can be used as a resistance element using a gate electrode of a MOS type semiconductor.

Further, since there is a parasitic capacitance between the third metal wiring layer 14 and the upper wiring layer, the mesh type plate used in the second embodiment,
It is also possible to apply a slit-type metal wiring layer composed of lines and spaces (stripes) to the third metal wiring layer.

As described above, the embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The technical scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0062]

According to the semiconductor device and the method of manufacturing the same according to the present invention, a high-frequency circuit with less noise can be manufactured by using a silicon element by a normal semiconductor device manufacturing process. Further, it is possible to reduce deterioration of circuit characteristics due to stray capacitance of an unused spare semiconductor element.

[Brief description of the drawings]

FIG. 1 is a sectional structural view of a MOS transistor according to a first embodiment.

FIG. 2 is a schematic diagram of the MOS transistor according to the first embodiment as viewed from above.

FIG. 3 is a schematic diagram of a MOS transistor according to a second embodiment as viewed from above.

FIG. 4 is a plan view of the mesh plate 17;

FIG. 5 is a schematic diagram of a MOS transistor according to a third embodiment as viewed from above.

FIG. 6 is a cross-sectional structural view of a capacitive element according to a fourth embodiment as viewed from above.

FIG. 7 is a schematic sectional view of a conventional MOS transistor.

[Explanation of symbols]

Reference Signs List 1 silicon substrate, 2 element isolation region, 3 well region, 4a gate insulating film, 4 gate electrode, 5 channel region, 6 sidewall, 7 drain diffusion layer, 8
Source diffusion layer, 9 impurity diffusion layer, 10 interlayer insulating film, 11a, 11b, 11c plug electrode, 12 first
Metal wiring layer, 13 second metal wiring layer, 14 third metal wiring layer, 15 high frequency signal, 16 high frequency signal, 17 mesh type plate, 17a line, 17b space,
18 floating electrode, 19 lower electrode, 20 capacitance insulating film,
21 upper electrode, 101 silicon substrate, 102 element isolation region, 103 well region, 104 gate electrode,
104a gate insulating film, 105 channel region, 10
6 sidewall, 107 drain diffusion layer, 108
Source diffusion layer, 109 first conductivity type impurity diffusion layer, 1
Reference Signs List 10 interlayer insulating film, 112 first metal wiring layer, 113
Second metal wiring layer, 114 Third metal wiring layer, 1000
A, 1000B, 2000A, 2000B Element block.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 (72) Inventor Yasuyuki Hashizume 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation F term (reference) 5F033 HH07 KK01 KK07 UU05 VV03 VV05 XX23 5F038 AC05 AC06 AC14 EZ20 5F040 DA03 DB01 DC01 EJ02 EK05 FA03 FC11 5F048 AB10 AC01 BA01 BE09

Claims (5)

[Claims] 1. A semiconductor device comprising a semiconductor element provided in a well region, the semiconductor device comprising: a first element for fixing a potential of the well region provided so as to surround the semiconductor element via an element isolation region.
A semiconductor device comprising: a diffusion layer; a plurality of plug electrodes disposed on the first diffusion layer; and a wiring plate provided above the semiconductor element and connected to the plug electrode and fixed at a ground potential. 2. The semiconductor device according to claim 1, wherein a mesh-type wiring layer in which a plurality of wirings are arranged so as to cross each other is used for said wiring plate. 3. A MOS transistor is formed, wherein the semiconductor element includes a gate electrode, and the well region includes a second diffusion layer serving as a source region and a third diffusion layer serving as a drain region. 3. The semiconductor device according to claim 1, wherein at least one of the semiconductor devices is not electrically connected to an element provided outside. 4. The semiconductor element has a capacitor element using a gate electrode of a MOS transistor as an upper electrode and a high-concentration impurity diffusion layer formed in the well region as a lower electrode. 3. The semiconductor device according to claim 1, wherein at least one of the electrodes is not electrically connected to an element provided outside. 5. A step of forming a well region, a step of forming a semiconductor device on the well region, and fixing an electric potential of the well region so as to surround the semiconductor device with an element isolation region interposed therebetween. Forming a first diffusion layer; forming a plurality of plug electrodes on the first diffusion layer; forming a wiring plate connected to the plug electrode above the semiconductor element; Fixing the potential of the wiring plate to the ground potential;
A method for manufacturing a semiconductor device, comprising: