JP2001274127A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which has a planarizing step, capable of achieving a global planarization. SOLUTION: A layer 3 to be polished is formed on a substrate 1 in the form of covering protrudent patterns 2a, 2b, 2c, 2d. The layer 3 is etched off to form a plurality of perforated patterns 5c, 5d on portions C, D which have areas broader than other portions of step tops of the layer 3, where the patterns 5c, 5d are formed such that the polishing quantity distribution in the substrate 1 plane is set uniform. Then the planarizing polishing is made, starting from the surface of the layer 3, to advance the polishing at an equal polishing rate in the substrate 1 plane.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a step of flattening a surface of a substrate on which a convex pattern is formed.

[0002]

2. Description of the Related Art In recent years, with the progress of high integration and high functionality of semiconductor devices as seen in ULSIs and the like, there is a demand for miniaturization of gate electrodes and element isolation regions and reduction of the interval between these devices. It's getting tougher. Although miniaturization largely depends on the exposure technique in the lithography process, the depth of focus at the time of exposure is becoming increasingly narrower due to the shortening of the exposure wavelength accompanying the miniaturization. Therefore, a flattening polishing technique called a chemical mechanical polishing (hereinafter, referred to as CMP) method has been introduced into a manufacturing process of a semiconductor device.

However, the flattening polishing has a property that polishing is difficult to progress in a portion having a large polishing amount, and polishing is easy to progress in a portion having a small polishing amount. For this reason, as shown in FIG. 4A, for example, when the polishing target layer 3 covering the convex patterns 2a, 2b, 2c, and 2d on the surface of the substrate 1 is polished, the area above each step in the polishing target layer 3 is small. Part B or C where the area above the step is larger than that of Part A
Polishing hardly proceeds in the portion and the D portion, and as a result, a global step is left on the polished surface.

Therefore, as shown in FIG. 4 (2), as a pre-process for flattening and polishing, the layer 3 to be polished is subjected to pattern etching to form a portion B or C having a large area above the step in the layer 3 to be polished. Each of the convex patterns 2b to 2
An inversion pattern removal step of forming the removal patterns 4b, 4c, and 4d inverted with respect to d is performed. This reduces the amount of polishing of the polished layer 3 in the B portion, the C portion, and the D portion.

In the inversion pattern removing step, a resist pattern is formed by lithography for exposing the inversion patterns of the underlying patterns 2b to 2c in each part.
The polished layer 3 is etched using this resist pattern as a mask. At this time, the punching pattern 4b of each part,
4c and 4d are the respective convex patterns 2 arranged on each of them.
In some cases, the distance may be smaller or larger than b, 2c, or 2d by a fixed amount. Here, the cut patterns 4b, 4
The case where c and 4d are smaller than the convex patterns 2b, 2c and 2d is shown. In addition, for example, the arrangement state of the underlying pattern 2d is dense as shown in part D, so that the
In a portion where the area above the step becomes large, the base pattern 2d is formed as one large pattern to form the cutout pattern 4d. Further, the minimum area or the minimum line width of the portion of the layer to be polished 3 where the punched pattern is to be formed is determined so that the portion of the layer to be polished such as the portion A where the area above the step is small is not etched. This part is kept covered with the resist pattern.

[0006]

However, the method of manufacturing a semiconductor device which performs such planarization polishing has the following problems. That is, when forming a punched pattern inverted with respect to the base pattern on the layer to be polished, as shown in the plan view of FIG.
One large blanking pattern 4c, 4 corresponding to the area
d will be formed. For this reason, the cutout patterns 4c and 4d having a larger area than the part B are formed in the part C and the part D where the area above the step is large, and the polishing amount is excessively reduced.

As a result, as shown in FIG. 6, the polished surface at the portion C or D becomes lower than the portion A or B, and a step H is formed on the polished surface of the layer 3 to be polished. There is a problem in that global flattening with high accuracy cannot be performed.

Further, as shown in FIG.
When the polishing is performed up to the convex patterns 2a to 2d under the polished layer 3 when the polished layer 3 covering the to-be-polished layer 3 is flattened and polished from the surface side, a convex material different from the polished layer 3 during the polishing is used. The patterns 2a to 2d will appear on the polished surface.
Here, the base of the polishing target layer 3 (that is, the convex patterns 2a to 2d in this case) is usually made of a material having a lower polishing rate than the polishing target layer 3. Therefore, the polishing rate of a portion where the ratio of the exposed area of the convex patterns 2c and 2d is large, such as the portion C and the portion D, is lower than that of the portion A or the portion B.

Therefore, in this case, even if the polished layer 3 can be polished to have a flat surface, the convex patterns 2a to 2d
Polished, the polished surface in the C portion and the D portion becomes higher than the A portion and the B portion, and it becomes difficult to perform global planarization.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of achieving global flattening of a polished surface.

[0011]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises forming a layer to be polished on a substrate while covering the convex pattern on the surface of the substrate. After forming a plurality of punched patterns formed by etching and removing the polished layer for each portion having a larger area than the other portions in the upper portion of the step of the polished layer, the surface of the polished layer is formed. It is characterized in that flattening polishing is performed from the side.

Here, in the step of forming the cut pattern, the cut pattern is formed so that the polishing amount distribution in the substrate surface becomes uniform.

In the method of manufacturing a semiconductor device in which such a step is performed, a plurality of cutout patterns are arranged for each portion having a large area above the step of the layer to be polished. The formation of the cut pattern having the area is prevented, and the formed portion of the cut pattern is divided and dispersed. Therefore, the upper portion of the step of the layer to be polished is more evenly arranged on the substrate surface, and the variation in the polishing amount of the layer to be polished in the substrate surface is suppressed.

Here, in the step of forming the blanking pattern, the blanking pattern is formed so that the distribution of the polishing amount in the substrate surface becomes uniform. It is uniformed in the plane.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the drawings. The same members as those described in the related art with reference to the drawings are denoted by the same reference numerals.

(First Embodiment) FIG. 1 is a sectional process view for explaining the manufacturing method of the first embodiment, and FIG. 2 is a plan view for explaining the manufacturing method of the first embodiment. ,
Hereinafter, the first embodiment of the present invention will be described with reference to these drawings.

First, as shown in FIG. 1A, a plurality of convex patterns 2a to 2d are formed on the front side of the substrate 1. These convex patterns 2a to 2d are formed, for example, on the substrate 1
What is obtained by patterning the material layer provided above,
The pattern is a pattern formed by patterning the surface layer of the substrate 1 and has the same height here.

At a portion A on the substrate 1, convex patterns 2a having a small area in plan view are provided at predetermined intervals. Further, the B pattern on the substrate 1 has a convex pattern 2b having a larger area than the A pattern.
Is provided. Further, a convex pattern 2c having a larger area than that of the part B is provided in the part C on the substrate 1. Further, in the D portion on the substrate 1, the convex pattern 2 of the A portion is provided.
The convex pattern 2d having the same area as the area a is provided more densely than the area A.

Then, a polished layer 3 having a thickness greater than the height of the convex patterns 2a to 2d is formed on the substrate 1 in a state where the spaces between the convex patterns 2a to 2d are buried.

On the surface of the layer 3 to be polished, a step h follows the shape of the base. For this reason, the upper portion of the step of the layer 3 to be polished (hereinafter simply referred to as the upper portion of the step) is independently arranged in the portion A in a state corresponding to each of the convex patterns 2a. In the part B, the upper part of the step is arranged corresponding to the convex pattern 2b. The upper part of the step in this part B is A
The area is wider than the upper part of each step in the portion. In the portion C, the upper part of the step is arranged corresponding to the convex pattern 2c. The upper part of the step in the part C has a larger area than the upper part of the step in the part B. Further, in the portion D, an integrated step upper portion is arranged so as to be continuous on each pattern 2d. It is assumed that the upper part of the step in the part D has approximately the same area as the upper part of the step in the part C.

Next, in order to flatten the surface of the layer 3 to be polished, prior to flattening and polishing the layer 3 to be polished from its surface side, as shown in FIG. The patterns 5b, 5c, 5d are formed. These removal patterns 5b, 5c and 5d are formed to a depth approximately equal to the step h of the polished layer 3 by etching the polished layer 3 using a resist pattern formed by lithography as a mask. Shall be done.

At the time of this etching, the minimum area of the upper portion of the step where the blank pattern is to be formed is determined based on the area and the line width of the upper portion of each step (hereinafter, typically referred to as area). Then, one punched pattern 5b is formed in a portion having a step upper portion having the minimum area (here, portion B), and in a portion (here, portion A) in which the area of each step upper portion is smaller than the portion B, Cover with a resist pattern so that a blank pattern is not formed.

Further, as shown in the plan view of FIG.
In the C part and the D part where the area of the step upper part is larger than the B part,
A plurality of blanking patterns 5c and 5d are respectively formed.

Here, each of these cut patterns 5b, 5
The sizes of c and 5d, the arrangement state thereof, and the ratio of these cut patterns 5b, 5c and 5d in the C and D portions are set as follows based on the actual polishing amount of the polished layer 3 in each portion. Shall decide. However, here, in order to simplify the calculation of the actual polishing amount, each of the convex patterns 2a to 2d
Is a linear example.

The portion where no punching pattern is formed (A
Va) = h × b where b is the area ratio (%) of the upper part of the step in part A. The actual polishing amount Vb of the portion where one punched pattern is formed (portion B) is as follows: Vb = h × e × (cd) / c where c is the width of the upper part of the step in the portion B, and d is the punching amount. It is the width of the pattern 5b, and e is the area ratio (%) of the upper part of the step in the B portion. Part where a plurality of punching patterns are formed (C part and D part)
The actual polishing amounts Vc and Vd are, for example, when the portion C is taken as an example. Vc ≒ h × i × g / (d + g) where d is the width of the cut pattern 5c and g is the cut pattern 5c in the C portion. And i is the area ratio (%) of the upper part of the step in the portion C.

From these equations, the actual polishing amounts Va, Vb,
D and g that minimize the difference between the values of Vc and Vd
Are obtained, and the cutout patterns 5b, 5c,
5d is formed in the B portion, the C portion, and the D portion. In particular, a plurality of cutout patterns 5c and 5d are formed at equal intervals g in the C portion and the D portion.

After the above, as shown in FIG.
The polished layer 3 is polished from the surface side by the P method, and the surface of the polished layer 3 is flattened.

According to the above-described manufacturing method, the cutout patterns 5a to 5d are arranged in the portions B, C, and C where the area above the step of the layer 3 to be polished is large. Since the plurality of independent punching patterns 5c and 5d are respectively arranged in the C portion and the D portion where the area of the polishing target is large, it is prevented that a large area punching pattern is formed in a part of the layer 3 to be polished. Thus, the portions where the punched patterns 5b to 5d are formed are dispersed on the substrate 1 surface. Therefore, after the formation of the punched pattern, the arrangement of the stepped portion (that is, the polished surface) of the layer 3 to be polished in the surface of the substrate 1 is made uniform, and the variation in the polishing amount of the layer 3 to be polished in the surface of the substrate 1 is suppressed. .

In particular, in the portions A to D, the cutout patterns 5b to 5d are arranged so that the actual polishing amount becomes uniform, so that the polishing rate in the surface of the substrate 1 can be made uniform. Therefore, as shown in FIG. 1C, it is possible to obtain a flattened surface in which the global step H1 is suppressed to be small. As a result, it is possible to improve the precision of the subsequent fine processing on the polished layer 3.

(Second Embodiment) In this embodiment, when polishing is performed from the surface side of the layer to be polished in the same manner as in the manufacturing method described in the first embodiment, the polishing extends to the base of the layer to be polished. Will be described.

First, similarly to the first embodiment described with reference to FIG.
The polished layer 3 is covered while covering 2d. Convex pattern 2a-
2d and the layer to be polished 3 are the same as in the first embodiment. However, the convex patterns 2a to 2d and the polished layer 3 are made of different materials.

The polished layer 3 and the convex pattern 2a
2d is polished from the surface side of the layer 3 to be polished from the surface side of the layer 3 to flatten the surface. Exposure of the patterns 2a to 2d complicates the planarization technique.

Therefore, prior to performing the flattening polishing, FIG.
As shown in (1), the removal pattern 6b,
6c and 6d are formed. These cut patterns 6b, 6
Similar to the first embodiment, c and 6d are portions B, C, and D having the same depth as the step h of the layer 3 to be polished by the lithography technique and the subsequent etching of the layer 3 to be polished.
It is formed on each part of the part.

Here, each of the cut patterns 6b, 6
The sizes and arrangement states of c and 6d, and the ratios of the cut patterns 6b, 6c and 6d in the C and D sections are set as follows based on the actual polishing amounts of the respective sections, for example. . However, here, in order to simplify the calculation, a case where each of the convex patterns 2a to 2d is linear is taken as an example.

The step h of the layer 3 to be polished and the depth of the punched pattern are substantially the same, and the underlying convex patterns 2a to 2d are formed.
Is set to k, and the polishing rate v2 of the material forming the polished layer 3 with respect to the polishing rate v1 of the material forming the convex patterns 2a to 2d (that is, v2 / v1) is set to s. Generally, polishing is performed under the condition that the polishing rate v1 of the convex patterns 2a to 2d is lower than the polishing rate v2 of the layer 3 to be polished. Further, Va, Vb, and Vc are the actual polishing amounts of the polished layer 3 in the portions A to C described in the first embodiment. The thickness from the lower part of the step of the layer 3 to be polished to the upper part of the convex patterns 2a to 2d is defined as j.

The portion where no punching pattern is formed (A
Va) = Va + k × {b ′ × s + (1-b ′)} + j ×
100 where b 'is the area ratio (%) of the convex pattern 2a in the portion A. The actual polishing amount Vb ′ of the portion where one punched pattern is formed (part B) is as follows: Vb ′ = Vb + k × {e ′ × s + (1-e ′)} + j ×
100 where e 'is the area ratio (%) of the convex pattern 2b in the portion B. Part where a plurality of punching patterns are formed (C part and D part)
The actual polishing amounts Vc ′ and Vd ′ are, for example, in the case of part C, as follows: Vc ≒ Vc + k × {i ′ × s + (1-i ′)} + j × 1
Here, i ′ is the area ratio (%) of the convex pattern 2c in the portion C.

In each of these equations, the first item indicates the polishing amount at the step h, the second item indicates the polishing amount at the polishing thickness k of the underlying convex patterns 2a to 2d, and the third item indicates the polishing amount. The polished amount in the thickness j portion from the lower part of the step of the layer to be polished 3 to the upper part of the convex patterns 2a to 2d is shown.

From these equations, the actual polishing amounts Va ′, V
d and g are determined so that the difference between the values of b ′, Vc ′ and Vd ′ is the smallest, and the pattern 6 having a width d corresponding to this is determined.
b, 6c, and 6d are formed in the B portion, the C portion, and the D portion. In particular, a plurality of punched patterns 6c, 6d
Are formed at equal intervals g.

After the above, as shown in FIG.
By the P method, the polishing target layer 3 and the convex patterns 2a to 2d are polished from the surface side of the polishing target layer 3 until the polishing removal thickness k of the convex patterns 2a to 2d is reached, thereby obtaining a flat surface.

According to such a method, even when the underlayers having different polishing rates are exposed on the polishing surface, the polishing of the layer to be polished can be performed within a range in which the polishing rates of the underlayer and the layer to be polished are considered. Since the punched pattern is arranged so that the amount becomes more uniform, the polishing rate in the substrate surface can be made uniform as in the first embodiment, and a flat surface with a reduced global step can be obtained. Will be possible.

For example, in a STI (shallow trench isolation) step performed in the manufacture of a semiconductor device, a convex pattern whose surface layer is made of silicon nitride is covered with a silicon oxide film, and the silicon oxide film is coated on the silicon nitride from the surface side. The entire surface is polished and flattened by the CMP method. At this time, by forming the punched pattern as in the second embodiment, even if silicon nitride is exposed on the polished surface, a polished surface with a flat surface can be obtained as a result.

In each of the above-described embodiments, the convex patterns 2a to 2d are simplified to have a linear shape in order to simplify the calculation of the actual polishing amount. Therefore, the actual polishing amount is calculated by classifying the convex patterns into representative shapes. Also, the formula for calculating the actual polishing amount is not limited to the formula shown in each embodiment, and the calculation accuracy is further improved by using a coefficient as needed.

[0043]

As described above, according to the method of manufacturing a semiconductor device of the present invention, polishing is performed in a state in which a plurality of cutout patterns are provided for each portion having a large area above the step of the layer to be polished. With this configuration, the polishing amount of the layer to be polished can be made uniform within the substrate surface, and global flattening can be achieved. As a result, it is possible to improve the subsequent fine processing accuracy.

[Brief description of the drawings]

FIG. 1 is a sectional process view showing a manufacturing method of a first embodiment.

FIG. 2 is a plan view illustrating the present invention.

FIG. 3 is a sectional process view showing a manufacturing method of a second embodiment.

FIG. 4 is a sectional process view showing an example of a conventional technique.

FIG. 5 is a plan view showing an example of a conventional technique.

FIG. 6 is a cross-sectional view illustrating an example of a problem in the related art.

FIG. 7 is a cross-sectional view illustrating another example of the problem of the related art.

[Explanation of symbols]

1 ... substrate, 2a, 2b, 2c, 2d ... convex pattern, 3 ...
Layer to be polished, 5b, 5c, 5d, 6b, 6c, 6d...

Claims (2)

[Claims] A step of forming a layer to be polished on the substrate in a state of covering the convex pattern on the surface of the substrate; A semiconductor comprising: a step of forming a plurality of punched patterns formed by etching and removing the layer to be polished for each portion; and a step of performing flattening polishing from the surface side of the layer to be polished. Device manufacturing method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein, in the step of forming the blanking pattern, the polishing amount distribution is uniform in the substrate surface in the step of performing the planarization polishing. A method for manufacturing a semiconductor device, comprising forming a punched pattern.