JP2001273779A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate a main cause of generating an error read-out data caused by dispersion of coupling capacitor between an upper side bit line and a lower side bit line. SOLUTION: This device is provided with switches S1A, S2B short-circuiting a bit line BL0 of a data side of upper bit lines BL0, BBL0 and a bit line BBL1 of a reference side of lower bit lines BL1, BBL1 in accordance with activation of a control signal A0, a switch S2 connecting/cutting off the bit lines BL0, BBL0 and a sense amplifier SA0 in accordance with activation/non-activation of a control signal B0, and a switch S3 connecting/cutting off the bit lines BL0, BBL0 and the bit lines BL1, BBL1 in accordance with activation/non- activation of a control signal C0.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device comprising a multi-level memory cell in which one memory cell holds two or more bits.

[0002]

2. Description of the Related Art In recent years, in order to reduce the size of a semiconductor memory device, a multi-valued memory capable of storing multi-bit information in one memory cell has been developed. This multi-valued memory has EE
In a PROM, a threshold value of a memory cell is changed in multiple stages so that one or more bits of information (data) can be stored in one memory cell. In a dynamic semiconductor memory device (DRAM), a memory is stored. There are various schemes such as one in which charge is divided into multiple stages and one or more bits of data can be stored in one memory cell.

A semiconductor memory device using these multi-valued memory cells has a smaller number of memory cells than a cell in which only one bit of data can be stored in one memory cell, that is, a general memory device consisting of one bit cell. Therefore, it is possible to reduce the size of the storage device, and furthermore, the semiconductor device including the storage device as one component.

However, a semiconductor memory device using a multi-level cell requires a circuit configuration different from a general circuit configuration for driving a 1-bit cell due to the specificity of the cell.

For example, a DRAM using a binary memory cell
The conventional semiconductor memory device described in Japanese Patent Application Laid-Open No. 9-282891 (Document 1) requires two sense amplifiers for one bit line, and requires a predetermined coupling capacity when reading 2-bit data. And read it out.

Referring to FIG. 8 which is a simplified circuit diagram of the conventional semiconductor memory device described in Document 1, this conventional semiconductor memory device has a binary memory cell CL and reading of upper bits and lower bits. Complementary bit lines (pairs, hereinafter omitted unless otherwise specified) BL0, BBL0
, BL1, BBL1, one word line WL, an upper bit sense amplifier SA0 connected to the bit lines BL0, BBL0, a lower bit sense amplifier SA1, connected to the bit lines BL1, BBL1, and a control signal C0. In response to the activation / inactivation of the bit lines, conducts / blocks the upper bit lines BL0, BBL0 and the lower bit lines BL1, BBL1.
And a switch S3 for disconnecting the switch.

Also, there is a clearance between the positive phase side (hereinafter referred to as data side) and the complementary phase side (hereinafter referred to as reference side) of each of the upper and lower bit lines, that is, the bit lines BL0 and BBL1 and the bit lines BBL0 and BL1. Are coupled to each other.

Next, referring to FIG. 8 and FIG. 9 showing a time chart of operation waveforms of respective parts, in a conventional semiconductor memory device, binary 2-bit data "1" is stored in a memory cell CL.
The read operation when "0" is stored will be described. First, each of the upper bit lines BL0 and BBL0 and the lower bit lines BL1 and BBL1 is precharged to a predetermined potential. At this time, the control signal C0 is The switch S3 is activated, and the switch S3 is conductive, and the bit lines BL0 and BL1 and BBL0 and BBL1 are electrically connected.

Next, multi-value data "10" from the memory cell CL is sensed by two sense amplifiers SA0 and SA1, respectively. The word line WL is activated and the bit line B
After outputting the data signals corresponding to the multi-level data "10" to L0 and BL1, the control signal C0 is inactivated and the switch S3 is cut off to separate the regions 100 and 200. Sense amplifier S
A0 senses the data signal corresponding to the data “1” of the higher-order bit read to the bit line BL0, and outputs the bit line pair B
Full swing of L0 and BBL0.

At this time, due to the coupling capacitance Cc,
The potential of the bit lines BL1 and BBL1 on the lower bit side fluctuates. In the case of 2-bit data “10” in this example, the potentials of the bit lines BL1 and BBL1 on the lower bit side are inverted on the data side and the reference side, and “0” data is read.

At this time, if the variation in the coupling capacitance Cc is large, the signal amount of the bit lines BL1 and BBL1 on the lower bit side after the potential is inverted will decrease.
For this reason, the value of the read data becomes uncertain, which is a cause of an error. However, it was actually difficult to manufacture the capacitance value of the coupling capacitance Cc without variation.

[0012]

In the conventional semiconductor memory device described above, when the value of the upper bit and the value of the lower bit are mutually inverted values, the voltage between the upper bit line and the lower bit line is reduced. If the variation in the coupling capacitance is large, the signal amount of the bit line pair on the lower bit side after the potential inversion is reduced, thereby causing an error in the read data, but the variation in the coupling capacitance should be eliminated. There was a drawback that it was difficult to manufacture.

An object of the present invention is to reduce the signal amount of a bit line pair on a lower bit side after a potential is inverted without being affected by a variation in coupling capacitance between an upper bit line and a lower bit line. It is an object of the present invention to provide a semiconductor memory device in which a factor causing an error in read data is eliminated by holding the data stably.

[0014]

According to a first aspect of the present invention, there is provided a semiconductor memory device including: a binary memory cell capable of storing two bits of information in one memory cell; upper bit data and lower bit from the binary memory cell; And an upper bit line pair and a lower bit line pair each comprising a data side bit line and a reference side bit line for reading the data.
The signals corresponding to the upper bit data and the lower bit data read from the value memory cell are passed through a plurality of switches, respectively, to the two bits for the upper bit and the lower bit.
In a multi-level DRAM type semiconductor memory device sensed by two sense amplifiers, a bit line on the data side of the upper bit line pair and a bit on the reference side of the lower bit line pair in response to activation of a first control signal. And a second switch for connecting / disconnecting the upper bit line pair and the upper bit sense amplifier in response to activation / deactivation of a second control signal. And the third
And a third switch for connecting / disconnecting the upper and lower bit line pairs in response to activation / deactivation of the control signal. After reading the bit data, the third switch is turned off to separate the upper bit line pair and the lower bit line pair, and the first switch is connected before reading the lower bit data to connect the first switch. The level of the lower bit line pair is changed by short-circuiting the bit line on the data side of the upper bit line pair and the bit line on the reference side of the lower bit line pair.

Further, a first floating capacitance of a wiring including the upper bit line pair in a first region surrounded by the first, second, and third switches and a second region to which the lower bit line pair belongs. The first, second and third switches are arranged so that a predetermined relationship is established between a second floating capacitance of a wiring including the lower bit line pair and a capacitance of the memory cell. It may be a feature.

According to a second aspect of the present invention, there is provided a semiconductor memory device capable of storing two-bit information in one memory cell, and reading out upper bit data and lower bit data from the binary memory cell. An upper bit line pair and a lower bit line pair each comprising a bit line on a data side and a reference side, and the upper bit line read from the binary memory cell connected to the upper bit line pair and the lower bit line pair, respectively. In a multi-level DRAM type semiconductor memory device in which signals corresponding to bit data and lower bit data are sensed by two sense amplifiers for upper bits and lower bits via a plurality of switches, respectively, In response to the activation of the signal, the bit line on the data side of the upper bit line pair and the bit line on the reference side of the lower bit line pair are activated. And a second switch for connecting / disconnecting the upper bit line pair and the upper bit sense amplifier in response to activation / deactivation of a second control signal. A switch, and a third switch for connecting / disconnecting the upper and lower bit line pairs in response to activation / deactivation of a third control signal, wherein the second and third switches are connected to each other. After reading the lower bit data, the third switch is turned off to separate the upper bit line pair from the lower bit line pair, and the first switch is read before reading the upper bit data. To short-circuit the bit line on the data side of the upper bit line pair and the bit line on the reference side of the lower bit line pair to change the level of the upper bit line pair. is there.

Further, a first floating capacitance of a wiring including the lower bit line pair in a first region surrounded by the first, second, and third switches and a second region to which the upper bit line pair belongs. And arranging the first, second and third switches so that a predetermined relationship is established between the second floating capacitance of the wiring including the upper bit line pair and the capacitance of the memory cell. It may be a feature.

According to a third aspect of the present invention, there is provided a semiconductor memory device comprising: a memory cell array including first and second binary memory cells capable of storing two bits of information in one memory cell;
And an upper bit line pair and a lower bit line pair each comprising a common data side and a reference side bit line for reading out upper bit data and lower bit data from the second binary memory cell, The upper bit line pair and the lower bit line pair respectively correspond to the upper bit data and the lower bit data read from the memory of the selected one of the first and second binary memory cells. In a multi-level DRAM type semiconductor memory device in which a signal is sensed by two sense amplifiers for upper bits and lower bits via a plurality of switches, the upper bit sense amplifier is connected to one end of the memory cell array. Lower bit sense amplifiers are arranged at the other end of the memory cell array, respectively, to activate the first control signal. A first switch for short-circuiting a bit line on the data side of the upper bit line pair and a bit line on the reference side of the lower bit line pair in response to the activation, and activating / deactivating a third control signal A third switch for connecting / disconnecting each of the upper and lower bit line pairs in response to the above, and a sense amplifier for the upper bit in response to the activation / deactivation of a second control signal. A second switch for connecting / disconnecting the upper bit line pair to / from the third switch; and a second switch connected to the lower bit sense amplifier in response to activation / deactivation of a fourth control signal. A fourth switch for connecting / disconnecting the lower bit line pair and the third switch, wherein the first to fourth switches are arranged in the middle of the first and second sense amplifiers; When one memory cell is selected, After the second and third switches are connected and the upper bit data is read, the third switch is turned off to separate the upper bit line pair and the lower bit line pair, and the lower bit data is read. Before reading, the first switch is connected to connect a part of the bit line on the data side of the upper bit line pair, the bit lines on the reference side of the lower bit line pair, and the bit on the reference side of the upper bit line pair. The level of the lower bit line pair is changed by short-circuiting a part of the line and the bit lines on the data side of the lower bit line pair, and when the second memory cell is selected, the fourth and the fourth memory cells are selected. A third switch is connected, and after reading the data of the lower bit, the third switch is turned off to separate the upper bit line pair from the lower bit line pair, Before reading the data, the first switch is connected to connect a part of the bit line on the data side of the lower bit line pair to the bit line on the reference side of the upper bit line pair and the reference side of the lower bit line pair. The level of the lower bit line pair is changed by short-circuiting a part of the bit line and the bit lines on the data side of the upper bit line pair.

A semiconductor memory device according to a fourth aspect of the present invention is a multi-valued memory cell capable of storing m (an integer of 2 or more) +1 bit information in one memory cell, and a multi-valued memory cell out of the m + 1 bits from the multi-valued memory cell. An upper bit line pair and a lower bit line pair each comprising a data side and a reference side bit line for reading arbitrary two-bit upper bit data and lower bit data of the multi-valued memory cell A multi-valued DRAM type semiconductor memory device having means for sensing signals corresponding to the upper bit data and the lower bit data of the multi-valued data read from the memory by m + 1 sense amplifiers through a plurality of switches, respectively. , For each of the (m + 1) sense amplifiers, read out the signal of the upper bit corresponding to the data of the upper bit that is the relevant bit. And a reference bit line of a lower bit line pair for reading a signal of a lower bit corresponding to data of a lower bit of the bit, and a reference bit line of the upper bit line pair A first switch for short-circuiting the data bit line of the lower bit line pair and a second switch, respectively.
A second switch for connecting / disconnecting the upper bit line pair and the sense amplifier for the upper bit in response to activation / deactivation of the control signal, and activation / deactivation of a third control signal A third switch for connecting / disconnecting the upper and lower bit line pairs in response to the switching, and connecting the second and third switches in the first sense amplifier that senses first. After reading the upper bit data, the third switch is turned off to separate the upper bit line pair from the lower bit line pair, and the first switch is connected before reading the lower bit data. A first sense cycle is performed in which the bit line on the data side of the upper bit line pair and the bit line on the reference side of the lower bit line pair are short-circuited to change the level of the lower bit line pair. A second sense amplifier performs a second sense cycle on the level of the lower bit line in the same procedure as that of the first sense cycle, and thereafter performs the same operation as the first sense cycle until the (m + 1) th sense cycle. By repeating the procedure, the data of m + 1 bits is read.

[0020]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

In the semiconductor memory device of the present embodiment, in a DRAM using multi-valued memory cells for storing multi-valued data of 2 bits or more in one memory cell, the upper bit is sensed by a higher bit sense amplifier. A sense amplifier disconnection switch for disconnecting the sense amplifier from the bit line of the upper bit, and a short-circuit switch for short-circuiting the upper bit line and the lower bit line after disconnecting the upper bit sense amplifier and the bit line are provided. When reading lower-order bit data to be read out sequentially and read out later, it is possible to read out multi-valued data by short-circuiting the upper bit line that was read earlier and the lower bit line that is read later. This makes it possible to use two bits without using coupling capacitors, which make it difficult to manufacture capacitance values without variation. Wherein the reading stored data above.

Further, in order to prevent the capacity of the bit line pair from which data is read later from being different between the case where the memory cell is connected to the bit line and the case where the memory cell is not connected, the bit line connected to the memory cell is used. Read the other side first.

Further, by connecting a plurality of sense amplifiers to a bit line, two sense amplifiers stored in one memory cell can be connected.
It is possible to read multi-value data of more than bits.

Next, the embodiment of the present invention will be described with reference to FIG. 1 which is similarly shown in a circuit diagram with common reference characters / numerals added to components common to FIG. The semiconductor memory device according to the first embodiment has a common binary memory cell CL
And two pairs of complementary bit lines BL0, BBL0 and BL1, BBL1 for reading the upper bit and the lower bit, respectively.
, One word line WL and bit lines BL0, BBL0
After the data read from the memory cell CL to the upper bit line bit lines BL0 and BBL0 is output, and the lower bit sense amplifier SA1 connected to the bit lines BL1 and BBL1 and the upper bit line BL0 and BBL0 are output. In response to activation / inactivation of a control signal C0 for cutting off the memory cell side circuit and the sense amplifier SA0 when the data is sensed by the sense amplifier SA0, the memory cell CL and the bit lines BL0 and BBL0 are connected to each other. In addition to the switch S3 for conducting / cutting off the connection, the control signal B0 is activated /
A switch S2 for connecting / disconnecting the connection between the sense amplifier SA0 and the bit lines BL0, BBL0 on the upper bit side in response to the inactivation, and an activation / activation of the control signal A0 after the upper bit is sensed by the sense amplifier SA0. Switches S1A and S1A for short-circuiting upper bit lines BL0 and BBL0 and lower bit lines BL1 and BBL1 in response to inactivation.
S1B.

The switch S1A responds to activation / inactivation of the control signal A0 by turning on the bit line BL0 and the bit line BBL.
1 and the switch S1B is connected to the bit line BBL.
0 is connected / disconnected with the bit line BL1.

Each of the switches S1, S2, S3 can be formed of, for example, a transfer gate composed of an N-channel or P-channel MOS transistor having a gate as a control electrode and conducting / cutting off between a drain and a source. Since the semiconductor memory device has a complementary structure, the arrangement of the circuit elements below the lower-order bit side positive-phase (hereinafter, data) side bit line BL1 and the complementary-phase (hereinafter, reference) side bit line BBL1 is the same as described above. Configuration.

In FIG. 1, switches S3, S2, S1
A, bit lines BL0 and BBL in region 1 surrounded by S1B
The stray capacitance of the wiring including 0 is Cx, and the lower bit line BL
Bit lines BL1 and BBL in region 2 to which
When the stray capacitance of No. 1 is Cb, the capacitance of the memory cell CL is Cs, and the capacitance of each bit line in the sense amplifiers SA0 and SA1 is ignored, the following relationship holds between the capacitances Cx, Cb, and Cs. To be designed. Cx = (1/3) · {Cs · (Cx + Cb)} / (Cx + Cb + Cs) (1/3) Cs (1) That is, the bit lines BL0, The stray capacitance Cx of the wiring including BBL0 is set to be approximately 1/3 of the capacitance Cs of the memory cell CL.

The wiring stray capacitance Cx in the area 1 is determined by the switch S
3, S2, S1A, and S1B are changed depending on the positions or arrangements, and as described later, are adjusted to an optimum value that satisfies the expression (1) in the finishing process at the time of manufacturing the semiconductor memory device of the present embodiment.

Next, the operation of the present embodiment will be described with reference to FIG. 1 and FIG. 2 showing the operation timing in a time chart. First, two bits of binary data "00" are stored in one memory cell CL. "," 01 "," 10 ",
One of the four values “11” is stored.

Referring to FIG. 3, which shows an example of the read level corresponding to each data of the memory cell CL, the level of the highest level data "11" is DV, the level of the lowest level data "00" is 0, and the level thereof is 0. The difference VD is divided into three equal parts, and the intermediate data “10” and “01” are respectively divided by 2 /
3 VD, 1/3 VD. The center level 1/2 VD of the highest and lowest levels is set as a reference potential, that is, a precharge potential.

As an example, data “1” is stored in the memory cell CL.
The read operation when "0" is stored will be described. First, each of the upper bit lines BL0 and BBL0 and the lower bit lines BL1 and BBL1 is precharged to a reference potential, in this example, 1/2 VD. At this time, the control signals C0 and B0 are activated, and the switches S3 and S2 are activated.
Is conductive, so that bit lines BL0 and BL1 and BBL0 and BBL1 are electrically connected, and sense amplifier SA0 and bit lines BL0 and BBL0 are also connected. On the other hand, the control signal A0 is in an inactive state, the switches S1A and S1B are shut off, and thus the bit lines BL0 and BBL1 and BBL0 and BL1 are disconnected.

Next, the multi-value data "10" from the memory cell CL is sensed sequentially by the two sense amplifiers SA0 and SA1. The word line WL is activated and the bit line BL
A data signal corresponding to multi-level data "10", that is, 2/3 VD is output to 0 and BL1.

At this time, the potentials of the bit lines BL0 and BL1 fluctuate by a minute potential dV with respect to the precharge potential 1 / 2VD, and become {(1/2) VD + dV}. The sense amplifiers SA0 and SA1 are designed to be able to perform a sensing operation at the potential dV. Further, the data “0” of the memory cell CL
Bit lines BL0 and BL0 for 0 corresponding to "0", 1/3 VD corresponding to data "01", and VD corresponding to data "11", respectively.
The potential of BL1 is ｛(1/2) VD-3d, respectively.
V｝ ｛(１ ／) VD−dV｝ ｛(１ ／) VD + 3d
V｝.

A data signal corresponding to multi-level data "10", that is, 2/3 VD is output, and bit lines BL0, BL
1 becomes {(1/2) VD + dV}, the control signal C0 is deactivated and the switch S3 is cut off, and the upper bit lines BL0 and BBL0 and the lower bit lines BL1 and BL1 are turned off.
BBL1, that is, regions 1 and 2 are electrically separated.

The sense amplifier SA0 has a potential ｛(1/2) VD corresponding to the data “10” read to the bit line BL0.
+ DV} and sense upper bit lines BL0, BBL0
To the potential difference between the potential VD and the potential 0. In this example, the potential of the data bit line BL0 is set to the potential VD,
The potential of the reference bit line BBL0 becomes 0. Since the potential difference dV is small compared to the precharge potential 1/2 VD, these potential changes can be regarded as approximately 1/2 VD, respectively.

Next, the control signal B0 is inactivated to turn off the switch S2, and the sense amplifier SA0 is disconnected from the upper bit lines BL0 and BBL0. Next, the control signal A0 is activated to make the switches S1A and S1B conductive, and the bit lines BL0 and BBL1 and the bit lines BBL0 and BBL are turned on.
L1 is short-circuited to change each potential of the lower bit line pair, that is, the bit lines BL1 and BBL1.

The bit line BL1 is set to ｛(1/2) VD + d
As the potential of the bit line BBL0 drops from V｝ to the potential 0 of the bit line BBL0, the potential of the bit line BBL1 falls to ｛(1 /
2) As the potential of VD + dV} rises to the potential VD of bit line BL0, the potential of bit line BL0 rises.
The potential of each of BL1 is reversed.

The signal difference Vr between the data side of the bit line and the reference side of the voltage read from the memory cell CL when the maximum potential VD is held is the area 1 because the switch S3 at the time of reading is conductive. And the region 2 are connected, and the effective capacity of the load composed of these regions 1 and 2 is Cx + Cb, so that Vr = VD / ｛1+ (C
x + Cb) / Cs}. Therefore, the signal difference 2dV between the levels is 2dV = VD / ｛3 × ｛1+ (Cx + C
b) / Cs}.

That is, dV = (1/2). (1/3)
DVＤCs / (Cs + Cx + Cb)

Next, after sensing by the sense amplifier SA0,
Switches S3 and S2 are turned off, and switches S1A and S1B
Is turned on, the increased charge corresponding to the potential VD of the bit line BL0 is applied to the bit line BBL1, the potential of the bit line BBL1 is increased, and the lowered bit line BBL0
Is applied to the bit line BL1 to lower the potential of the bit line BL1.

At this time, in order to ensure that the potentials of the bit lines BL1 and BBL1 are inverted, the switches S3, S2 and S1A are switched in the final finishing step in the later-described manufacturing so as to satisfy the above-mentioned equation (1). , S1B have been determined.

Next, the lower sense amplifier SA1 senses the potentials of the bit lines BL1 and BBL1, and reads data "0".

Next, the above-mentioned data "10" or "11"
The final finishing step at the time of manufacturing the semiconductor memory device of the present embodiment will be described using the example of sensing as follows. The word line WL is activated, and the bit lines BL0, BL
After the data signal corresponding to the multi-level data "10" read to 1 is output, the switch S3 is turned off, and the sense amplifier SA0 senses the potential corresponding to the data "1" read to the bit line BL0. , The bit lines BL0 and BBL0 make a full swing. Next, the switch S2 is turned off to disconnect the sense amplifier SA0 from the upper bit lines BL0 and BBL0. Next, the switches S1A and S1B are turned on, the bit lines BL0 and BBL1 and the bit lines BBL0 and BL1 are short-circuited, respectively, and the lower bit line B
Each potential of L1 and BBL1 is changed.

At this time, as a finishing process of the semiconductor memory device, the potential of the reference bit line BBL1 on the lower bit side is changed to read the data potential and the data "11" when the data "10" is read from the memory cell. The position or arrangement of the switches S3, S2, S1A, and S1B is determined so as to match an intermediate potential with the potential on the data side at the time of the switching.

However, the setting of the potential in the finishing step is one example for finishing the semiconductor memory device according to the present embodiment, and in general, the potential of the reference bit line BBL1 is set to be lower than the potential of the memory cell CL. What is necessary is just to set the same value when the data of “11” is read and the data of “10” is read. It is not always a necessary condition that the potential be intermediate between the potential on the data side and the potential on the data side when data "10" is read.

Thereafter, as a continuation of the above finishing step, the sense amplifier SA1 senses the potential of the lower bit lines BL1 and BBL1 and confirms that data "0" or "1" can be read.

When the binary data "01" or "00" is stored in the memory cell CL, the potential of the reference bit line BBL1 on the lower bit side is changed from the data " Position, arrangement, and characteristics of the switches S3, S2, S1A, and S1B so as to match an intermediate potential between the data-side potential when “01” is read and the data-side potential when data “00” is read. ,
Determine characteristic values and the like.

Since the semiconductor memory device of the present embodiment does not require a coupling capacitance, a reduction in the read signal of the lower bit due to the variation in the coupling capacitance does not occur.

Next, referring to FIG. 4, which shows a second embodiment of the present invention in the same manner as FIG. The present embodiment differs from the above-described first embodiment in that a memory cell array is constituted by two memory cells CL0 and CL1 storing binary data of upper bits and lower bits, respectively, Switch S for short-circuiting and dividing lines BL0 and BBL0 and lower bit lines BL1 and BBL1
1, S2, S3 and S4.
This means that S2, S3 and S4 are arranged in the center of the memory cell array, that is, in the middle between the sense amplifiers SA0 and SA1.

Therefore, the upper bit lines BL0, BBL0
Is directly connected to the sense amplifier SA0, and the lower bit line B
L1 and BBL1 are directly connected to the sense amplifier SA1,
The switches S2 and S4 are different from the switch S3 by the upper bit lines BL0 and BBL0 and the lower bit lines BL1 and BB.
Connect / disconnect L1.

Further, each word line WL0, WL1 of the memory cells CL0, CL1 is provided.

With reference to FIG. 4 and FIG. 5 showing the operation waveforms of respective parts in a time chart, the operation of this embodiment will be described focusing on the differences from the first embodiment. The word line WL0 is selected. The sense amplifier SA0
, The switch S2 is turned off, and the switch S1 is turned on, so that a part BL0P of the bit line BL0 and the bit line B2 are turned on in the same manner as in the first embodiment.
BL1 and a part of the bit line BBL0 and the bit line BL
1 is short-circuited, and the signal of the bit line pair BL1, BBL1 is read by the sense amplifier SA1. Also, the word line WL
1 is selected, the readout is performed by the sense amplifier SA1, then the switch S4 is turned off, and the switch S1 is turned off.
Of the bit line BL1 and BB
L0 and the bit line BL0 and a part BBL1P of the bit line BBL1 are short-circuited to form a pair of bit lines BL0 and BBL.
0 is read by the sense amplifier SA0.

By adopting the above configuration, the voltage level of the lower bit line when a part of the upper bit line and the lower bit line are short-circuited between when the memory cell is connected to the bit line and when it is not connected The occurrence of discrepancies can be suppressed.

Next, a third embodiment of the present invention will be described with reference to FIG. 6, which is a circuit diagram in which components common to those of FIG. 1 are denoted by common reference characters / numbers. This embodiment is different from the first embodiment in that three or more bits of multi-bit data are stored in one memory cell. In this example, m (a positive integer of 2 or more) is used. +1 bit, and m +
One sense amplifier SA0, SA1,... SAm, and a switch for short-circuiting the upper bit line pair for the bit and the lower bit line pair for the lower bit for each sense amplifier. It is.

That is, the sense amplifiers SA0, SA1,.
..Higher bit lines BL0 and BBL corresponding to SAm
0 and lower bit lines BL1a, BBL1a,... Bit lines BLma, BBLma.

Upper bit line BL of sense amplifier SA0
0, BBL0 and switches S10a, S11a operating in response to control signals A0a, A1a for short-circuiting and dividing the lower bit lines BL1a, BBL1a, and switches S20 operating in response to control signals B0, C0, respectively.
S30 is provided.

Upper bit line BL of sense amplifier SA1
1b, BBL1b and lower bit lines BL2a, BBL2
The switches S10b and S11b that operate according to the control signals A0b and A1b for short-circuiting and dividing the switch a, and the switches S that operate according to each of the control signals B1 and C1
21, S31.

Hereinafter, the same configuration up to the sense amplifier SAm is provided.

Referring to FIG. 6 and FIG. 7 showing an example of a read level corresponding to each data of the memory cell CL, the operation of the present embodiment will be focused on the differences from the first and second embodiments. First, in this embodiment, for convenience of description, one memory cell has three bits (m =
The case where the data of 2) is stored and the second data “110” from the highest level is read is shown.

Referring to FIG. 7, the level of the highest level data "111" is DV, and the lowest level data is "00".
The level of “0” is set to 0, and the level difference VD is divided into seven equal parts.
Intermediate data “110”, “101”, “100”,
“011”, “010” and “001” are each 6 /
7VD, 5 / 7VD, 4 / 7VD, 3 / 7VD, 2/7
VD, 1/7 VD. The center level 1/2 VD of the highest and lowest levels is set as a reference potential, that is, a precharge potential.

First, as described in the first embodiment, each of the upper bit lines BL0 and BBL0 and the lower bit lines BL1a and BBL1a is set to the reference potential. In this example,
It is precharged to 1/2 VD. At this time, the control signal C
0 and B0 are activated, and the switches S30 and S20 are conductive, so that the bit lines BL0 and BL1a and BBL0 and BBL1a are electrically connected, and the sense amplifier SA0 and the bit lines BL0 and BBL0 are also connected. It has become. On the other hand, the control signals A0a and A1a are in an inactive state, and the switches S10a and S11a are shut off, so that the bit lines BL0, BBL1a and BBL
0 and BL1a are separated.

Next, the multi-level data "110" from the memory cell CL is sensed by the sense amplifier SA0. The word line WL is activated, and a data signal corresponding to the multi-level data “110”, that is, 6 / 7V is applied to the bit lines BL0 and BL1.
D is output.

At this time, the potentials of the bit lines BL0 and BL1a are set to a small potential sV with respect to the precharge potential １ ／ VD.
And {(1/2) VD + sV}. In addition,
The sense amplifiers SA0, SA1,... SAm (SA2 in this example) are designed to be capable of sensing operation at the potential sV.

A data signal corresponding to multi-level data "110",
That is, 6/7 VD is output, and bit lines BL0, B
After the potential of L1a becomes {(1/2) VD + sV}, the control signal C0 is inactivated to shut off the switch S30, and the upper bit lines BL0 and BBL0 and the lower bit lines BL1a and BBL1a are electrically connected. To separate.

The sense amplifier SA0 has a potential ｛(1/2) corresponding to the data “110” read to the bit line BL0.
VD + sV} and sense upper bit lines BL0, BB
L0 fully swings to a potential difference between the potential VD and the potential 0.

Thereafter, the switch S20 is cut off by inactivating the control signal B0, the sense amplifier SA0 is disconnected from the bit lines BL0 and BBL0, and the control signals A0a and A1a are disconnected.
Is activated, the switches S10a and S11a are closed, and the reference side of the pair of bit lines BL1 and BBL1, that is,
By shorting the bit line BBL1a and the bit line BL0, the level of the bit line BBL1a is changed to the data “11”.
The level is changed to an intermediate level between the read level of “0” and the data “101” (first sense cycle).

Next, in the same procedure as described above, the sense amplifier SA1 sets the bit line pair BL1a, BL1b, BBL1a,
The potential difference between BBL1b (hereinafter BL1, BBL1...) Is amplified to the full swing by the sense amplifier SA1 (second
Sense cycle).

Thereafter, the same procedure as above is repeated, and the bit line B on the reference side of the bit line pair BL2, BBL2 is
By short-circuiting BL2 and the data-side bit line BL1 of the pair of bit lines BL1 and BBL1, the level of the bit line BBL2 is changed to an intermediate level between the read levels of "111" and "110". The potential difference between the pair of bit lines BL2 and BBL2 is amplified (third sense cycle).

In this example, since multi-value data stored in one memory cell is 3 bits, sense amplifier SA2
The above operation completes the read operation, but the above operation is repeated up to the sense amplifier SAm even for multi-valued data of 3 bits or more (m-1) bits (the (m + 1) th sense cycle). This makes it possible to read out 3-bit data stored in one memory cell.

[0070]

As described above, the semiconductor memory device of the present invention comprises a first switch for short-circuiting a data-side bit line of an upper bit line pair and a reference bit line of a lower bit line pair, A second switch for connecting / disconnecting the upper bit line pair and the sense amplifier for the upper bit, and a third switch for connecting / disconnecting the upper and lower bit line pairs to each other; After the switch is connected and the upper bit data is read, the third switch is turned off to separate the upper bit line pair from the lower bit line pair, and the first switch is connected before reading the lower bit data. Since the level of the lower bit line pair is changed by short-circuiting the bit line on the data side of the upper bit line pair and the bit line on the reference side of the lower bit line pair, the coupling capacitance previously required Becomes unnecessary, there is an effect that the error cause of the lower bits of the read data is removed due to variations in the coupling capacitance.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a time chart illustrating an example of an operation in the semiconductor memory device according to the present embodiment;

FIG. 3 is an explanatory diagram showing an example of a read level of each data of the semiconductor memory device of the present embodiment.

FIG. 4 is a circuit diagram showing a second embodiment of the semiconductor memory device of the present invention.

FIG. 5 is a time chart illustrating an example of an operation in the semiconductor memory device according to the present embodiment;

FIG. 6 is a circuit diagram showing a second embodiment of the semiconductor memory device of the present invention.

FIG. 7 is an explanatory diagram showing an example of a read level of each data of the semiconductor memory device of the present embodiment.

FIG. 8 is a circuit diagram showing an example of a conventional semiconductor memory device.

FIG. 9 is a time chart showing an example of an operation in a conventional semiconductor memory device.

[Explanation of symbols]

1,2,100,200 area BL0, BL1, BLm, BBL0, BBL1, BBL
m bit lines CL, CL0, CL1 Memory cells S1, S2, S3, S10, S20, S30, S11
Switch SA0, SA1, SAm Sense amplifier WL, WL0, WL1 Word line

Claims (7)

[Claims] 1. A binary memory cell capable of storing 2-bit information in one memory cell, and a data side and a reference side for reading out upper bit data and lower bit data from the binary memory cell. An upper bit line pair and a lower bit line pair comprising bit lines, the upper bit data and the lower bit data read from the binary memory cell respectively connected to the upper bit line pair and the lower bit line pair. Multi-valued DRAM that senses a signal corresponding to each of a plurality of switches by two sense amplifiers for upper bits and lower bits via a plurality of switches
A first switch for short-circuiting a data-side bit line of the upper bit line pair and a reference bit line of the lower bit line pair in response to activation of a first control signal A second switch for connecting / disconnecting the upper bit line pair and the sense amplifier for the upper bit in response to activation / deactivation of a second control signal; and activation of a third control signal. A third switch for connecting / disconnecting the upper and lower bit line pairs in response to activation / deactivation, and connecting the second and third switches to read the data of the upper bit After that, the third switch is cut off to separate the upper bit line pair and the lower bit line pair,
Before reading the data of the lower bit, the first switch is connected to short-circuit the bit line on the data side of the upper bit line pair and the bit line on the reference side of the lower bit line pair. A semiconductor memory device characterized by changing the level of a line pair. 2. A first region to which a first stray capacitance of a wiring including the upper bit line pair and a second region to which the lower bit line pair belongs, in a first region surrounded by the first, second, and third switches. A second stray capacitance of a wiring including the lower bit line pair,
2. The semiconductor memory device according to claim 1, wherein the first, second, and third switches are arranged so that a predetermined relationship is established between the capacities of the memory cells. 3. A binary memory cell capable of storing 2-bit information in one memory cell, and a data side and a reference side for reading out upper bit data and lower bit data from the binary memory cell. An upper bit line pair and a lower bit line pair comprising bit lines, the upper bit data and the lower bit data read from the binary memory cell respectively connected to the upper bit line pair and the lower bit line pair. Multi-valued DRAM that senses a signal corresponding to each of a plurality of switches by two sense amplifiers for upper bits and lower bits via a plurality of switches
A first switch for short-circuiting a data-side bit line of the upper bit line pair and a reference bit line of the lower bit line pair in response to activation of a first control signal A second switch for connecting / disconnecting the upper bit line pair and the sense amplifier for the upper bit in response to activation / deactivation of a second control signal; and activation of a third control signal. A third switch for connecting / disconnecting the upper and lower bit line pairs in response to activation / deactivation, and connecting the second and third switches to read the data of the lower bit After that, the third switch is cut off to separate the upper bit line pair and the lower bit line pair,
Before reading the data of the upper bit, the first switch is connected to short-circuit the bit line on the data side of the upper bit line pair and the bit line on the reference side of the lower bit line pair. A semiconductor memory device characterized by changing the level of a line pair. 4. A first region of the first region surrounded by the first, second, and third switches, the first stray capacitance of a wiring including the lower bit line pair, and a second region to which the upper bit line pair belongs. A second stray capacitance of a wiring including the upper bit line pair,
4. The semiconductor memory device according to claim 3, wherein the first, second, and third switches are arranged such that a predetermined relationship is established between the capacities of the memory cells. 5. The semiconductor memory device according to claim 2, wherein said predetermined relationship is such that said first stray capacitance is substantially equal to one third of the capacitance of said memory cell. 6. A memory cell array comprising first and second binary memory cells capable of storing 2-bit information in one memory cell, and data of upper bits from the first and second binary memory cells. An upper bit line pair and a lower bit line pair each comprising a common data side and a reference side bit line for reading out lower bit data, and connected to the upper bit line pair and the lower bit line pair, respectively. The signals corresponding to the upper bit data and the lower bit data read from the memory of the selected one of the first and second binary memory cells are respectively transmitted to the upper bit and the lower bit via a plurality of switches. Multi-valued DR sensed by two sense amplifiers for lower bits
In the AM type semiconductor memory device, the upper bit sense amplifier is arranged at one end of the memory cell array, and the lower bit sense amplifier is arranged at the other end of the memory cell array. A first switch for short-circuiting a bit line on the data side of the upper bit line pair and a bit line on a reference side of the lower bit line pair in response to the activation / deactivation of a third control signal A third switch for connecting / disconnecting the upper and lower bit line pairs to each other; and a higher switch connected to the upper bit sense amplifier in response to activation / deactivation of a second control signal. A second switch for connecting / disconnecting the bit line pair and the third switch; and a second bit connected to the lower bit sense amplifier in response to activation / deactivation of a fourth control signal. A fourth switch for connecting / disconnecting the lower bit line pair and the third switch, wherein the first to fourth switches are arranged between the first and second sense amplifiers, When the first memory cell is selected, the second and third switches are connected, and after reading the data of the upper bit, the third switch is turned off to disconnect the upper bit line pair and the lower bit line. Before reading the data of the lower bit, the first switch is connected so that a part of the bit line on the data side of the upper bit line pair and a bit line on the reference side of the lower bit line pair are separated from each other. The level of the lower bit line pair is changed by short-circuiting a part of the bit lines on the reference side of the upper bit line pair and the bit lines on the data side of the lower bit line pair. When a memory cell is selected, the fourth switch and the third switch are connected, and after reading the data of the lower bit, the third switch is shut off to connect the upper bit line pair and the lower bit line pair. Before reading the data of the upper bit, the first switch is connected to connect a part of the bit line on the data side of the lower bit line pair and the bit line on the reference side of the upper bit line pair and the lower bit line. A semiconductor memory device, wherein a level of the upper bit line pair is changed by short-circuiting a part of a bit line on a reference side of the bit line pair and bit lines on a data side of the upper bit line pair. 7. One memory cell contains m (an integer of 2 or more).
A multi-valued memory cell capable of storing + 1-bit information, and any two of m + 1 bits from the multi-valued memory cell.
An upper bit line pair and a lower bit line pair each comprising a data side and a reference side bit line for reading the upper bit data and the lower bit data of the bit, and read the multi-level memory cell. Multi-valued DR having means for sensing signals corresponding to the upper bit data and the lower bit data of the value data by m + 1 sense amplifiers via a plurality of switches, respectively
In the AM type semiconductor memory device, for each of the m + 1 sense amplifiers, a data side bit line of an upper bit line pair for reading a signal of an upper bit corresponding to data of the upper bit being the bit and the bit A reference bit line of a lower bit line pair for reading a lower bit signal corresponding to data of a lower bit of the lower bit line, a reference bit line of the upper bit line pair, and a data side bit line of the lower bit line pair. A first switch for short-circuiting, a second switch for connecting / disconnecting the upper bit line pair and the sense amplifier for the upper bit in response to activation / inactivation of a second control signal; A third switch for connecting / disconnecting the upper and lower bit line pairs in response to activation / deactivation of a third control signal; In the first sense amplifier for sensing, the second
And after connecting the third switch and reading the upper bit data, disconnecting the third switch to separate the upper bit line pair and the lower bit line pair, and before reading the lower bit data. The first switch is connected to the first bit line to short-circuit the bit line on the data side of the upper bit line pair and the bit line on the reference side of the lower bit line pair to change the level of the lower bit line pair. Then, the second sense amplifier that senses performs the second sense cycle on the level of the lower bit line in the same procedure as the first sense cycle, and thereafter performs the operation up to the (m + 1) th sense cycle. A semiconductor memory device which reads out the (m + 1) -bit data by repeating a procedure similar to that of the first sense cycle.