JP2001267314A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, where a surface protective film having a good surface protection operation is formed instead of a multiple layer structure including a silicon nitride surface protective film, and to provide its manufacturing method. SOLUTION: A semiconductor device 25, where a surface protective film 23 constituted of a silicon oxide insulating film, is installed on a semiconductor substrate 16 and at least the surface area of the surface protection film 23 is improved by ion implantation 37 and the manufacturing method are arranged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having good surface protection and an efficient manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, a method for protecting a surface of a semiconductor device is as follows. First, FIG. 10 shows a structural cross-sectional view of a semiconductor device (insulated gate type field effect transistor) 67 according to a conventional technique.

A gate insulating film 64 is formed on a channel (MOS transistor type) region between a source region 57a and a drain region 57b formed in the vicinity of the surface of a semiconductor substrate 56. Electrode 58
And 62 are provided.

This MOS (Metal Oxide Semiconducto)
Between the r) type transistor and the source electrode 61a or the drain electrode 61b, the interlayer insulating film has a reflow property by a chemical vapor deposition method (hereinafter, referred to as a CVD method), and has a trapping effect of absorbing sodium ions. An insulating film (PSG) (phosphosilicate glass) 63 mainly made of SiO ₂ is deposited. Further, an interlayer insulating film (NSG) (non-doped silicate glass) 60, 65 for increasing the film thickness is added, and a machine formed by a plasma CVD method (hereinafter, referred to as P-CVD) as a passivation film thereon. Nitride (P-SiN) 6 as a water-resistant, surface protective film with strong mechanical strength
6 are deposited.

That is, a MOS transistor including a semiconductor substrate 56, source and drain regions 57a and 57b, a gate insulating film 64 and a gate electrode 58, and a source electrode 61a
And a drain electrode 61b and the like form a semiconductor device. An interlayer insulating film (PSG) 63 or 65 or an insulating film (NSG) 6 made of a silicon oxide film between these electrodes.
0, a surface protective film (P-SiN) 66 and the like are formed. The insulating film (NSG) 60 and the interlayer insulating film (PS)
G) The respective film thicknesses with 63 are 500 nm and 800
nm.

Next, details of the protective film and the like will be described.

As shown in the cross-sectional view of the semiconductor device in FIG. 10, after forming MOS type transistors and electrodes 61a and 61b of aluminum or copper, a silicon oxide insulating film (PSG) 63 containing phosphorus and almost phosphorus -Free silicon oxide interlayer insulating films (NSG) 60, 65
And a surface protection film (passivation film) 66 made of a silicon nitride film or a silicon nitride film containing oxygen (see, for example, Japanese Patent Application Laid-Open No. 1-12).
5939), thereby protecting the MOS transistor, the wiring portion, and the like in the semiconductor device 67 from the subsequent mounting and the mechanical damage in the latter half of the process.

[0008]

However, conventionally, a plasma CVD (Chemical vapor) has been used as a passivation film.
silicon nitride surface protection film (P
-SiN film) 66 is mainly used, but hydrogen contained in the surface protective film (P-SiN film) is trapped at the interface between the semiconductor substrate 56 and a silicon oxide film such as an interlayer insulating film, and is hot. You will be tied to the carrier. As a result, interface states and interface charges are formed, causing the MOS transistor to change with time, and further changing the operation threshold voltage (Vth) of the MOS transistor, thereby making the operation of the semiconductor device unstable. It is thought to cause.

Accordingly, an object of the present invention is to provide a semiconductor device which forms a protective film having a good surface protective action without using a surface protective film formed by plasma CVD such as P-SiN, and a method of manufacturing the same. Is to do.

[0010]

That is, the present invention provides a semiconductor device having a surface protective film on a semiconductor substrate, wherein at least the surface area of the surface protective film is modified by ion implantation, and a method of manufacturing the same. Pertains to the method.

According to the present invention, since at least the surface area of the surface protective film is modified by ion implantation, the surface protective film (passivation film) of the semiconductor device can be formed without using a conventional plasma process. The semiconductor device can be manufactured in a simplified process while stabilizing the performance of the semiconductor device.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, in an apparatus and a manufacturing method according to an embodiment of the present invention, ion implantation is performed by plasma immersion ion implantation (PIII), and at least the surface area of the surface protective film is made of carbon. It is preferable that the surface protective film is modified by implantation of ions and / or nitrogen ions, and the surface protective film is a passivation film made of phosphor silicate glass.

Further, an interlayer insulating film may be provided below the surface protective film, and the interlayer insulating film may be modified as needed. Further, at least a negative pulse voltage is applied to the semiconductor substrate to perform the ion implantation, and a cathodic arc device, a Kauffman-type ion source, an RF plasma ion source, or the like is used alone as an ion generation source for the ion implantation.
Alternatively, it is preferable to use them in combination.

Next, preferred embodiments of the present invention will be specifically described with reference to the drawings.

First, as a manufacturing method, FIG. 2 shows a configuration example of the plasma immersion ion implantation apparatus 26 according to the first embodiment. This plasma immersion ion implantation (PIII) device 26 is a sample (semiconductor device) 5
And implants plasma ions generated by another device under pulse application.

The plasma immersion ion implanter 26 includes a high vacuum chamber 1, a vacuum exhaust system 6 for exhausting the inside of the high vacuum chamber 1, and a water-cooled substrate holder 2 for supporting the sample 5 inside the high vacuum chamber 1.
And an ion generator (cathodic arc device) 3 for supplying ions 37 to be injected into the sample 5, and a high-frequency pulse power supply 4 for applying a pulsed voltage including a positive pulse voltage and a negative pulse voltage to the sample 5 Consists of

The high vacuum chamber 1 is a container whose interior is evacuated to a high vacuum state. Next, the vacuum exhaust system 6 is a vacuum pump for exhausting the inside of the high vacuum chamber 1 to obtain a high vacuum state. The plasma immersion ion implantation apparatus 26 evacuates the inside of the high vacuum chamber 1 by the vacuum exhaust system 6 and sets the degree of vacuum before introducing ions into the inside of the high vacuum chamber 1, that is, the background degree of vacuum, for example, 10 ^−. Set to about ⁷ Torr.

Next, the water-cooled substrate holder 2 supports the sample 5 and is supported inside the high vacuum chamber 1. Then, when performing surface modification on the sample 5, the sample 5 is attached to the water-cooled substrate holder 2.

Now, a cooling water introduction pipe is incorporated in the water-cooled substrate holder 2, and the cooling water is caused to flow through this pipe, so that the sample 5 attached to the water-cooled substrate holder 2 is removed.
To cool. Here, the cooling water introduction pipe incorporated in the water-cooled substrate holder 2 is led out of the high vacuum chamber 1. Then, cooling water is supplied to a cooling water introduction pipe incorporated in the water-cooled substrate holder 2 via a cooling water introduction pipe led out of the high vacuum chamber 1.

When the ion implantation is performed, the temperature of the sample 5 increases with the ion implantation. However, since the sample 5 is a semiconductor device and processing at a high temperature is not preferable, if the temperature of the sample 5 rises during ion implantation, there is a problem in quality and the like.

However, the plasma immersion ion implantation apparatus 26 of the first embodiment uses the water-cooled substrate holder 2 having a water-cooling function to perform surface modification on the sample 5 by ion implantation. The temperature of the sample 5 can be controlled. Therefore, when the sample 5 is a semiconductor device,
When the treatment at a high temperature is not preferable, the ion implantation into the sample 5 can be performed while suppressing the temperature rise of the sample 5.

The ion generating device (cathodic arc device) 3 is a plasma generating means for supplying ions 37 to be injected into the sample 5 and generating plasma containing ions to be injected into the sample 5.

That is, the sample (semiconductor device) 5 is mounted on the water-cooled substrate holder 2 as shown in FIG. next,
A high purity amorphous carbon plate as a solid source is mounted on the cathode 13 of the cathodic arc device 3.

Then, the inside of the high vacuum chamber 1 is maintained at a high vacuum of the order of 10 −7 by the vacuum exhaust system 6. Further, the cathode 13 made of the amorphous carbon plate inside the cathodic arc device 3
Then, an arc discharge is caused to ionize the carbon atoms. Since the high-purity solid source is ionized in the high vacuum chamber 1 by arc discharge, contamination of impurities such as hydrogen can be drastically reduced.

The arc current and arc voltage during arc discharge were 60 A and 25 V, respectively. And
The carbon ions and the like diffuse and irradiate a region including the sample (semiconductor device) 5 in a plasma state. Then, a pulse voltage is applied to the sample (semiconductor device) 5 from the high-frequency pulse power supply 4 through the water-cooled substrate holder 2.

With this pulse voltage waveform, positive carbon ions 37 are implanted into the silicon oxide insulating film 20 for protecting the semiconductor substrate 16 as shown in FIGS. Then, after the protective film is formed, the surface is modified by ions to form a surface modified layer 33 of 100 to 1000 degrees. Finally, an annealing heat treatment is performed as a post-treatment.

Next, a plasma immersion ion implantation apparatus 36 according to a second embodiment shown in FIG. 3 includes a high vacuum chamber 101, a vacuum exhaust system 106 for exhausting the inside of the high vacuum chamber 101, and a high vacuum Chamber 10
1, a water-cooled substrate holder 102 that supports the sample 105, an ion generator (Kauffman-type ion source) 27 that supplies ions 110 to be injected into the sample 105, and a positive pulse voltage and a negative pulse voltage. And a high-frequency pulse power supply 104 for applying a pulsed voltage to the sample 105.

The high vacuum chamber 101 is a container that is evacuated to a high vacuum state. The evacuation system 106 is a vacuum pump for evacuating the inside of the high vacuum chamber 101 to obtain a high vacuum state.
In the plasma immersion ion implantation apparatus 36, the inside of the high vacuum chamber 101 is evacuated by the vacuum evacuation system 106, and the degree of vacuum before introducing ions into the inside of the high vacuum chamber 101, that is, the background degree of vacuum is, for example, 10 ^−7.
Torr.

Next, the water-cooled substrate holder 102 supports the sample 105 and is a high vacuum chamber 101.
Supported inside. Then, when the surface modification is performed on the sample 105, the sample 105 is attached to the water-cooled substrate holder 102.

A cooling water introduction pipe is incorporated in the water-cooled substrate holder 102, and cooling water flows through the pipe to cool the sample 105 attached to the water-cooled substrate holder 102. Here, the water-cooled substrate holder 10
The cooling water introduction pipe incorporated in 2 is led out of the high vacuum chamber 101. Then, the cooling water can be supplied to the water-cooled substrate holder 102 via a cooling water introducing pipe led out of the high vacuum chamber 101.

When the ion implantation is performed, the temperature of the sample 105 increases with the ion implantation. However, since the sample 105 is a semiconductor device and treatment at a high temperature is not preferable, if the temperature of the sample 105 rises during ion implantation, there is a problem in quality and the like.

However, the plasma immersion ion implanter 36 has a water-cooled substrate holder 102 having a water-cooled function.
Can be used to control the temperature of the sample 105 when performing surface modification on the sample 105 by implanting ions 110. Therefore, when processing at a high temperature is not preferable, as in the case of a semiconductor device, the sample 1
The ion implantation into the sample 105 can be performed while suppressing the temperature rise of the sample 105.

The Kaufman-type ion source 27 used at this time is an apparatus using an ion gun combining a hot cathode 29 and a magnetron discharge.
The ion 110 generated by the hot cathode 29, the operating gas, and the coil 30 is converted into a beam and sent into the high vacuum chamber 101 through the grid 31. In this Kaufman-type ion source, the operating gas serving as the ion source To generate ions from the working gas.

That is, the surface is modified by ion implantation using a gas source as an ion source by using a Kauffman-type ion source or an RF plasma source or the like. In addition, as a gaseous source, CO, CO ₂ , N ₂ , ammonia, gaseous paraffin hydrocarbons such as methane and ethane, vaporized methanol and ethanol, etc., form carbon ions and nitrogen ions, Perform ion implantation.

At this time, the shape of the grid 31, which is an outlet of the ion beam 110, is modified (for example, see Japanese Unexamined Patent Application Publication No.
349428), or by ionizing these gases at an appropriate high frequency to select an ion species (for example, JP-A-6-275223) and implant a desired ion species.
Further, by using the cathodic arc device 3 and the Kauffman-type ion source 27 in combination, irradiation of carbon ions and nitrogen ions is performed, and the waveform of the pulse voltage is further optimized to form a passivation layer of the semiconductor device. .

Further, the cathodic arc device 3 will be described in detail.

As shown in FIG. 2, a deflection coil 14 for efficiently guiding ions 37 generated from the cathode 13 to the anode 12 is provided outside the discharge cathode 13 to which a driving voltage is supplied from the trigger power supply 15. Then, the electromagnetic coil 11 disposed in front of the anode 12 functions as an electromagnetic induction system for guiding the charged ions 37 to the sample 5. The water-cooled substrate holder 2 and the high-frequency pulse power supply 4 have a function of a bias unit described later, and the power supply 9 is a power supply for applying a drive voltage to the electromagnetic coil 11 and constitutes a low-voltage circuit.

In this case, the ion current is 1 to 100 mA, and the ion acceleration voltage is about 0 to 1000 V. And
As a means for biasing the substrate, as shown in FIG. 2, a sample 5 to be processed is attached to a water-cooled substrate holder 2,
From the high-frequency pulse power supply 4, a direct current and an alternating current, an alternating current in which a direct current is superimposed, a pulse voltage in which a direct current is superimposed, and a pulse voltage in which a direct current is superimposed are applied.

It should be noted that ions are generated in the source of the cathodic arc device 3 without using an operating gas.
Specifically, the source of the cathodic arc device 3 is
An arc discharge is generated using the cathode 13 serving as an ion source, whereby the cathode 13 evaporates and ionized particles are emitted. Since the source of the cathodic arc device 3 does not use a working gas for generating ions,
Ions can be generated while maintaining a high vacuum state.

If the source of the cathodic arc device 3 is used as an ion generating source, the cathode 13 melts and droplets are generated. In order to solve the problem of droplet generation,
There is one that removes droplets using an electromagnetic filter, and this cathodic arc source is called a filtered cathodic arc source. In the plasma immersion ion implanter 26, the filtered cathodic arc source may be used as an ion source.

This is achieved by arc discharge from a high-purity solid ion source, that is, without using an ion source such as a rare gas, as compared with an electromagnet mass separation type ion implantation apparatus used in a conventional semiconductor device manufacturing process. Since carbon is ionized, mass separation is not required, and the amount of ion current can be increased by two digits or more. Further, the structure of the device can be further simplified. Therefore, the surface treatment can be performed at a high speed, and the process cost can be suppressed.

Next, for example, in the plasma immersion ion implantation apparatus 26 of the first embodiment shown in FIG.
In the state where the sample (semiconductor device) 5 is arranged in the ions to be implanted, a pulse-like voltage including a positive pulse voltage and a negative pulse voltage is generated by the high-frequency pulse power supply 4, and this pulse-like voltage is generated. A bias voltage is applied to the sample 5. Thus, the ions 37 are drawn into the sample 5, and the ions are implanted into the sample 5.

More specifically, when a negative pulse voltage is applied to the sample 5, positive ions are drawn into the sample 5, and the positive ions are injected into the sample 5.

Here, the amount of ion implantation into the sample 5, the depth of the implantation, and the like are determined based on the pulse peak value, pulse rise time, pulse interval, pulse width, process pulse, and the like of the negative pulse voltage applied to the sample 5. It is considered to depend on time. Accordingly, by controlling the waveform of the pulse-like voltage applied to the sample 5, it is possible to control the amount and depth of the ion implantation into the sample 5. The pulse voltage used in this case was ± 10 kV, the pulse width was 10 microseconds, and the rise of the pulse was 1 microsecond.

As described above, when the positive ions are drawn into the sample 5 and the ions are implanted into the sample 5, charges are accumulated in the sample 5. Therefore, if a negative voltage is continuously applied to the sample 5, the ion implantation into the sample 5 cannot be continued. Therefore, in the plasma immersion ion implanter 26, the charge accumulated in the sample 5 is converted into a positive pulse by setting the bias voltage applied to the sample 5 to a pulse-like voltage including a positive pulse voltage and a negative pulse voltage. Neutralize with voltage.

That is, when a positive pulse voltage is applied to the sample 5, electrons are drawn into the sample 5, and the charges accumulated in the sample 5 are neutralized by the electrons. When the charges accumulated in the sample 5 are neutralized in this way, when a negative pulse voltage is subsequently applied, positive ions are drawn into the sample 5 again, and
Is implanted.

As described above, when the bias voltage applied to the sample 5 is a pulse-like voltage including a positive pulse voltage and a negative pulse voltage, the sample 5 does not enter the charge-up state, but Ion implantation can be performed.

In the case of the conventional ion implantation method, since an ion beam having a constant energy is accelerated and implanted into a sample, its ion implantation profile (depth from the surface of the sample and that injected into the object to be processed) are obtained. The relationship with the ion density) has a Gaussian-type distribution having a peak at a certain depth from the surface, as shown by the broken line graph in FIG. That is, in the conventional ion implantation method using a constant applied voltage, a Gaussian function type implantation profile having a peak at a certain depth (a broken line in FIG. 7) is shown because the energy of the implanted ions is constant. In the case of ion implantation using a pulse voltage, the energy distribution of the implanted ions expands from 0 to the maximum applied voltage, so that the distribution of the implanted ions in the depth direction is represented by a solid line in FIG. As described above, the surface is more uniformly distributed to a certain depth direction, and the effect of the surface modification appears more.

When a pulse voltage is used at the time of ion implantation, charge-up of the semiconductor surface is alleviated in a time period when no voltage is applied, so that a controlled and desired amount of ions can be implanted. At the same time, damage to the semiconductor device due to a local electrostatic field can be avoided.

Similarly, when ions are implanted by the plasma immersion ion implanter 26, the pulse voltage applied to the sample 5 is controlled.
The implantation amount and implantation depth of ions to be implanted into the substrate are controlled. Accordingly, the implantation profile can have the same ion density up to a certain depth near the surface, as shown by the solid line graph in FIG.

Next, the pulse-like voltage applied to the sample 5 when performing ion implantation with the plasma immersion ion implantation apparatus 26 shown in FIG. 2 will be described with some examples.

In the example shown in FIG. 4, first, a negative pulse voltage of 10 kV is applied for 10 microseconds, and immediately thereafter, a positive pulse voltage of 10 kV having almost the same absolute value of the pulse peak is applied for 10 microseconds. Thereafter, a period during which no voltage is applied is provided. Then, this pulse train is repeatedly applied to the sample 5.

When the pulse voltage has the waveform shown in FIG. 4, when a negative pulse voltage is applied, positive ions are accelerated and drawn into the sample 5. Thus, ion implantation into the sample 5 is performed. At this time, positive ions are drawn into the sample 5 and charge is accumulated in the sample 5.
On the other hand, when a positive pulse voltage is applied, electrons
Drawn into. Thus, the charges accumulated in the sample 5 are neutralized.

Therefore, when the pulse-like voltage having the waveform shown in FIG. 4 is applied to the sample 5 as a bias voltage, the ion implantation into the sample 5 can be continued without the sample 5 being in a charge-up state.

Next, in the example shown in FIG. 5, a negative pulse voltage of 10 kV is applied for 10 microseconds, a period during which no voltage is applied is provided, and the negative pulse voltage of 10 kV and the absolute value of the pulse peak are further set. A positive pulse voltage of 10 kV having approximately the same value is applied for 10 microseconds, and thereafter, a period in which no voltage is applied is provided.

Then, this pulse train is repeatedly applied to the sample 5.

Even when the pulse voltage is changed to the waveform shown in FIG. 5, when a negative pulse voltage is applied, positive ions are accelerated and drawn into the sample 5 as in FIG. Thus, ion implantation into the sample 5 is performed. At this time,
Positive ions are attracted to the sample 5 and charge is accumulated on the sample 5. On the other hand, when a positive pulse voltage is applied, electrons are drawn into the sample 5. Thus, the charges accumulated in the sample 5 are neutralized.

Therefore, when the pulse-like voltage having the waveform shown in FIG.
Similarly to the above, the ion implantation into the sample 5 can be continued without the sample 5 being in the charge-up state.

Further, in FIG. 5, after applying the negative pulse voltage, a period in which the voltage is not applied is provided, and after a certain period of time, the positive pulse voltage is applied. If a period in which no voltage is applied is provided after the application of the negative pulse voltage, the charges accumulated in the sample 5 during that period are:
It is thought to be out to some extent. Therefore, charge is easily neutralized by applying a positive pulse voltage.

In FIG. 6, a negative pulse voltage of 10 kV is set to 1
A period in which no voltage is applied is provided immediately after application of 0 microsecond. Then, a negative pulse voltage of 10 kV is applied for 10 microseconds. This pulse train is repeatedly applied to the sample 5.

When the pulse-like voltage has the waveform shown in FIG. 6, when a negative pulse voltage is applied, positive ions are accelerated and drawn into the sample 5. Thus, ion implantation into the sample 5 is performed. At this time, positive ions are drawn into the sample 5 and the sample 5 is charged.

After applying the negative pulse voltage, a period in which no voltage is applied is provided, and after a certain period of time, the negative pulse voltage is applied again. This is because, if a period in which no voltage is applied after the application of the negative pulse voltage is provided, it is considered that charges accumulated in the sample 5 are drained to some extent during that period.

Therefore, when the pulse-like voltage having the waveform shown in FIG. 6 is applied to the sample 5 as a bias voltage, the ion implantation into the sample 5 can be continued without the sample 5 being in a charge-up state.

The hardness of the sample obtained from the above embodiment was measured with a thin film hardness meter (MHA400 manufactured by NEC). From the measurement results and the simulation by the finite element method, the surface was hardened from 5 GPa to 15 GPa.
Further, when the injection profile shown by the solid line in FIG. 6 was compared between the surface portion and the side portion of Sample 5, they were almost the same. Therefore, it is considered that this ion implantation method is effective even for the surface modification of the passivation film surface of a semiconductor device having severe irregularities due to the shape of a workpiece inside the semiconductor device.

Further, the following can be considered. First,
Unlike a conventional ion implantation apparatus, a mass separation mechanism is not required, so that surface modification can be performed at high speed. In addition, even on a highly uneven surface, uniform surface modification can be performed without rotating the sample or moving the ion beam during the surface treatment. It suppresses charge-up during ion implantation and prevents damage to the semiconductor device due to a local high electric field. Further, regardless of whether the ion source is solid or gas, the surface modification can be performed by implanting desired ions by using or combining a cathodic arc device, a Kauffman-type ion source, or an RF-type plasma source.

Next, a cross-sectional view of a semiconductor device, which is an example of a sample after ion implantation, is shown in FIG. Semiconductor substrate 1
6, a MOS device including the source and drain regions 17a and 17b, the gate insulating film 24, and the gate electrode 18, a source electrode 21a, a drain electrode 21b, and the like form a semiconductor device. Insulating films 20 and 23 of a silicon oxide film are formed between these electrodes. The respective film thicknesses are 500 nm and 800 nm
Met.

After the formation of the insulating film (PSG) 23, further ion implantation is performed to form a surface modification layer 33 of 100 to 1000 ° (for example, SiC if the ions are C ^+).
Is formed.

Next, FIG. 9 shows a cross-sectional view of a semiconductor device as another sample. Semiconductor substrate 116, source and drain regions 117a and 117b, gate insulating film 12
4. a MOS transistor including a gate electrode 118;
A semiconductor device is formed by the source electrode 121a, the drain electrode 121b, and the like. Between these electrodes, an interlayer insulating film (NSG) 120 and insulating films (PSG) 123 and 138 are formed by a silicon oxide film. The interlayer insulating film (NSG) 120 and the insulating film (PSG) 1
23 are 500 nm and 800 n, respectively.
m.

Then, after the insulating film (PSG) 138 is formed as a protective film, ion implantation is performed for 100 ° to 100 ° C.
1000 ° surface modification layer 133 (for example, if the ions are C ⁺
Then, SiC) is provided.

This is applicable to a semiconductor device having a multilayer wiring structure as shown in FIG. Note that ions may be implanted into an arbitrary layer in the step of forming a multilayer. Further, it is considered that ions may be directly implanted into the insulating film (PSG) as the passivation film, and it is considered that it is not always necessary to implant ions into the surface protective film (P-SiN).

It should be noted that the present invention does not depart from the gist thereof,
The above embodiment can be variously modified.

For example, the ion species to be implanted may be changed, the material of the insulating film to be implanted, the method of generating the implanted ions, and the like may be variously changed.

[0073]

According to the present invention, since at least the surface area of the surface protective film is modified by ion implantation, the surface protective film (passivation film) of the semiconductor device is not formed by the conventional plasma process. The semiconductor device can be manufactured in a simplified process while stabilizing the performance of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of a plasma immersion ion implantation device using a cathodic arc device.

FIG. 3 is a diagram showing a configuration example of a plasma immersion ion implantation apparatus using a Kauffman-type ion source.

FIG. 4 is a diagram illustrating an example of a waveform of a pulsed voltage applied to the semiconductor device when the surface of the semiconductor device is modified.

FIG. 5 is a diagram showing another example of the waveform of the pulsed voltage applied to the semiconductor device when the surface of the semiconductor device is modified.

FIG. 6 is a diagram showing still another example of the waveform of the pulse voltage applied to the semiconductor device when the surface of the semiconductor device is modified.

FIG. 7 is a correlation diagram between the density of implanted atoms and the depth of a sample during ion implantation into a semiconductor.

FIG. 8A is a cross-sectional view of the surface protective film before ion implantation, and FIG. 8B is a cross-sectional view of the surface protective film after ion implantation.

FIG. 9 is a partial cross-sectional view of a semiconductor device according to another embodiment of the present invention.

FIG. 10 is a partial cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

1, 101: high vacuum chamber, 2, 102: water-cooled substrate holder, 3: cathodic arc device, 4, 10
4: High frequency pulse power supply, 5, 105: Sample (semiconductor device), 6, 106: Vacuum exhaust system, 9: Power supply, 11: Electromagnetic coil, 12: Anode, 13: Cathode, 14: Deflection coil, 15: Trigger power supply , 16, 56, 116 ...
Semiconductor substrates (for example, silicon substrates), 17a, 57a,
117a: source region, 17b, 57b, 117b: drain region, 18, 58, 118: gate electrode, 20,
60, 120... Insulating film (NSG), 21a, 61a, 1
21a ... source electrode, 21b, 61b, 121b ... drain electrode, 22, 62, 122 ... gate electrode, 23, 6
3, 123 ... insulating film (PSG), 24, 64, 124 ...
Gate insulating film, 25, 67, 125: semiconductor device (insulated gate field effect transistor), for example, MOS transistor, 26, 36: plasma immersion implanter, 27: Kauffman ion source, 28: magnetron anode, 29: heat Cathode, 30 ... coil, 31 ... grid,
33, 133: surface modification layer, 37, 110: ion beam, 65: interlayer insulating film (NSG), 66: surface protective film (P-SiN), 138: insulating film (PSG)

Claims (12)

[Claims] 1. A semiconductor device having a surface protective film on a semiconductor substrate, wherein at least a surface area of the surface protective film is modified by ion implantation. 2. The semiconductor device according to claim 1, wherein said ion implantation is performed by plasma immersion ion implantation. 3. At least a surface area of the surface protective film,
The semiconductor device according to claim 1, wherein the semiconductor device is modified by implanting carbon ions and / or nitrogen ions. 4. The semiconductor device according to claim 3, wherein said surface protection film is a passivation film made of a silicon oxide insulating film. 5. An interlayer insulating film under the surface protective film,
The semiconductor device according to claim 1, wherein the modification is added to the interlayer insulating film as needed. 6. A method for manufacturing a semiconductor device, comprising: a step of forming a surface protective film on a semiconductor substrate; and a step of implanting ions into at least a surface region of the surface protective film. 7. The method according to claim 6, wherein said ion implantation is performed by plasma immersion ion implantation. 8. The method according to claim 1, wherein at least a surface area of the surface protective film is
The method for manufacturing a semiconductor device according to claim 3, wherein the modification is performed by implanting carbon ions and / or nitrogen ions. 9. The method according to claim 4, wherein the surface protection film is a passivation film made of a silicon oxide insulating film. 10. An interlayer insulating film under the surface protective film, wherein the interlayer insulating film is modified as required.
A method for manufacturing a semiconductor device according to claim 5. 11. The method of manufacturing a semiconductor device according to claim 7, wherein said ion implantation is performed by applying at least a negative pulse voltage to said semiconductor substrate. 12. The method of manufacturing a semiconductor device according to claim 6, wherein a cathodic arc device, a Kauffman-type ion source, or an RF plasma ion source is used alone or in combination as an ion source for the ion implantation.