JP2001266586A - Read only semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the circuit scale of a read only semiconductor memory without using dummy cells. SOLUTION: This device is provided with a memory cell 1 storing information, a bit line 5 by which voltage is transferred in accordance with the storage information of a memory cell 1, a pre-charge circuit 3 for pre-charging the bit line 5, and a sense amplifier circuit 41 for deciding the storage information on the memory cell 1 by comparing the voltage VBIT of the bit line 5 with reference voltage VREF generated from the pre-charge circuit 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor read-only memory, and more particularly to a technique for reducing a chip size.

[0002]

2. Description of the Related Art Semiconductor read only memory (hereinafter referred to as RO)
M) is a memory cell 1 for storing information and a bit line converted to a voltage by detecting a current flowing through a bit line 5 in accordance with information stored in the memory cell 1 as shown in the block diagram of FIG. By comparing the voltage with the reference voltage VREF, a sense amplifier circuit 4 that determines the storage information of the memory cell 1 and a dummy cell 2 that detects the current flowing through the reference line 6 and generates the reference voltage VREF
And a precharge circuit 3 for precharging the bit line 5 and the reference line 6. In the ROM shown in FIG. 4, if the bit line voltage is higher than the reference voltage VREF, the stored information is determined to be "1", and if the bit line voltage is lower than the reference voltage VREF, it is determined to be "0".
FIG. 5 is a circuit diagram more specifically showing the block diagram of FIG. The precharge circuit 3 includes an N-channel transistor Q1 and a NOR gate NOR2. The drain, gate and source of the N-channel transistor Q1 are a power supply (Vcc) and a NOR gate NOR, respectively.
2 and to the node N1. One input of the NOR gate NOR2 has a chip enable bar signal C
EB (when selected: "L" level, when not selected: "H" level) is applied, and the other input is connected to node N1. The drains of N-channel transistors Q2 and Q3 are connected to node N1. The precharge signal PR is input to the gates of the N-channel transistors Q2 and Q3. The bit line 5 and the reference line 6 are connected to the sources of the N-channel transistors Q2 and Q3, respectively. Bit line 5 is connected to memory cell 1, and reference line 6 is connected to dummy cell 2.

Referring to FIG. 5, the principle of charging the node N1 to a predetermined precharge voltage by the precharge circuit 3 will be described. The precharge voltage generated by this circuit is determined by adjusting the inversion voltage of the NOR gate NOR2.

First, when the node N1 is at "L" level, a read operation is started. When the signal CEB is at "L" level, the output of the NOR gate NOR2 is at "H" level, so that the N-channel transistor Q1 is turned on. I do.
Then, node N1 is charged to a voltage lower than the gate voltage of N-channel transistor Q1 by a threshold voltage. However, the voltage of this node N1 becomes NOR gate NOR.
When the inverted voltage exceeds 2, the output of the NOR gate NOR2 becomes "L" level, so that the N-channel transistor Q1 is turned off and the charging of the node N1 is stopped. Conversely, when the voltage at the node N1 falls below the inverted voltage of the NOR gate NOR2, the output of the NOR gate NOR2 goes to "H" level, so that the N-channel transistor Q1 turns on and the node N1 is charged.

In this way, the precharge voltage of the node N1 is stabilized near the inverted voltage of the NOR gate NOR2. Normally, the precharge voltage of the node N1 is set to about half of the power supply voltage. For example, if the power supply voltage is 3.3 V, the precharge voltage of the node N1 is 1.65 V.

Next, a read operation from a memory cell will be described.

Since the precharge signal PR is at "H" level for a while after the start of the read operation, the N-channel transistors Q2 and Q3 are on, and the levels of the bit line voltage VBIT and the reference voltage VREF are both at the node N1. Is the same voltage (1.65 V) as the precharge voltage.

Thereafter, precharge signal PR attains "L" level, and N-channel transistors Q2 and Q3
Is turned off. Here, when a memory cell and a dummy cell are selected for a word line and a column, the bit line voltage VBIT approaches a different voltage according to information stored in the memory cell. This bit line voltage VBIT is a voltage determined by the ratio between the ON resistance of the memory cell and the resistance R1.
For example, when the storage information of the memory cell is “0”,
As the voltage approaches 1.45V, the stored information of the memory cell becomes "
In the case of “1”, the voltage remains at 1.65 V. On the other hand, the reference voltage VREF is the ON resistance of the dummy cell and the resistance R.
It approaches the voltage determined by the ratio of 2. For example, this voltage is 1.55V.

When the precharge signal PR is at "L" level and the N-channel transistors Q2 and Q3 are off, the resistors R1 and R2 compensate for the potential drop of the bit line 5 and the reference line 6 caused by leakage, and sense The resistors R1 and R1
The resistance value of 2 is set to a value sufficiently larger than the on-resistance values of the memory cell and the dummy cell.

Then, by comparing the bit line voltage VBIT with the reference voltage VREF by the sense amplifier circuit 4, information stored in the memory cell 1 is output from the sense amplifier circuit 4.

FIG. 6 shows a configuration of a normal sense amplifier circuit. Bit line voltage VBIT and reference voltage VREF are input to the gates of P-channel transistors Q4 and Q5, respectively. The sources of P-channel transistors Q4 and Q5 are connected, and are connected to power supply Vcc via resistor R. P-channel transistor Q
The drains of 4 and Q5 are connected to the drains of N-channel transistors Q6 and Q7, respectively. The sources of N-channel transistors Q6 and Q7 are both grounded. The drain of the N-channel transistor Q6,
The gate and the gate of the N-channel transistor Q7 are connected, and the drain of the N-channel transistor Q7 becomes the output SAOUT of the sense amplifier circuit 4. In order to accurately compare the bit line voltage VBIT and the reference voltage VREF, the shapes of the P-channel transistors Q4 and Q5 must be equal. With such a normal sense amplifier circuit, the information stored in the memory cell
1 "and the bit line voltage VBIT is the reference voltage V
If it is higher than REF, the sense amplifier output SAOU
T becomes “H” level, and the storage information of the memory cell becomes “H”.
0 "and the bit line voltage VBIT is the reference voltage V
If it is lower than REF, the sense amplifier output SAOU
T becomes "L" level.

[0012]

The above-mentioned conventional ROM
Thus, a dummy cell for generating the reference voltage VREF was required. Such a dummy cell has a layout similar to that of a memory cell.
On-cells and off-cells are mixed in the same row of dummy cells in order to form the same structure as the memory cells and generate the reference voltage VREF. Furthermore, in order to realize a state in which wraparound to adjacent cells is considered,
The dummy cell has a plurality of memory cell transistors (for example, 16 columns) per row, and has the same number of rows as the memory cells.

As described above, the conventional dummy cell has a considerably large circuit scale.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the conventional semiconductor read-only memory, and has as its object to reduce the circuit scale of the semiconductor read-only memory by not using a dummy cell. Is what you do.

[0015]

A semiconductor read-only memory according to the present invention comprises a memory cell for storing information, a bit line to which a voltage is transferred in accordance with information stored in the memory cell, and a precharge for the bit line. And a sense amplifier circuit for comparing the voltage of the bit line with a reference voltage generated from the precharge circuit to determine the storage information of the memory cell.

During the precharge period, an output from the precharge circuit is supplied to the bit line, and after the precharge period ends, the supply from the precharge circuit to the bit line is cut off. Is converted to a voltage and transferred to the bit line, and the voltage transferred to the bit line in the sense amplifier circuit is compared with a reference voltage generated from the precharge circuit, and the storage information of the memory cell is Output.

In the sense amplifier circuit, the bit line voltage is applied to a first differential input P-channel transistor, and the reference voltage generated from the precharge circuit is applied to a second differential input P-channel transistor. Wherein the conductance of the first differential input P-channel transistor is smaller than that of the second differential input P-channel transistor.

In the sense amplifier circuit, the bit line voltage is applied to a first differential input N-channel transistor, and the reference voltage generated from the precharge circuit is applied to a second differential input N-channel transistor. Wherein the conductance of the first differential input N-channel transistor is greater than that of the second differential input N-channel transistor.

According to the semiconductor read-only memory of the present invention, the precharge voltage output from the precharge circuit is used as a reference voltage in the sense amplifier circuit, which is necessary in the conventional circuit configuration. This eliminates the need for dummy cells.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments of the present invention.

FIG. 1 is a block diagram showing a read circuit of a semiconductor read-only memory according to the present invention. A memory cell 1 for storing information, and a current flowing through a bit line 5 is detected according to the storage information of the memory cell 1, and the bit line voltage VBIT converted into a voltage is compared with a reference voltage VREF to store the data in the memory cell 1. A sense amplifier circuit 41 for determining information and a precharge circuit 3 for precharging the bit line 5 and the reference line 6 are provided. Compared with the conventional circuit of FIG. 4, the dummy cell 2 is eliminated and the circuit scale is reduced. In FIG. 1, blocks with the same reference numerals as those in FIG. 4 are the same. However, the reference voltage VREF is applied to the precharge circuit 3
Is the voltage generated from

Next, a preferred embodiment of the present invention will be described.
This will be described with reference to the drawings. FIG. 2 is a block diagram of one embodiment of the present invention, and is a circuit diagram more specifically showing the block diagram of FIG.

As in FIG. 5, the precharge circuit 3
It comprises a channel transistor Q1 and a NOR gate NOR2. The drain, gate and source of the N-channel transistor Q1 are connected to a power supply (Vc
c), the output of the NOR gate NOR2, and the node N1. One input of NOR gate NOR2 is supplied with chip enable bar signal CEB, and the other input is connected to node N1. The drains of N-channel transistors Q2 and Q3 are connected to node N1. The precharge signal PR is input to the gates of the N-channel transistors Q2 and Q3. The bit line 5 and the reference line 6 are connected to the sources of the N-channel transistors Q2 and Q3, respectively. Bit line 5
Is connected to the memory cell 1 and one input of the sense amplifier 41, and the reference line 6 is connected to the other input of the sense amplifier 41. Compared with the conventional circuit of FIG. 5, the dummy cell 2 is omitted.

The principle that the node N1 is charged to a constant precharge voltage by the precharge circuit 3 of FIG.
The description is omitted because it is the same as the conventional circuit of FIG. Assuming that the power supply voltage is 3.3V, the precharge voltage of node N1 is set to 1.65V.

Next, a read operation from a memory cell will be described.

Since the precharge signal PR is at "H" level for a while after the start of the read operation, the N-channel transistors Q2 and Q3 are on, and the bit line voltage VBIT and the reference voltage VREF are both at the node N1. Is the same voltage (1.65 V) as the precharge voltage. Thereafter, the precharge signal PR goes to "L" level, and the N-channel transistors Q2 and Q3 are turned off. Here, when a memory cell is selected for a word line and a column, the bit line voltage VBIT approaches a different voltage according to the storage information of the memory cell, as in the conventional circuit of FIG. This bit line voltage VBIT depends on the on-resistance of the memory cell and the resistance R.
It is a voltage determined by the ratio to 1. For example, when the storage information of the memory cell is “0”, the voltage approaches 1.45 V, and when the storage information of the memory cell is “1”, 1.6.
It remains at 5V. On the other hand, the reference voltage VREF remains at 1.65V. Then, the bit line voltage VBI
By comparing T with the reference voltage VREF by the sense amplifier circuit 41, information stored in the memory cell 1 is output from the sense amplifier circuit 41.

An embodiment (not shown) in which the gate of the N-channel transistor Q3 is always connected to the power supply (Vcc) is also conceivable.

FIG. 3 shows a configuration example of a sense amplifier circuit according to an embodiment of the present invention. Means such as constituent elements and wiring are substantially the same as those of the sense amplifier circuit used in the conventional circuit shown in FIG. The difference is that the P-channel transistors Q41 and Q51
Transistor size. By making the L / W (channel length / channel width ratio) of the P-channel transistor Q41 larger than that of the P-channel transistor Q51, the conductance is reduced, and the sense amplifier output is output at a predetermined voltage where the bit line voltage VBIT is lower than the reference voltage VREF. It is designed to be inverted. For example, when the bit line voltage VBIT is the reference voltage VRE
When the transistor sizes of the P-channel transistors Q41 and Q51 are set such that the output of the sense amplifier is inverted at a voltage of 1.55V that is 0.1V lower than F = 1.65V, when the storage information of the memory cell is "0", Is
Since the bit line voltage VBIT becomes 1.45 V, the sense amplifier output SAOUT becomes “L” level, and when the storage information of the memory cell is “1”, the bit line voltage VBI is set.
Since T remains at 1.65 V, the sense amplifier output S
AOUT becomes "H" level.

FIG. 7 shows another configuration example of the sense amplifier circuit according to one embodiment of the present invention. The difference from FIG. 3 is that the transistor polarity is inverted.

N-channel transistors Q11 and Q
The bit line voltage VBIT and the reference voltage VREF are input to the twelve gates, respectively. The sources of N-channel transistors Q11 and Q12 are connected,
It is grounded via a resistor R '. The drains of N-channel transistors Q11 and Q12 are connected to the drains of P-channel transistors Q13 and Q14, respectively. P-channel transistors Q13 and Q
14 are both connected to the power supply Vcc. The drain and gate of the P-channel transistor Q13 are connected to the gate of the P-channel transistor Q14, and the drain of the P-channel transistor Q14 becomes the output SAOUT of the sense amplifier circuit.

In this configuration, the L / W (channel length / channel width ratio) of the N-channel transistor Q11 is made smaller than that of the N-channel transistor Q12, so that the conductance of the N-channel transistor Q11 is reduced. Above that, the sense amplifier output is inverted at a predetermined voltage where the bit line voltage VBIT is lower than the reference voltage VREF. For example, the bit line voltage VBIT
Is 0.1 V from the reference voltage VREF = 1.65 V
N-channel transistors Q11 and Q12 so that the output of the sense amplifier is inverted at a voltage as low as 1.55V.
Is set, when the storage information of the memory cell is “0”, the bit line voltage VBIT becomes 1.
Since the voltage becomes 45 V, the sense amplifier output SAOUT becomes “L” level, and when the storage information of the memory cell is “1”, the bit line voltage VBIT remains at 1.65 V. H "level.

[0032]

As described above in detail, according to the present invention, the voltage generated from the conventional precharge circuit is used as the reference voltage of the sense amplifier circuit, and the input of the sense amplifier circuit is offset. This makes it possible to eliminate a dummy cell which has been used for generating a reference voltage and which requires a considerably large circuit scale, thereby reducing the chip area.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor read-only memory of the present invention.

FIG. 2 is a circuit diagram showing a configuration of one embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration example of a sense amplifier circuit used in an embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional semiconductor read-only memory.

FIG. 5 is a circuit diagram more specifically showing the block diagram of FIG. 4;

FIG. 6 is a circuit diagram showing a conventional sense amplifier circuit.

FIG. 7 is a circuit diagram showing another configuration example of the sense amplifier circuit used in the embodiment of the present invention;

[Explanation of symbols]

Reference Signs List 1 memory cell 3 precharge circuit 41 sense amplifier circuit 5 bit line 6 reference line Q1 N-channel transistor NOR2 NOR gate Q41, Q51 differential input P-channel transistor Q11, Q12 differential input N-channel transistor

Claims (5)

[Claims] 1. A memory cell for storing information, a bit line to which a voltage is transferred according to information stored in the memory cell, a precharge circuit for precharging the bit line, and a voltage of the bit line And a sense amplifier circuit for determining the storage information of the memory cell by comparing the reference voltage with a reference voltage generated from the precharge circuit. 2. The semiconductor read-only memory according to claim 1, wherein the drain of the N-channel transistor is
A gate and a source respectively connected to a power supply, an output of the NOR gate, and a first input of the NOR gate;
A semiconductor read-only memory, comprising: the precharge circuit to which a chip enable bar signal is supplied to a second input of the NOR gate. 3. The semiconductor read-only memory according to claim 1, wherein an output from said precharge circuit is supplied to said bit line during a precharge period, and said precharge circuit is provided after the end of said precharge period. The supply from the charge circuit to the bit line is cut off, the current flowing in the selected memory cell is converted to a voltage and transferred to the bit line, and in the sense amplifier circuit, the voltage transferred to the bit line is A semiconductor read-only memory which is compared with a reference voltage generated from a charge circuit and outputs information stored in the memory cell. 4. The semiconductor read-only memory according to claim 1, wherein the bit line voltage is applied to a first differential input P-channel transistor, and a reference generated from the precharge circuit. A voltage is applied to a second differential input P-channel transistor;
A semiconductor input-only memory comprising the sense amplifier circuit, wherein the conductance of the differential input P-channel transistor is smaller than that of the second differential input P-channel transistor. 5. The semiconductor read-only memory according to claim 1, wherein said bit line voltage is applied to a first differential input N-channel transistor, and a reference generated from said precharge circuit. A voltage is applied to a second differential input N-channel transistor;
A semiconductor input-only memory comprising the sense amplifier circuit having a conductance of a differential input N-channel transistor larger than that of the second differential input N-channel transistor.