JP2001266103A - Ic card and microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an IC card and a microcomputer, which reinforce security and speed up and reinforce a signal processing for security. SOLUTION: In an IC card, an operation voltage is supplied by the electrical connection of an outer terminal with a read/write device and the input/output operation of data with a ciphering processing and a decoding processing is performed. A dummy processing operation aiming at disturbance is included in the ciphering processing or the decoding processing and the operation timing and the operation current of an inner circuit are unified. In the microcomputer of module constitution, which includes the input/output operation of data with the ciphering processing or the decoding processing, the dummy processing operation aiming at disturbance is included in the ciphering processing or the decoding processing and the operation timing and the operation current of the inner circuit are unified.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC card and a microcomputer, and more particularly, to a CPU such as an IC card and a one-chip microcomputer with a program.
The present invention relates to a technology that is effective for use in confidentiality protection technology, although it performs data processing using an encryption key including a memory and a memory.

[0002]

2. Description of the Related Art In an IC card in which data is encrypted or decrypted using key information stored in a memory, an execution content and an encryption key are estimated using a difference in processing time. In order to counter hacking techniques such as the TA (Timing Attack) method, delay processing is performed during or before or after the execution of encryption or decryption processing to lose the temporal correlation with the contents of key information. Japanese Patent Application Laid-Open No. H10-69222 discloses an example of such a technique. Also, I
As for the C card, there is “IC card” written by Junichi Mizusawa, edited by Ohmsha Publishing Electronic Information Communication Society.

[0003]

In recent years, by observing and analyzing current consumption when an IC card is performing encryption processing, it is possible to easily estimate the contents of encryption processing and encryption keys. Has been suggested. For this,
John Wiley & sons W.Rankl & W. Effing's Smart C
ard Handbook '' 8.5.1.1 Passive protective mechan
It is described in isms (page 263).

That is, SPA (Simple Power Analysi)
In the s) method, the encryption key and the data being processed are analyzed based on the difference in the current consumption waveform caused by the difference in the operation instruction or the data being processed, and the DPA (Differ
In the entia1 Power Analysis method, a current consumption waveform is statistically processed to estimate an encryption key. In the DPA method, for example, an assumed encryption key is applied to a certain portion of DES, and a current consumption waveform is measured and statistically changed while changing plain text. This operation is repeated while changing the encryption key in various ways, and when the key is correct, the current waveform shows a large peak.

As described in the above publication, TA (Timing Att
ack) In the delay processing in which only the method is considered, even the correlation of the current consumption by the actual calculation cannot be lost, and the SPA or D of observing the current consumption waveform as described above is observed.
It cannot compete with hacking techniques such as the PA method. Therefore, the inventors of the present application disclose the above IC card and IC
For those that perform a certain data processing operation by a built-in program such as a microcomputer mounted on a module such as a card, etc., the contents of the encryption processing and the decryption of the encryption key by observing the above current consumption are improved We have developed security technology that can be reliably prevented.

An object of the present invention is to provide an IC card and a microcomputer that realize enhanced security. Another object of the present invention is to provide an IC card and a microcomputer which realize high-speed signal processing for security protection and its enhancement. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in an IC card to which an operating voltage is supplied by an external terminal being electrically connected to a read / write device and which includes an input / output operation of data accompanied by an encryption process or a decryption process, Alternatively, the decoding process includes a dummy processing operation for the purpose of disturbance similar to the original processing operation, so that the operation timing and the operation current of the internal circuit are made uniform.

[0008] The following is a brief description of the outline of another typical invention disclosed in the present application. That is, in a microcomputer having a module configuration including an input / output operation of data accompanied by an encryption process or a decryption process, the encryption process or the decryption process includes a dummy processing operation for the purpose of disturbance similar to the original processing operation. Instead, the operation timing and operation current of the internal circuit are made uniform.

[0009]

FIG. 1 is an external view of one embodiment of an IC card to which the present invention is applied. The IC card includes a card 101 made of a plastic case,
It has an IC card chip including a one-chip microcomputer (not shown) mounted inside the card 101. The IC card further has a plurality of contacts (electrodes) 102 connected to external terminals of the IC card chip. The plurality of contacts 102 include a power supply terminal VCC, a power supply reference potential terminal VSS, a reset input terminal RES bar, a clock terminal CLK, a data terminal I / O-1 / IRQ bar, I
/ O-2 / IRQ bar. The IC card receives power supply from an external coupling device such as a reader / writer (not shown) through the contact point 102, and performs data communication with the external coupling device.

FIG. 2 shows an IC card chip (microcomputer) mounted on the IC card according to the present invention.
1 is a schematic block diagram of one embodiment. Each circuit block in FIG. 1 is formed on a single semiconductor substrate such as single crystal silicon, though not particularly limited, by a known MOS integrated circuit manufacturing technique.

The structure of the IC card chip according to the present invention is basically the same as that of a microcomputer. The configuration includes a clock generation circuit 205, a central processing unit (hereinafter, sometimes simply referred to as a CPU) 201, an RO
M (Read Only Memory) 206 and RAM (Random Access M
emory) 207, a storage device such as a nonvolatile memory 208,
Coprocessor 20 for performing operations of encryption and decryption processing
9, an input / output port (I / O port) 202 and the like.

A clock generation circuit 205 receives an external clock CLK supplied from a reader / writer (external coupling device) (not shown) via the contact 102 in FIG. 1, and forms a system clock signal synchronized with the external clock signal. This is the circuit that supplies it inside the chip. CPU2
Reference numeral 01 denotes a device that performs a logical operation or an arithmetic operation, and controls a system control logic, a random number generator, a security logic, a timer, and the like. Storage device 20
6, 207 and 208 are devices for storing programs and data. The coprocessor 209 outputs R
It is composed of an arithmetic unit that performs a power-residue multiplication operation applicable to SA cryptography and the like, a register, and control logic. I /
The O (input / output) port 202 is a device that communicates with a reader / writer. Data bus 204 and address bus 203
Is a bus for interconnecting the devices.

Of the storage devices 206, 207, and 208, the ROM 206 is a memory whose storage contents are fixed in a nonvolatile manner, and is mainly a memory for storing programs. A volatile memory (hereinafter, referred to as a RAM) 207 is a memory in which stored information can be freely rewritten. However, when power supply is interrupted, stored contents are erased. When the IC card is removed from the reader / writer, the power supply is interrupted, so that the contents of the RAM 207 are not retained.

The nonvolatile memory (hereinafter referred to as an EEPROM)
(Electrical Erasable Programmable Read Only Memor
208) is a rewritable nonvolatile memory, and the information once written therein is retained therein even when the power supply is stopped. This E
EPROM 208 needs to be rewritten, and IC
Used to store data that should be retained even if the card is removed from the reader / writer. For example, in a case where an IC card is used as a prepaid card, the frequency of the prepaid card is rewritten each time the card is used. In this case, the frequency and the like need to be stored and held in the IC card even if the reader / writer is removed.
8 is held.

The CPU 201 has a configuration similar to a so-called microprocessor. That is, although not shown in detail, an instruction register therein, a micro instruction ROM for decoding an instruction written in the instruction register and forming various micro instructions or control signals, an arithmetic circuit, a general-purpose register (RG6, etc.) And an input / output circuit such as a bus driver and a bus receiver coupled to the internal bus BUS. The CPU 201 reads an instruction stored in the ROM 206 or the like, and performs an operation corresponding to the instruction.
The CPU 201 captures external data input through the I / O port 202, reads out data such as commands from the ROM 206 and fixed data necessary for executing the commands, and writes and reads data into and from the RAM 207 and the EEPROM 208. Operation control and the like are performed.

The CPU 201 includes a clock generation circuit 2
The system clock signal is generated from the system clock signal 05 and is operated with an operation timing and a period determined by the system clock signal. The main part of the CPU 201 is composed of a CMOS circuit including a P-channel MOSFET and an N-channel MOSFET. Although not particularly limited, the CPU 201 synchronizes a statically operated CMOS static circuit such as a CMOS static flip-flop, a precharge of a charge to a signal output node and a signal output to a signal output node with a system clock signal. And a CMOS dynamic circuit.

The security functions of the IC card include:
In addition to a random number generator that automatically generates random numbers inside the chip, a timer function that generates random interrupts, and the like, a high security function according to the present invention includes an RSA encryption used when data is transmitted and received between an IC card and an external device. A cryptographic processing operation unit (coprocessor) 209 for performing a modular exponentiation operation applicable to the law and the like is built in. The coprocessor 209 includes a dedicated register.

Security system for IC card
System, encryption of communication data is indispensable.
In the example, R is used as the public key
SA encryption is used. This encryption method uses encryption / decryption
Modular exponentiation X^YmodN is used.
Is the remainder by a long-known calculation algorithm.
Multiplication A^TwoDecompose into two forms, modN and ABmodN
be able to. That is, Y = e_ne_n-1... e₁The value of the
e_iE_nTo the lowest e₁One bit at a time until
Look, e_iA = 0^TwomodN only, e_i
A if = 1 ^TwoCalculate modN and ABmodN.
Therefore, e_iA when = 0^TwomodN operation
Thereafter, a process of determining whether i = 0 is performed, and e_i= 1
Sometimes A^TwoAfter the operation of modN and ABmodN, i
Since the determination process of whether = 0 is performed, e_i= 0
There are two types of current waveforms corresponding to and 1.
U.

As in this embodiment, the coprocessor 209 is
When used, the current consumption is lower than the current consumption of the CPU.
Observe the current waveform in this part because everything is relatively large
Makes it easy to identify the coprocessor operation mode
The encryption key Y can be obtained by the TA method and the SPA method.
Is likely to be deciphered. So, this fruit
In the coprocessor 209 of the embodiment, the encryption / decryption
Power multiplication X used for^YPerform modN operation
In this case, a dummy operation for the purpose of disturbance is inserted. One
That is, the timing chart of FIG. 3 and the flowchart of FIG.
E as shown _iA = 0 or 1^TwomodN and ABm
in order to always perform both operations of oddN.
You.

In the timing chart of FIG. 3, as shown in FIG. 3A, when e _n = 1, the calculation of A ² modN is originally performed, and after the time t 1, ABm is calculated by 1 in the determination of e _n.
The calculation of the oddN is performed, and after the calculation, i is decremented (n-1), and the time t2 is spent for the determination of i = 0. Next, when the next bit e _n-1 = 0, the operation of A ² modN is performed, the judgment of e _n-1 = 0 and i are decremented (n−
2) Then, time t3 is spent for determining i = 0. When the next bit e _n−2 = 1, the arithmetic operation of A ² mod _N is performed, and ABmod is applied after a time t1 by the determination 1 of e _n−2.
N is calculated, and after the calculation, i is decremented (n−
3) Then, time t2 is spent for determining i = 0. Hereinafter, those repeating the same similar operation to e _1.

In the coprocessor 209 of this embodiment, the operation of AB mod N is performed after the operation of A ² mod N regardless of the logic 0 or 1 of each bit e _i of the encryption key Y. The operation of ABmodN described above when e _i is a logical 0, such as when e _n-1 = 0 in FIG. 3B, is inserted as a dummy operation for the purpose of disturbance. That is,
As shown in the timing chart of (b) and the flow chart of FIG. 4, for example, a time t1 including the determination of the determination of e _i is spent between the arithmetic operations of A ² modN and ABmodN. Between the corresponding A ² modN operation operations, a uniform operation timing and operation current can be obtained in which the decrement operation of i and the determination time t2 of i = 0 are spent. However, in this embodiment, the determination processing of e _i is omitted in the flowchart of FIG. 4 because the result is not used as a condition for branching the operation.

FIG. 5 is a block diagram showing one embodiment of the coprocessor. In this embodiment, it is mainly composed of an arithmetic unit, control logic, and a dedicated register block, and the final result of the modular exponentiation operation is transmitted to the central processing unit CPU via a data buffer and a data bus. The selection operation of the dedicated register is performed in response to an address signal supplied from an address bus.

In this embodiment, the internal bus MDB and the read / write buffer (R / W Buffer) of the register block are used.
And a gate circuit 1 is provided. This gate circuit 1
Is controlled by the control logic, and if e _i is logic 0, the gate that has been opened after the operation result of the A ² modN operation is taken into the predetermined register CDA via the internal bus MDB and the read / write buffer is read. It is made to close.
In other words, when the operation result is taken into the read / write buffer, the gate is closed thereafter, and writing of new data to the read / write buffer is prohibited. Therefore, the calculation result of ABmodN performed thereafter is treated as invalid data. If e _i is logic 1, the gate circuit 1 keeps the gate open.

FIG. 6 is a block diagram showing another embodiment of the coprocessor. In this embodiment, the read / write buffer (R / W Buffer) of the register block is used.
A gate circuit 2 is provided between r) and each register. The gate circuit 2 is controlled by the control logic in the same manner as described above. If e _i is logic 0, the operation result of the A ² modN operation is written to a predetermined register CDA via the internal bus MDB and the read / write buffer. The gates that were open after being closed are closed. That is, when the result of the operation is taken into the register CDA, the gate is closed thereafter, and writing of new data to the register CDA is prohibited. Therefore, the operation result of ABmodN performed thereafter is written to the read / write buffer, but is actually treated as invalid data. If e _i is logic 1, the gate circuit 2 keeps the gate open.

FIG. 7 is a diagram showing the internal configuration of an embodiment of the gate circuit. The dummy write control unit is configured by an AND gate circuit. One input is supplied with a write enable signal from the control logic, and the other input is supplied with a write strobe signal generated by an arithmetic unit. The output signal of the gate circuit is transmitted to a data buffer (R / W Buffer) and a dedicated register as a write slope signal.

In this embodiment, the generation timing of a write strobe signal for instructing a write operation to a register or a data buffer is switched, instead of controlling transmission of the operation result itself. In other words, when e _i = 0, the write enable signal is set to low level after the operation result of the A ² modN operation is output so that the gate of the AND gate circuit is closed. Conversely, when e _i = 1, the control logic keeps the write enable signal at the high level, and the write strobe signal formed by the arithmetic unit is transmitted to the data buffer or the dedicated register as it is. In this configuration, it is not necessary to provide a plurality of gate circuits corresponding to the operation result A composed of a plurality of bits, so that simplification is possible.

FIG. 8 is a block diagram showing another embodiment of the coprocessor. In this embodiment, the read / write buffer (R / W Buffer) of the register block is used.
A selector 2 is provided between r) and each register, and a dummy register 1 is provided in a register block. This selector 2
Control is performed by the control logic in the same manner as described above. If e _i is logic 0, the operation result of the A ² modN operation is
B and a predetermined register C via the read / write buffer.
A signal path for writing to DA is formed, and then a signal path for selecting the dummy register 1 is formed.

That is, when the above operation result is taken into the register CDA, the dummy register 1 is selected thereafter. Therefore, while the writing of new data to the register CDA is inhibited, the operation result of ABmodN that is performed thereafter is stored in the dummy register 1A. Will be written to. e _i is logical 1
Then, the selector 2 always selects the register CDA. This configuration can be made completely the same when the current waveform is viewed when e _i is logic 0 and when it is logic 1 including the operation of writing the operation result to the register. Neutralization can be performed more reliably.

FIG. 9 is a block diagram for explaining the operation of another embodiment of the coprocessor according to the present invention. In the timing chart of FIG. 9A and the flowchart of FIG. 9B, as described above, A ² modN
After the calculation of ( _i) , A ² modN is continued as a dummy calculation operation during the time t1 of the determination of e _i , and the operation proceeds to the calculation of ABmodN.

After the operation, i is decremented (-1), and time t2 is spent for determination of i = 0.
The calculation of BmodN is continued. Hereinafter, those repeating the same similar operation to e _1. In this configuration, during the arithmetic operation, the arithmetic operation as described above is continued irrespective of when _ei is logic 0 and 1, so that no special feature can be found when viewed from the current waveform. Can be neutralized by using the attack.

FIG. 10 is a block diagram showing one embodiment for realizing the operation of the coprocessor shown in FIG.
In the control logic, a dummy enable signal and a copro enable signal are transmitted. The dummy enable signal and the co-pro enable signal are input to an arithmetic unit through an OR gate circuit. Therefore, the arithmetic unit performs an arithmetic operation when the dummy enable signal is active in addition to when the copro enable signal is active.

The dummy enable signal is supplied to one input of an AND gate circuit through an inverter circuit, and the other input of the AND gate circuit is supplied with a write strobe signal formed by an arithmetic unit. That is, transmission of the write strobe signal formed by the arithmetic unit can be selectively stopped by the dummy enable signal. When the normal operation is completed by activating the co-pro enable signal, a write strobe signal for outputting the operation result is formed. As described above, when the co-pro enable signal is active, the inverted signal of the dummy enable signal is set to the active level to control the gate of the AND gate circuit to be opened.
The result of the normal operation is represented by R
/ W buffer or a predetermined register of the register block.

When the above-described normal operation is completed, the dummy enable signal becomes active, and instructs the operation unit to execute the operation. Upon completion of this operation, the write strobe signal is formed. However, since the AND gate circuit closes the gate by the inverted signal of the dummy enable signal, the write strobe signal generated by the dummy operation operation for the purpose of the disturbance is generated. It is not transmitted to a predetermined register of the R / W buffer or the register block. As a result, the dummy operation result for the purpose of the disturbance is erased as invalid data.

FIG. 11 is a timing chart for explaining the operation of another embodiment of the coprocessor according to the present invention. As in the embodiment shown in FIG. 3, a dummy operation for the purpose of disturbance is inserted, and A ² modN and ABm are unified with respect to e _i as shown in the timing diagram of FIG.
Even if the calculation of the oddN is performed as a pair,
For each operation, there are those that require overflow processing (Yes) and those that do not require overflow processing (None).

Since such an overflow process increases the operation time, it is possible to distinguish between the presence and absence of the overflow process in the current waveform. Since it is considered that it is not impossible to infer the calculation contents and calculation data from such characteristics of the current waveform, in this embodiment, as shown in the timing chart of FIG. Even if necessary, overflow processing is inserted. That is, apparently, the operation for the overflow process is uniformly performed in all the calculations A ² modN and ABmodN, so that the identification is disabled.

FIG. 12 is a flow chart for explaining the operation of another embodiment of the coprocessor according to the present invention. This flowchart is shown in FIG.
This corresponds to (b). Each operation of A ² modN and ABmodN includes a remainder operation unit and an overflow operation unit, and performs the overflow operation process regardless of the operation result.

FIG. 13 shows a coprocessor according to the present invention.
Timing for explaining operation details of another embodiment of
FIG. Before the countermeasure according to this embodiment,
Note A ^TwoFor co-production operations like modN and ABmodN
In addition, overflow processing is performed according to the operation result.
There were two types, one with and one without, but in this example
After the countermeasure by^TwomodN and ABmodN
In such a co-production operation,
Is executed. For this reason,
Performed for arithmetic operations that do not require overflow processing.
Overflow processing is a dummy operation for the purpose of disturbance.
You.

FIG. 14 is a block diagram showing one embodiment for realizing the operation of the coprocessor shown in FIGS. The control logic sends out a dummy overflow signal and a co-pro overflow signal. The dummy overflow signal and the co-pro overflow signal are input to an arithmetic unit through an OR gate circuit. Therefore, the arithmetic unit performs the overflow processing operation when the dummy overflow signal is active in addition to when the copro overflow signal is active.

The copro overflow signal is supplied to one input of an AND gate circuit, and the other input of the AND gate circuit is supplied with a write strobe signal formed by an arithmetic unit. That is, transmission of the write strobe signal formed by the arithmetic unit can be selectively stopped when the copro overflow signal is not at the active level. In other words, when the co-pro overflow signal is not at the active level, the arithmetic unit performs overflow processing using the dummy overflow signal.
The write strobe signal formed by the overflow processing is invalidated by closing the gate of the gate circuit. Therefore, when the normal overflow processing is completed, a write strobe signal for outputting the processing result is formed, and the processing result is written to a predetermined register of the R / W buffer or the register block.

On the other hand, when the dummy overflow signal becomes active to instruct the arithmetic unit to perform the overflow processing operation, the write strobe signal formed by the overflow processing is AND gated by the co-pro overflow signal. Since the gate of the circuit is closed, the write strobe signal generated by the dummy overflow processing operation for the purpose of the disturbance is not transmitted to the R / W buffer or the predetermined register of the register block. As a result, the result of the dummy overflow processing for the purpose of the disturbance is erased as invalid data.

FIG. 15 is a timing chart for explaining the operation of still another embodiment of the coprocessor according to the present invention. Originally as shown in (a), e _n =
Performs an operation of A ² modN when one performs computation of ABmodN over time t1 by first determination of e _n, the time t2 to determine i = 0 is decremented (n-1) the i after the operation spend. Next, when the next bit e _n-1 = 0, the calculation of A ² modN is performed, and the determination of e _n-1 = 0 and i are decremented (n-2), and the time t3 is determined by the determination of i = 0. For the operation operation to be spent, a dummy cycle for the purpose of disturbance is inserted for the time t1, t2, and t3 for each operation.

In the timing diagram (b), the dummy cycle for the purpose of the disturbance is inserted so that the time for each operation is aligned with the longest time t3. As a result, A ² mod N or A ²
Since any operation of BmodN is performed, apparently, the current waveform corresponding to the operation is made uniform and the identification is disabled. On the other hand, in the timing diagram (c), a dummy cycle for the purpose of disturbance whose time randomly changes is inserted in the interval of each operation, contrary to the above (b). The above A ² mod N or A
Any operation of BmodN is randomly performed in time. Therefore, when viewed from the current waveform, the current value is irrelevant to each of the arithmetic operations and irregular. In other words, since the arithmetic unit has a non-reproducibility from a statistical point of view such that the same state and the same operation are different every time, the identification can be disabled.

The dummy cycle for the purpose of the disturbance as described above makes the calculation interval variable using a timer as shown in FIG. Alternatively, a timer is provided outside the coprocessor, and the execution of the next operation is waited until a certain time elapses. That is, in the operation of the modular exponentiation multiplication by the coprocessor, a dummy cycle for the purpose of disturbance is inserted into the times t1, t2, and t3 of each operation shown in FIG. Put in. As a result, the times t1, t2, and t3 are all constant as shown in FIG. 15B, making it difficult to attack from the current waveform. Alternatively, a random number generated by a random number generator may be set in the timer, and the times t1, t2, and t3 may be randomly changed every time as shown in (c). Also, the counting can be performed by software without using a timer.

In the modular exponentiation multiplication, if the value of Y is processed by 2 bits or 3 bits at a time for the purpose of speeding up the operation by the coprocessor, for example, FIG.
As shown in the flow chart of FIG. 2, if the description is made using the example of 2-bit processing, A ² mod N−A ² mod N−ABm
odN and i-2 and i = 0? Are repeated, so that the processing time and the current waveform are constant without performing the dummy operation for the purpose of disturbance as in the case of performing one bit at a time. Therefore, it becomes difficult to estimate the value of Y from the current waveform. In addition, the number of operations is 2n at the maximum in the case of the binary method, but 1.5n is always required in the case of 2-bit processing, which leads to a reduction in operation time.

By the time the coprocessor operation starts, A,
The values of B and N are respectively transferred to and stored in the coprocessor dedicated register. However, when performing 2-bit processing, there are four B values B ₁ , B ₂ ,
B ₃ and B ₄ are required, and these values are calculated in advance. It is stored in a RAM or EEPROM, etc. {circle around (1)} every time it is transferred to the coprocessor dedicated register. At this time, there is a possibility that a characteristic may appear in the current waveform during transfer depending on the four values of B.

For example, consider the case where data is transferred to a 16-bit precharge bus. The precharge bus is
This is a bus in which the values of all buses are set to "1" before data transfer. When data having different values but the same number of “1” bits, for example, “88” and “11” in hexadecimal with the number of “1” bits being 2 are transferred to this bus, the current waveform Are expected to have approximately the same waveform. This is because the same number of bits have changed from “1” to “0”, so that current is consumed in the same manner and the current waveform becomes the same.

If the number of bits of “1” is different from that of data by one, for example, “89” where the number of bits of “1” is three
Or "19", the current consumption is different from that of the data in which the number of bits of "1" is 2. Since the value of the bus for 13 bits has changed from "1" to "0", the current is consumed by that amount. Therefore, the current consumption is reduced by one bit as compared with the data in which the previous 14 bits have changed. Generally, there is a regularity that the current waveform becomes higher as the number of changing bits increases. It is likely that the data being transferred can be estimated from this regularity, and is likely to be subject to current attacks. The following measures are taken to prevent this.

FIGS. 17 and 18 are block diagrams of another embodiment of the coprocessor according to the present invention. The coprocessor of this embodiment is directed to 2-bit processing and 3-bit processing. In other words, the register capacity of the coprocessor is increased, and in the case of 2-bit processing, 4
B values B _{1 to} B ₄ are set to 8 in the case of 3-bit processing.
Storing the value B ₁ .about.B ₈ street B in a register of the coprocessor. Therefore, during the operation, the storage circuit (RAM)
This eliminates the need for such a transfer to the coprocessor register through the data bus, and can protect against the current attack.

[0049]

[0050]

In other words, in the flowchart shown in FIG. 16, when the coprocessor executes ABmodN, the correct B register CDB out of four (when three-bit processing or eight) is executed as described below. The two bits of Y (or 3
Bit) to the coprocessor control register (CCN
T), and in the case of 2-bit processing, AB _{1
modN, AB 2 modN, AB 3} modN, AB 4 m
The operator is allowed to select which operation to perform from among oddN.

FIG. 19 is a block diagram showing another embodiment of the coprocessor according to the present invention. The coprocessor of this embodiment is also directed to multi-bit processing such as 2-bit processing and 3-bit processing. In this embodiment, a switch is provided on the data bus so that data can be transferred while performing calculations. This configuration is effective in both reducing the execution time and preventing current attacks without increasing the register capacity of the coprocessor.

Coprocessor dedicated registers (CDA, CD
B, CDN, and CDW), as shown in the figure, four registers are exclusively used between the CPU and the arithmetic unit of the coprocessor. When performing 2-bit processing, two A ²
It is efficient if the value of B can be transferred from the RAM to the B register CDB in the coprocessor dedicated register unit while performing modN.

The I / O of the A register CDA and the B register CDB of the coprocessor are separated, and a read / write buffer (R / W Buffer) is provided for each, so that they can operate independently. While the computing unit is computing A ² modN, the control signal passes the data bus through path 1 (pa).
th1), the value of B is transferred from the RAM of the CPU (not shown) to the B register CDB via the independently provided read / write buffer. Next, the arithmetic unit is ABm
When executing the odN, a path 2 (pa) is controlled by a control signal.
th2), and sends the B value of the B register to the arithmetic unit so that the CPU cannot access the B register CDB. According to this method, the operation of A ² modN and the operation of transferring the B value are performed at the same time, so that not only the operation time is shortened, but also the current consumption of the operation and the transfer are overlapped, so that both waveforms cannot be identified. It is effective for current attack countermeasures.

FIG. 20 is a block diagram showing a main part of another embodiment of the IC card chip according to the present invention. In this embodiment, a counter is provided in the memory at the time of transfer between the cryptographic processing operation unit and the memory (RAM). In this embodiment, current disturbance when transferring four values used for 2-bit processing or eight values used for 3-bit processing from the coprocessor external memory RAM to the B register CDB in the coprocessor dedicated register unit is described. It is something to do.

In this embodiment, in the IC card chip shown in FIG. 2, a counter is provided on the RAM side. The RAM decodes the address signal formed by the counter and sends the data to the data bus. At this time, a fake address formed with a random number generator is transmitted to the address bus. Thereby, the correlation between the address and the data is lost, and the current analysis can be made difficult.

FIG. 21 is a block diagram showing one embodiment of the counter. The counter uses a head address register that holds the first address of the block to be transferred and an incrementer, and is controlled by an enable signal for enabling block transfer and an increment instruction signal such as a clock or a read / write signal. When starting a block transfer, first, a transfer start address and a transfer start enable signal are transmitted from the CPU to the counter.
It is held in the above-mentioned head address register. After that, the incrementer operates according to the increment instruction signal to form the start address A + 1 of the start address register, and generates the address and rewrites the contents of the start address register. As shown in the timing chart of FIG. increment RAM address in order a, a + 1, a + 2, will be ..., sequential data D _a in accordance with the address, D _{a +} 1, D _{a +} 2 · · · · is written / read.

In this embodiment, after the block transfer is enabled, the address from the address bus is not accepted by the counter, so that the data is correctly read no matter what value comes to the address bus. Therefore, random numbers B, C, D,
Is output, the current consumption of the address bus can be disturbed. From this effect, the current consumption of the entire chip can be disturbed. This makes it difficult to analyze the internal operation of the chip.

FIG. 23 is a main block diagram showing still another embodiment of the IC card chip according to the present invention. Also in this embodiment, a counter is provided in the memory at the time of transfer between the cryptographic processing operation unit and the memory (RAM). Address offset function is provided. That is, a random number generated by a random number generator or the like is simultaneously transferred to the CPU and the counter side in advance, and a value obtained by adding or subtracting the random number to the first address of the block transfer is output to the address bus. The counter decodes the value of the address bus using the same random number to obtain the first address.

FIG. 24 is a timing chart for explaining the transfer operation. The random number generated by the random number generator is transferred to the CPU and the RAM in advance, and the address A ± S obtained by adding or subtracting the random number S to or from the first address A of the block transfer by the offset calculation unit 1 is sent to the address bus. . On the counter side, the value of the address bus is decoded using the same random number S, and the offset calculation unit 2
, The first address A is obtained, and thereafter, it is incremented in the same manner as described above to generate addresses A + 1, A + 2,. Since the random number generator sends out random numbers B, C, D,... To the address bus in synchronization with the addresses A + 1, A + 2, the current consumption of the address bus including the head address can be disturbed, and the chip internal It becomes possible to make the operation analysis more difficult.

In the encryption / decryption device as in the above-described embodiment, the modular exponentiation operation “X ^Y modN” (X, Y, N
Is a positive integer), X, Y and N are usually 100
Since a very large number of bits to about 2000 bits is used, it is important how to execute " ^XY modN" at high speed. As one of the solutions, the following algorithm for executing the remainder multiplication “ABR ⁻¹ modN” is known.
No. 21057 (U.S. Registration No. 5,961,57)
8) proposes a microcomputer using a multiply-accumulate unit based on the algorithm of "ABR ^-1 mod N".

The above algorithm includes the following steps (1) to (12). (1) input X, Y = e n e n-1 ··· e 1, N, R (2) B = R 2 modN (3) A = X (4) A = ABR -1 modN + kN (5) B = A (6) for i = n-1 to 1 step-1 {(7) A = A 2 R -1 modN + kN (8) if e i = 1 then A = ABR -1 modN + kN (9)} (10) A = AR ^-1 modN + kN (11) A = AmodN (12) output A

In another embodiment of the present invention, in the coprocessor 209 shown in FIG. 2, "A = "Remainder multiplication" described in ABR ^-1 mod N + kN or the like is executed. The coprocessor 209 includes an arithmetic circuit and a control circuit as described later. The input values A, B, R, N and the output value A of the remainder multiplication are held in a dedicated register or a storage device such as a RAM.

FIG. 26 is a block diagram showing another embodiment of the coprocessor used in the present invention. In the figure, reference numeral 33 denotes a first product-sum operation unit, reference numeral 34 denotes a second product-sum operation unit, reference numeral 35 denotes a temporary register holding a primary storage value Temp, reference numeral 36 denotes a register used for storing a value A,
37 is a register used for storing the value B, and 38 is a register used for storing the value N. 39 is a Mi generation logic, 40 is a value M _i generated by the Mi generation logic 39
Is a shift circuit for performing “÷ 2 ^L ”.

In this embodiment, the operation "(AB _i
+ M _i N) / 2 ^L ". First, first
The multiply-add unit 33, the value of the register 35 Temp, the value A of the register 36, the value B _i of the register 37 as an input,
The product-sum operation “Temp + A · B _i ” is executed. The result of the operation is set as a value Temp2 in the second product-sum operation unit 34 in the next stage.
Sent to The value Temp2 is an integer of n + L bit length.

On the other hand, the Mi generation logic 39 receives the L-bit length numbers A ₀ , B _i , N ₀ as inputs and receives an L-bit integer M
generates _i, the positive number M _i is temporarily held in the register 40. The second sum-of-products arithmetic unit 34 calculates the Temp2,
With N and M _i as inputs, the product-sum operation “Temp2 + M _i
N ". The lower L bits of the operation result having the n + L bit length are all 0, and this is erased by the shifter 41 (that is, divided by 2 ^L ), and the result having the n bit length becomes the value T.
It is sent to the register 35 as emp and held.

By repeating the above operation n / L times, the operation "(AB + MN) / R" can be realized. According to this, it is not necessary to calculate and hold the n-bit integer M in advance, and only the L-bit length M _i is calculated by the product-sum calculator 33.
May be obtained during the calculation of the value and held in the register 40, and the value M
Can be eliminated, and the scale of the storage means for holding the value M can be reduced. Further, by connecting the product-sum calculator 33 and the product-sum calculator 34 in series and operating them continuously, it is also necessary to provide a special storage means for temporarily holding the intermediate result Temp2 having an n + L bit length. Disappears.

The registers 35 to 38 are stored in the product-sum operation units 33, 3
4 via a bus 43. Therefore, register 3
5 to 38 can be constituted by the RAM 42. As a result, the area of the register on the semiconductor chip can be reduced. Also, in this configuration, since the data transfer amount by the data bus 43 is particularly large, it is necessary to prevent the bus width from increasing and the area of the semiconductor chip from increasing. By connecting the calculator 33 and the product-sum calculator 34 in series, the intermediate result T
Since it is unnecessary to transfer emp2 using the data bus, it is possible to reduce the amount of data transferred by the bus.

[0069] In the co-processor of this embodiment, Temp = 0 in the first product-sum operation unit 33, M _i · N = 0 in the second product-sum operation unit 34, further by the selector 41 of the "÷ 2 ^L" By not performing the operation, the arithmetic means shown in the figure can perform a multiple length multiplication (multiplication of a small number B _i and a large number A corresponding to the multiple length thereof) such as “A · B _i ”. It can be used as a running circuit. The multiple-precision multiplication operation such as “A · B _i ” is performed in step (2) of the above algorithm.
Calculation “R ² mod N” of the microprocessor 201
By applying the above when executing using, it is possible to speed up the operation.

As shown in the conceptual diagram of the calculation of “R ² modN” in FIG. 27, R = 2 ⁿ , n = 512, and N
Is 512 bits, R ² is lower 1024 bits all only the most significant bit is 1 is the value of 0. When the operation “R ² mod N” is performed by a microprocessor, it is not efficient to directly divide a large number of R ² by a similarly large number of N, so the dividend is divided into blocks of 64 bits from the most significant side. In addition, the divisor is grasped as a block of 32 bits from the most significant side, and division is sequentially performed on the higher-order blocks, and the value obtained thereby is grasped as an approximate number of the quotient.

In the figure, for example, Q (= Da ÷ Na)
As an approximate number of quotients. Schematically, “Q · Na” is subtracted from the upper side of R ² , and “Q · Nb” is subtracted from the upper side of the subtraction result. The same processing is performed on the subtraction result of “Q · Nb”, and the same processing is repeated on the result, thereby obtaining “R ² mo”.
dN ”can be obtained.

In practice, a subtraction process for erasing surplus bits is interposed on the way. At this time, the processing of the calculation “Q · Nb” is performed in the first time by using 32 bits and 48 bits
This is a multiplication process of a large number of 0 bits. Moreover, such a large number of multiplication processes is repeated many times. At this time, by using a multiple length multiplication operation such as “A · B _i ” which can be operated by the coprocessor shown in FIG. 26, in other words, such multiple length multiplication operation is If the processor is burdened, when the operation “R ² modN” of step 2 in the above algorithm 5 is executed using the microprocessor 201, the speed of the arithmetic processing can be increased.

In the above algorithm, “A =
In the arithmetic processing of “ABR ⁻¹ modN”, as described in detail in the above-mentioned publication (Japanese Patent Laid-Open No. 10-21057),
In the remainder multiplication, when there is an overflow, N is further subtracted from the operation result W-N, so that the operation time and current consumption differ depending on the presence or absence of the overflow. Therefore, there is a possibility that the current consumption of the IC card LSI as described above is observed, and the operation in the chip is analyzed from the timing and the result of the statistical processing.

FIG. 28 is a block diagram showing a main part of an embodiment of the arithmetic unit for encryption processing according to the present invention. The arithmetic unit for encryption processing of this embodiment is included in a coprocessor included in a one-chip microcomputer mounted on an IC card or the like as described above.

Referring to FIG. 28, the first type shown in FIG.
When the product-sum operation unit comprising a second sum of product arithmetic unit 33, the A ² R ^-1 modN or operation of ABR ^-1 modN is performed, the calculation result W is temporary register Tem
The overflow flag OV from the arithmetic unit is stored in the OV storage register of the control logic when an overflow occurs in the operation result. Then, after the remainder multiplication, the operation result WN stored in the temporary register Temp is subtracted.

When the overflow flag OV is present (logic 1), the result of the subtraction WN is stored in a temporary register Temp, and the overflow flag OV
When there is no (logic 0), the result of the subtraction WN is not stored in the temporary register Temp, and an appropriate storage circuit other than the temporary register Temp, for example, the register A
Is stored in In other words, the operation of storing the subtraction WN and the invalid data formed by the subtraction in an appropriate storage circuit is the dummy operation for the purpose of confusion. This allows
Even when the overflow does not occur in the remainder multiplication, the operation current of the IC card accompanying the subtraction of the WN and storing the operation result in the register always occurs, and it is difficult to externally determine whether or not the overflow exists. You can do it.

The above signal processing is performed by the following program. W ← (AB + MN) / R Store OV bit if OV then W ← W−N (Regular overflow processing and writing to W) Else A ← W−N (Dummy overflow processing and writing to A) Exchange W and A Output A

In the above program, W represents a temporary register and its data. By exchanging the address of the temporary register Temp with the address of the register A when the overflow flag OV is absent, the data of W or A is output as valid data corresponding to the presence / absence of the overflow flag OV. . In this embodiment, Exchange W and
By the address exchange such as A, the data of the temporary register (W) is output by specifying the address of the register A.

The above signal processing can be replaced by the following program. W ← (AB + NM) / R Store OV bit A ← WN (Overflow processing and writing to register A) if! OV then Exchange W and A Else nop Output A

That is, after the subtraction WN for the overflow processing unconditionally and the result of the subtraction are written into the A register depending on the presence or absence of the overflow OV, if the overflow flag OV is not present, Exchange W
As in the case of "and A", the address is exchanged to output the data of the temporary register (W) by specifying the address of the register A, and if not, the data W-N of the A register is output as valid data without exchanging the address.

The above signal processing can be further replaced by the following program. W ← (AB + NM) / R Store OV bit Exchange W and A W ← AN (Overflow processing and writing to register A) if OV then Exchange W and A Else no Output A

That is, before performing the subtraction WA for the unconditional overflow processing in the presence or absence of the overflow OV, the address is exchanged as in Exchange W and A, and the AN is subtracted, that is, WN And outputs data to a temporary register (W), that is, a register A. And the overflow flag OV
If there is, the address is exchanged again as in the case of Exchange W and A, and the data in the register A is changed to the overflow flag OV by specifying the address of the register A.
If there is no data, the data of the temporary register (W) is output by specifying the address of the register A while the data is exchanged as described above. In this configuration, the logic circuit for writing to the register has a configuration in which the temporary register (W) is apparently written, so that the logic for writing to the register A becomes unnecessary and the circuit can be simplified.

The address exchange between the temporary register Temp and the register A can be realized by a flag inversion circuit. That is, of the address signals supplied from the address bus, for example, one bit such as the least significant bit is set to be different between the temporary register Temp and the register A, and the bit inversion is selectively exchanged by the flag inversion circuit. By simply doing so, the register A can be selected by specifying the address assigned to the temporary register Temp, and conversely, the temporary register Temp can be selected by the address assigned to the register A.

In the embodiment shown in FIG. 28, two registers Temp and A are used, and one register (for example, a temporary register Temp) is always used in correspondence with the overflow flag OV.
And the valid data is output by the address designating the register A by the address exchange as described above. The operation of storing the subtraction WN and the invalid data formed by the subtraction in an appropriate storage circuit is a dummy operation for the purpose of confusion. Thereby, even when the overflow does not occur in the remainder multiplication, the operation current of the IC card is always generated due to the subtraction of the WN and storing the operation result in the register, and it is difficult to externally determine whether or not the overflow exists. Can be done.

As in the above embodiment, a borrow (Borro) is used instead of the overflow flag of the multiply-accumulate operation unit.
w) The flag BR may be used. That is, the operation result W of the A ² R ^-1 modN or the ABR ^-1 mod N is stored in the temporary register Temp, and W-N
The borrow flag BR from the arithmetic unit when the subtraction is performed is stored. Only when the borrow flag BR is present, the address of the temporary register Temp and the address of the register A are exchanged. The information may be read out.

The above signal processing can be realized by the following program.

FIG. 29 is a block diagram showing a main part of another embodiment of the encryption processing operation unit according to the present invention. The encryption processing operation unit of this embodiment is also included in the coprocessor included in the one-chip microcomputer mounted on the above-described IC card or the like. In this embodiment, one of the signal of the data bus and the output of the multiply-accumulate unit is used as the overflow flag O stored in the OV flag storage register.
A selector for outputting according to V is added.

After the remainder multiplication, WN subtraction is performed.
The subtraction result WN and the value of W read on the data bus for the operation are input to the selector, and the subtraction result WN is output when the overflow flag OV is present, and the data bus W is output when the overflow flag OV is not present. Is selected, and the selected value is stored in the register A.
Is finally output as valid data,
An operating current of the IC card or the microcomputer is always generated due to the subtraction of WN and the writing to the register, which makes it difficult to externally determine whether or not overflow has occurred.

FIG. 30 is a block diagram showing a main part of still another embodiment of the arithmetic unit for encryption processing according to the present invention. In this embodiment, a register X is added to the register block in the embodiment of FIG. In the same manner as described above, the subtraction of WN is performed after the remainder multiplication, and when the overflow flag OV is present, the subtraction result WN is stored in the register A. Is written. Thereafter, when the overflow flag OV does not exist, the addresses of the temporary register (W) and the register A are exchanged, and finally, valid data is output by the address for selecting the register A.

The above signal processing can be realized by the following program. W ← (AB + NM) / R Store OV bit if OV then A ← WN (Regular overflow processing and writing to A) Else X ← WN (Dummy overflow processing and writing to X) Exchange W and A Output A

The effects obtained from the above embodiment are as follows. That is, (1) an operation voltage is supplied by an external terminal being electrically connected to a read / write device, and an I / O operation including a data input / output operation accompanied by an encryption process or a decryption process.
In the C card, the encryption processing or the decryption processing includes a dummy processing operation for the purpose of disturbing similar to the original processing operation, so that the operation timing and operation current of the internal circuit are made uniform. An effect is obtained that decoding using the current waveform can be made difficult.

(2) In addition to the above, the encryption or decryption processing includes an exponentiation multiplication operation applicable to RSA cryptography or the like, thereby realizing an enhanced security of an IC card. Can be obtained.

(3) In addition to the above, high-speed data processing can be performed by performing the above-described modular exponentiation operation by an encryption processing operation unit that operates in response to an instruction from the central processing unit. The effect that it can be obtained is obtained.

(4) In addition to the above, the operation of the arithmetic unit for encryption processing receives the input X, Y, and N, sets A = 1, B = X, and sets A = A ² modN and A =
The operation of ABmodN is performed alternately. In this operation, when the upper bit of Y is viewed one bit at a time, and the logic 0, the above A
The calculation results of the ² modN uptake in the storage circuit as valid data, the A ² modN and ABmo is logic 1
The result of the operation of dN is taken into the storage circuit as valid data, and the operation of A = ABmodN at the time of logic 0 is used as the dummy processing operation for the purpose of the disturbance, so that the current waveform is used while performing the encryption processing. This makes it possible to make the decryption difficult.

[0095] (5) In addition to the above, using a register block including a plurality of registers data input and output is performed through the read-write buffer the memory circuit, the gate by a logical 1 or 0 of a specific bit e _i of the Y A circuit is controlled to control transmission of a write strobe signal supplied to a predetermined register, and only valid data among the operation results is stored in the predetermined register through a read / write buffer, thereby performing encryption processing. In addition, it is possible to obtain an effect that the decoding using the current waveform can be made difficult.

(6) In addition to the above, the storage circuit uses a register block including a plurality of registers for inputting and outputting data through a read / write buffer.
Controls the gate circuit by a logic 1 or 0 of a specific bit e _i of the Y, and controls the transmission of the write strobe signal supplied to the read-write buffer, valid data only read write buffer of the calculation result By storing the data in the above-mentioned predetermined register, the decryption using the current waveform can be made difficult while performing the encryption processing.

(7) In addition to the above, the storage circuit uses a register block including a plurality of registers and a dummy register for inputting and outputting data through a read / write buffer, and the read / write buffer, the dummy register, and the A selector is provided between the read and write buffers to store valid data among the operation results written in the read / write buffer in a predetermined register and to control the invalid data by controlling the logical 1 or 0 of the specific bit e _i of Y. By storing the data in the dummy register, it is possible to obtain the effect that the decryption using the current waveform can be made more difficult while performing the encryption processing.

(8) In addition to the above, the operation of the arithmetic unit for encryption processing receives the input X, Y and N, and sets A = 1, B = X, A = A ² mod N and A =
The operation of ABmodN is performed alternately. In this operation, when the upper bit of Y is viewed one bit at a time, and the logic 0, the above A
The operation result of ² mod N is taken into the storage circuit as valid data at the output timing thereof.
The calculation results of ² mod N and AB mod N are fetched into the storage circuit as valid data at the output timing, and are obtained from when the calculation result of A = A ² mod N is output until the calculation of A = AB mod N is started. In the meantime, the operation of the above A = A ² mod N is continued, and A = AB mod
By continuing the operation of A = ABmodN from the output of the calculation result of N to the start of the calculation of A ² modN corresponding to the next bit including the change determination process of the bit of Y, The effect is obtained that the decryption using the current waveform can be made more difficult while performing the encryption processing.

(9) In addition to the above, the operation of the arithmetic unit for encryption processing receives the input X, Y, and N, sets A = 1, B = X, and sets A = A ² modN and A =
An ABmodN operation and an overflow operation are performed on each of them. In such an operation, the upper bit of Y is examined one bit at a time, and if it is logic 0, the above A ² modN operation result is taken into the storage circuit as valid data, For example, the operation results of A ² mod N and AB mod N are fetched into the storage circuit as valid data, and the operation of A = AB mod N when the logic is 0 and the unnecessary overflow operation in each operation are performed by the above-mentioned disturbance object. With the dummy processing operation described above, there is an effect that the decryption using the current waveform can be made more difficult while performing the encryption processing.

(10) An operating voltage is supplied when the external terminal is electrically connected to the read / write device.
In addition, an IC card in which an input / output operation of data is performed along with an encryption process or a decryption process includes a dummy operation for the purpose of disturbance in the encryption process or the decryption process, and an operation timing and an operating current of an internal circuit. By giving the irregularities to the IC card, it is possible to obtain an effect that it is possible to obtain an IC card in which the decryption using the current waveform is more difficult while performing the encryption processing.

(11) An operating voltage is supplied when the external terminal is electrically connected to the read / write device.
In addition, an IC card in which data input / output operation is performed along with the encryption or decryption processing includes a dummy cycle for the purpose of disturbance in the interval of each operation in the encryption or decryption processing, so that the internal circuit is An IC that makes it more difficult to decipher using current waveforms while performing cryptographic processing by providing irregularities in operation timing and operation current
The effect that a card can be obtained is obtained.

(12) In a microcomputer having a module configuration including an input / output operation of data accompanied by an encryption process or a decryption process, the encryption process or the decryption process includes a dummy processing operation for the purpose of disturbance and is internally performed. By making the operation timing and the operation current of the circuit uniform, it is possible to obtain an effect that decoding using a current waveform for a modularized microcomputer can be made difficult.

(13) In addition to the above, by forming the module configuration of the microcomputer on one semiconductor substrate, it is possible to reduce the size and to prevent the direct decoding of programs or data other than the current waveform. The effect that it can be obtained is obtained.

(14) In addition to the above, the encryption or decryption processing of the microcomputer includes a power-residue multiplication operation applicable to RSA cryptography or the like, and the power-residue multiplication operation is performed by the central processing unit. Is performed by the cryptographic processing operation unit that operates in response to the above instruction, an effect is obtained that a high-speed cryptographic processing operation can be performed.

(15) In addition to the above, as the operation of the arithmetic processing unit for encryption processing of the microcomputer,
In response to the input X, Y and N, A = 1, B = X, and A = A ² modN and A = ABmodN are calculated. the uptake in the memory circuit the operation result of the a ² modN as valid data, if the logic 1 is assumed to incorporate a memory circuit the operation result of the a ² modN and ABmodN as valid data, when the above logical 0 By setting the arithmetic operation of A = ABmodN as the dummy processing operation for the purpose of the disturbance, it is possible to obtain an effect that it is difficult to perform the decryption using the current waveform while performing the encryption processing.

(16) In addition to the above, the operation of the arithmetic processing unit for encryption processing of the microcomputer includes:
In response to the input X, Y and N, A = 1, B = X, and A = A ² modN and A = ABmodN are calculated. For example, the result of the A ² modN operation is taken into the storage circuit as valid data at the output timing as valid data, and when the logic is 1, the result of the A ² mod N and AB mod N operation is taken as valid data into the storage circuit at the output timing. , and the above a = a ² between modN the operation result is outputted to the a = operation ABmodN is started round also continue the operation of the ^{a = a 2 modN, a =} ABmodN of the operation result Even after the output is performed and before the calculation of A ² modN corresponding to the next bit is started, including the change determination processing of the Y bit, the above A
By continuing the operation of = ABmodN, it is possible to obtain an effect that decryption using a current waveform can be made difficult while performing encryption processing. (17) In addition to the above, as an operation of the encryption processing operation unit of the microcomputer, the input X, Y, and N are received, and A = 1, B = X, and A = X ^Y
performs overflow calculation on modN and A = ABmodN operations and each, as viewed by one bit from the Y level in such operations, the A ² m is logic 0
Uptake in the memory circuit the calculation result of odN as valid data, the A ² modN and ABmodN is logic 1
Is taken into the storage circuit as valid data. The arithmetic operation of A = ABmodN when the logic is 0 and the unnecessary overflow operation in each arithmetic operation are set as the dummy processing operation for the purpose of the disturbance. Accordingly, it is possible to obtain an effect that decryption using a current waveform can be made difficult while performing encryption processing.

(18) In addition to the above, the input X, Y, and N are received by the encryption processing operation unit, and A = 1, B = X, and according to the value of the Y bit,
A: A = A ² R ⁻¹ mod N, A = ABR ⁻¹ mod N, and a normal operation of performing N subtraction W−N of N from the above calculation result W when an overflow occurs in the calculation result. Even if no overflow occurs in the operation result, a dummy operation for the purpose of disturbance for generating invalid data by the operation corresponding to the subtraction WN is performed, and valid data is output in accordance with the presence or absence of the above-mentioned overflow. The advantage is that it is possible to make it difficult to decipher using the current waveform while simplifying and increasing the speed of the arithmetic processing unit.

(19) In addition to the above, A ² R ^-1 m
The operation result W of the oddN or ABR ^-1 modN is stored in the first storage circuit, the presence / absence of the overflow flag OV of the operation unit is stored, and N is subtracted from the operation result W of the first storage circuit after the remainder multiplication. WN is performed, and the operation result is stored in the first storage circuit when the overflow flag OV is present, and is stored in a second storage circuit different from the first storage circuit when the overflow flag OV is not present. Of the first storage circuit, and outputs the operation result of the first storage circuit as valid data, thereby simplifying and speeding up the operation unit for the encryption process and making it difficult to decipher using the current waveform. Is obtained.

(20) In addition to the above, A ² R ^-1 m
The arithmetic result W of the oddN or the ABR ^-1 modN is stored in the first storage circuit, the presence or absence of the overflow flag OV of the arithmetic unit is stored, and after the remainder multiplication, the N is calculated from the arithmetic result W of the first storage circuit. The subtraction WN is performed. When the overflow flag OV is present, the operation result W-N is selected by the selector. When the overflow flag OV is not present, the operation result W of the first storage circuit is selected by the selector, and the second operation result is selected by the selector. By storing it in the storage circuit, it is possible to obtain the effect that the decryption using the current waveform can be made difficult while simplifying and increasing the speed of the operation unit for encryption processing.

(21) In addition to the above, A ² R ⁻¹ m
The arithmetic result W of the oddN or the ABR ^-1 modN is stored in the first storage circuit, the presence or absence of the overflow flag OV of the arithmetic unit is stored, and after the remainder multiplication, the N is calculated from the arithmetic result W of the first storage circuit. The subtraction WN is performed. When the overflow flag OV is present, the subtraction WN is stored in the second storage circuit. When the overflow flag OV is not present, the subtraction WN is stored in the third storage circuit. Is present, the data in the second storage circuit is output as valid data, and the overflow flag OV
When there is no data, the data of the first storage circuit is output as valid data, so that it is possible to simplify and speed up the operation unit for the encryption process and make it difficult to decipher using the current waveform. The effect is obtained.

(22) In addition to the above, A ² R ⁻¹ m
The arithmetic result W of the oddN or the ABR ^-1 modN is stored in the first storage circuit, the presence or absence of the overflow flag OV of the arithmetic unit is stored, and after the remainder multiplication, the N is calculated from the arithmetic result W of the first storage circuit. The subtraction result W-N is stored in the second storage circuit, and when there is no overflow flag OV, the lowest address for selecting the first storage circuit and the second storage circuit is inverted, and the second storage circuit is stored. The first memory circuit is selected according to the address to be selected and output as valid data, and when the overflow flag OV is present, the second address is selected without changing the lowest address for selecting the first memory circuit and the second memory circuit. By outputting the operation result of the storage circuit as valid data, in addition to simplifying the operation unit for encryption processing, power consumption is simplified while simplifying and speeding up the logic for writing to the register. An effect is obtained that decoding using the flow waveform can be made difficult.

(23) In addition to the above, A ² R ⁻¹ m
The operation result W of the oddN or ABR ^-1 modN is stored in the first storage circuit, the presence / absence of the overflow flag OV of the arithmetic unit is stored, and the first storage circuit and the second storage circuit are stored after the remainder multiplication. The addresses are exchanged, and from the operation result value W selected by the address for selecting the second storage circuit to N
Is subtracted, and the subtraction result WN is stored in the second storage circuit selected by the address for selecting the first storage circuit.
And the above address is exchanged again only when the overflow flag OV is present, and the data of the first or second storage circuit selected by the address for selecting the first storage circuit is output as valid data. As a result, in addition to the simplification of the encryption processing operation unit, it is possible to simplify the logic for writing to the register and to increase the speed, thereby making it difficult to decipher using the current waveform.

(24) In addition to the above, A ² R ^-1 m
The operation result W of the oddN or the ABR ^-1 modN is stored in the first storage circuit, and after the remainder multiplication, a subtraction W-N of N is performed from the operation result value W of the first storage circuit to perform the second storage. The borrow flag BR of the arithmetic unit at the time when the subtraction of WN is performed is stored. When the borrow flag BR is present, the lowest address for selecting the first storage circuit and the second storage circuit is stored. Invert, the operation result W of the first storage circuit is output according to the address for selecting the second storage circuit, and when there is no borrow flag BR, the lowest order for selecting the first storage circuit and the second storage circuit is output. By outputting the operation result WN of the second storage circuit with the address for selecting the second storage circuit while keeping the address as it is, in addition to simplifying the operation unit for encryption processing, writing to the register Argument The effect is that the decoding using the current waveform can be made difficult while simplifying the processing and increasing the speed.

(25) In addition to the above, as an arithmetic operation unit for encryption processing of the microcomputer, it receives X, Y, and N, and sets A = 1 and B = X according to the value of the Y bit. Where A = A ² R ⁻¹ mod N, A = AB
R- ¹ modN operation is performed, and when an overflow occurs in the operation result, a normal operation of further subtracting N from the operation result W is performed, and the subtraction is performed even when no overflow occurs in each operation result. By performing a dummy operation for the purpose of disturbance for generating invalid data by an operation corresponding to WN and outputting valid data in accordance with the presence or absence of the above-mentioned overflow, in addition to simplifying the arithmetic processing unit for encryption processing, The effect is obtained that the decoding using the current waveform can be made difficult while simplifying and speeding up the logic for writing to the register.

(26) In addition to the above, in the encryption processing operation unit of the microcomputer, the operation result W of A ² R ^-1 modN or ABR ^-1 mod N is stored in the first storage circuit, and The presence / absence of an overflow flag OV from the storage unit, and subtracting N from the operation result W of the first storage circuit after the remainder multiplication,
The operation result is stored in the first storage circuit when the overflow flag OV exists, and the overflow flag OV
When there is no V, the data is written into the second storage circuit different from the first storage circuit as the dummy operation for the purpose of the confusion, and the operation result of the first storage circuit is output as valid data, so that the encryption processing is performed. The effect is obtained that the decoding using the current waveform can be made difficult while simplifying and increasing the speed of the arithmetic unit.

(27) In addition to the above, the operation unit for encryption processing of the microcomputer stores the operation result W of A ² R ^-1 modN or ABR ^-1 mod N in the first storage circuit, and The presence / absence of the overflow flag OV of the device is stored. After the remainder multiplication, the operation result W-N is subtracted from the operation result W of the first storage circuit. N, and when there is no overflow flag OV, the selector selects the operation result W of the first storage circuit, stores it in the second storage circuit, and outputs it as valid data. The advantage is that the decoding using the current waveform can be made difficult while simplifying and speeding up the operation.

(28) In addition to the above, the arithmetic processing unit for encryption processing of the microcomputer stores the operation result W of A ² R ^-1 modN or ABR ^-1 mod N in the first storage circuit, and The presence / absence of an overflow flag OV is stored, and after the remainder multiplication, N is subtracted from the operation result W of the first storage circuit by W-N. When the overflow flag OV is not present, the subtraction result W−N is stored in the third storage circuit. When the overflow flag OV is present, the subtraction result W−N is stored in the second storage circuit.
Is output as valid data, and when there is no overflow flag OV, the data of the first storage circuit is output as valid data.
The effect is obtained that the decryption using the current waveform can be made difficult while simplifying and increasing the speed of the arithmetic unit for encryption processing.

(29) In addition to the above, the arithmetic processing unit for encryption processing of the microcomputer stores the operation result W of A ² R ^-1 modN or ABR ^-1 mod N in the first storage circuit, and The presence / absence of an overflow flag OV of the detector is stored. After the remainder multiplication, the subtraction result W−N of N from the operation result W of the first storage circuit is stored in the second storage circuit, and the overflow flag OV is not present. The lowest address for selecting the first storage circuit and the second storage circuit is reversed, the first storage circuit is selected by the address for selecting the second storage circuit, and output as valid data, and overflow occurs. When the flag OV is present, the operation result of the second memory circuit is output as valid data while leaving the lowest address for selecting the first memory circuit and the second memory circuit as it is. By the effect is obtained that can be difficult to decipher using in addition to simplifying the current waveform while achieving simplification of the write logic and faster to register the encryption processing operation unit.

(30) In addition to the above, the operation unit for encryption processing of the microcomputer stores the operation result W of A ² R ^-1 mod N or ABR ^-1 mod N in the first storage circuit, and Result value selected by the address for selecting the second storage circuit after exchanging the addresses of the first storage circuit and the second storage circuit after the remainder multiplication. The subtraction result WN is stored in the second storage circuit selected by the address for selecting the first storage circuit by performing the subtraction WN of W from N, and the above address is stored only when the overflow flag OV is present. The data is exchanged again, and the data of the first or second storage circuit selected by the address for selecting the first storage circuit is output as valid data, so that the data for encryption processing is output. Effect that decryption using the simplified addition current waveform while achieving simplification of the write logic and faster to registers calculation unit can be difficult to obtain.

(31) In addition to the above, the arithmetic processing unit for encryption processing of the microcomputer stores the arithmetic result W of A ² R ^-1 modN or ABR ^-1 mod N in a first storage circuit, After the remainder multiplication, the first
Is subtracted N from the operation result value W of the storage circuit, and stored in the second storage circuit. When the subtraction of WN is performed, the borrow flag BR is stored from the arithmetic unit, and the borrow flag BR is stored. When there is, the least significant address for selecting the first storage circuit and the second storage circuit is inverted, and the operation result W of the first storage circuit is output by the address for selecting the second storage circuit, When there is no borrow flag BR,
By leaving the lowest address for selecting the first storage circuit and the second storage circuit as it is, and outputting the operation result W-N of the second storage circuit by the address for selecting the second storage circuit, In addition to the simplification of the encryption processing operation unit, it is possible to simplify the logic for writing to the register and to increase the speed thereof, while making it difficult to use the current waveform for decoding.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, IC
The card may be one on which one semiconductor integrated circuit device is mounted, or one on which a plurality of semiconductor integrated circuit devices are mounted. The microcomputer may be formed on a single semiconductor integrated circuit device, or may be formed by mounting a CPU and its peripheral circuits on a plurality of chips and mounted on a single module substrate.

The arithmetic processing includes an arithmetic operation A and an arithmetic operation B as shown in a flowchart of FIG. Arithmetic processing with a branch of whether to perform,
Alternatively, it can be widely used when the next arithmetic processing is selectively added in response to the presence or absence of overflow in the arithmetic operation. That is, if the operation A is executed after the operation A, and if the operation B is unnecessary from the result of the operation A, an operation process that invalidates the operation result is performed. This is useful as a hacking measure for required data processing.

The microcomputer may be of any type as long as it includes a data processing device and a ROM in which the data processing procedure by the data processing device is written, and performs data input / output operation in accordance with the data processing procedure. . For example, the present invention can be widely applied to various microcomputers requiring security protection, such as a one-chip microcomputer for games and the like, in addition to the IC card chip as described above. INDUSTRIAL APPLICABILITY The present invention can be widely used for various IC cards and microcomputers requiring security.

[0124]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in an IC card to which an operating voltage is supplied by an external terminal being electrically connected to a read / write device and which includes an input / output operation of data accompanied by an encryption process or a decryption process, Alternatively, by making the decoding process include a dummy processing operation for the purpose of disturbance to make the operation timing and operation current of the internal circuit uniform, decoding using the current waveform can be made difficult.

In a microcomputer having a module configuration including an input / output operation of data accompanied by an encryption process or a decryption process, the encryption process or the decryption process includes a dummy processing operation for the purpose of disturbance and operates the internal circuit. By making the timing and the operating current uniform, it is possible to make it difficult for a modular microcomputer to use a current waveform for decoding.

[Brief description of the drawings]

FIG. 1 is an external view showing an embodiment of an IC card to which the present invention is applied.

FIG. 2 is a schematic block diagram showing one embodiment of an IC card chip mounted on an IC card according to the present invention.

FIG. 3 is a timing chart for explaining the operation of one embodiment of the coprocessor according to the present invention;

FIG. 4 is a flowchart for explaining the operation of the coprocessor of FIG. 3;

FIG. 5 is a block diagram showing one embodiment of the coprocessor of FIG. 3;

FIG. 6 is a block diagram showing one embodiment for realizing the operation of the coprocessor shown in FIG. 3;

FIG. 7 is a block diagram showing another embodiment of the coprocessor of FIG. 3;

FIG. 8 is a block diagram showing another embodiment of the coprocessor of FIG. 3;

FIG. 9 is a configuration diagram for explaining the operation of another embodiment of the coprocessor according to the present invention.

FIG. 10 is a block diagram showing one embodiment for realizing the operation of the coprocessor shown in FIG. 9;

FIG. 11 is a timing chart for explaining the operation of another embodiment of the coprocessor according to the present invention.

FIG. 12 is a flowchart for explaining the operation of another embodiment of the coprocessor according to the present invention;

FIG. 13 is a timing chart for explaining details of the operation of another embodiment of the coprocessor according to the present invention;

FIG. 14 is a block diagram showing one embodiment for realizing the operation of the coprocessor shown in FIGS. 11 to 13;

FIG. 15 is a timing chart for explaining the operation of still another embodiment of the coprocessor according to the present invention.

FIG. 16 is a flowchart showing another embodiment of the arithmetic operation of the coprocessor according to the present invention.

FIG. 17 is a block diagram showing another embodiment of the coprocessor according to the present invention.

FIG. 18 is a block diagram showing another embodiment of the coprocessor according to the present invention.

FIG. 19 is a block diagram showing another embodiment of the coprocessor according to the present invention.

FIG. 20 is a main part block diagram showing another embodiment of the IC card chip according to the present invention.

FIG. 21 is a block diagram showing one embodiment of the counter of FIG. 20;

FIG. 22 is a timing chart showing an example of the operation of the IC card chip of FIG. 20.

FIG. 23 is a main part block diagram showing still another embodiment of the IC card chip according to the present invention.

24 is a timing chart showing an example of the operation of the IC card chip of FIG.

FIG. 25 is a flowchart for explaining an arithmetic operation to which the present invention can be applied;

FIG. 26 is a block diagram showing another embodiment of the coprocessor used in the present invention.

FIG. 27 is a conceptual diagram showing a method of calculating “R ² modN” in the present invention.

FIG. 28 is a main part block diagram showing an embodiment of an operation unit for encryption processing according to the present invention.

FIG. 29 is a main part block diagram showing another embodiment of the arithmetic unit for encryption processing according to the present invention.

FIG. 30 is a main part block diagram showing still another embodiment of the encryption operation unit according to the present invention;

[Explanation of symbols]

201: central processing unit (CPU), 202: I / O port, 203: address bus, 204: data bus, 20
5. Clock generation circuit, 206 ROM, 207 RA
M, 208: EEPROM, 209: Coprocessor (operation unit for encryption processing), CDA, CDB, CDN,
CDW ... register. 33, 34: Product-sum operation unit, 35: Temporary register, 36-38: Register, 39: Mi
Generation logic, 40: latch (register) holding Mi, 41: shifter, 42: RAM, 43: data bus.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Kunihiko Nakata, Inventor Kunihiko Kodaira, Tokyo 5-20-1, Kamizuhoncho Within Hitachi Semiconductor Co., Ltd. (22) Inventor: Taku Tsukamoto 5-22-1, Kamimizu Honcho, Kodaira-shi, Tokyo In the Hitachi, Ltd. (72) ) Inventor Shigeo Hirabayashi 5-221-1, Josuihonmachi, Kodaira-shi, Tokyo Inside the Hitachi Super SII Systems Inc. (72) Inventor Hiroshi Watase 5-221-1, Josuihoncho, Kodaira-shi, Tokyo Sun (72) The inventor ▲ Taka ▼ Masatoshi Hashimachi 5-22-1, Kamizuhoncho, Kodaira-shi, Tokyo Nittsu-cho SII Systems F-term (reference) 5B035 BB09 CA38 5B062 AA07 CC01 EE01 EE02 EE10 JJ10 5J104 AA16 AA47 EA04 NA07 NA18 NA22 NA35 NA37 NA40

Claims (31)

[Claims] 1. An IC card which is supplied with an operating voltage when an external terminal is electrically connected to a read / write device, and includes an input / output operation of data accompanied by an encryption process or a decryption process. An IC card characterized in that the encryption processing or the decryption processing includes a dummy processing operation for the purpose of disturbance to make the operation timing and the operation current of the internal circuit uniform. 2. The IC card according to claim 1, wherein the encryption processing or the decryption processing includes a power-residue multiplication operation applicable to RSA encryption or the like. 3. The IC card according to claim 2, wherein the power-residue multiplication operation is performed by a cryptographic processing operation unit that operates in response to an instruction from a central processing unit. 4. The encryption processing unit according to claim 3, wherein the encryption processing operation unit receives the input X, Y, and N, and sets A = 1, B = X, and A = A ² mod N
And A = ABmodN are alternately performed. In this operation, the upper bits of Y are examined one bit at a time. If the logic is 0, the result of the A ² modN operation is taken into the storage circuit as valid data. The operation results of A ² mod N and AB mod N are taken into the storage circuit as valid data, and A = ABm when the logic is 0
An IC card wherein the operation of oddN is the dummy processing operation for the purpose of disturbance. 5. The storage circuit according to claim 4, wherein the storage circuit is a register block including a read / write buffer and a plurality of registers for inputting / outputting data through the read / write buffer. controls the gate circuit by a logic 1 or 0 of a specific bit e _i, and controls the transmission of the write strobe signal supplied to a predetermined register, only valid data is stored in the predetermined register through the read-write buffer An IC card, characterized in that: 6. The storage circuit according to claim 4, wherein the storage circuit is a register block including a read / write buffer and a plurality of registers for inputting / outputting data through the read / write buffer. controls the gate circuit by a logic 1 or 0 of a specific bit e _i, and controls the transmission of the write strobe signal supplied to the read-write buffer, only valid data stored in the predetermined register through the read-write buffer IC characterized by the following:
card. 7. The storage circuit according to claim 4, wherein the storage circuit is a register block including a read / write buffer, a plurality of registers for inputting / outputting data through the read / write buffer, and a dummy register. A selector provided between the read / write buffer, the dummy register, and the plurality of registers is controlled by a logical 1 or 0 of the specific bit e _i of Y to determine which of the operation results written in the read / write buffer is valid. Data is stored in a predetermined register,
An IC card wherein invalid data is stored in the dummy register. 8. The encryption processing unit according to claim 3, wherein the encryption processing operation unit receives the input X, Y, and N, and sets A = 1, B = X, and A = A ² mod N
And performed alternately calculation of A = ABmodN, as viewed by one bit from the Y level in such operations, the uptake in the memory circuit at its output timing the operation result of the A ² modN as valid data is logic 0, logic If 1, the operation result of A ² modN and AB mod N is taken into the storage circuit at the output timing as valid data, and after the operation result of A = A ² mod N is output, the operation of A = AB mod N is output. The operation of A = A ² modN is continued until A is started, and A = AB
also is intended to continue the operation of the A = ABmodN until calculation of A ² modN corresponding to the next bit is started including the bit change determination processing Y from the calculation results of modN is outputted An IC card, characterized in that: 9. The encryption processing unit according to claim 3, wherein the encryption processing operation unit receives the input X, Y, and N, and sets A = 1, B = X, and A = A ² mod N
, And A = ABmodN, and an overflow operation is performed on each of them.
Looking at each bit, if the logic is 0, the result of the A ² modN operation is taken into the storage circuit as valid data, and if the logic is 1, the result of the A ² mod N and AB mod N operation is taken as valid data in the storage circuit. And
An IC card characterized in that the operation of A = ABmodN when the logic is 0 and the unnecessary overflow operation in each operation is the dummy processing operation for the purpose of the disturbance. 10. An operating voltage is supplied when an external terminal is electrically connected to a read / write device, and
An IC card in which data input / output operation is performed along with an encryption process or a decryption process, wherein the encryption process or the decryption process includes a dummy operation for the purpose of disturbance, and an operation timing and an operation current of an internal circuit. IC card characterized by having irregularities. 11. An operating voltage is supplied by an external terminal being electrically connected to a read / write device, and
An IC card in which data input / output operation is performed along with encryption processing or decryption processing, wherein an interval of each operation in the encryption processing or decryption processing includes a dummy cycle for the purpose of disturbance, and An IC card characterized by having irregularities in operation timing and operation current. 12. A microcomputer having a module configuration including an input / output operation of data accompanied by an encryption process or a decryption process, wherein the encryption process or the decryption process includes a dummy processing operation for a disturbance purpose. A microcomputer characterized in that operation timing and operation current of an internal circuit are made uniform. 13. The microcomputer according to claim 12, wherein the module configuration is realized by being formed on one semiconductor substrate. 14. The method according to claim 13, wherein the encryption processing or the decryption processing includes a power-residue multiplication operation applicable to RSA cryptography or the like, and the power-residue multiplication operation receives an instruction from a central processing unit. A microcomputer that is operated by a cryptographic processing operation unit that operates. 15. The encryption processing unit according to claim 14, wherein the encryption processing operation unit receives the input X, Y, and N, and sets A = 1, B = X, and A = A ² modN.
And A = ABmodN are alternately performed. In this operation, the upper bits of Y are examined one bit at a time. If the logic is 0, the result of the A ² modN operation is taken into the storage circuit as valid data. The operation results of A ² mod N and AB mod N are taken into the storage circuit as valid data, and A = ABm when the logic is 0
A microcomputer characterized in that the operation of oddN is the dummy processing operation for the purpose of the disturbance. 16. The arithmetic unit for encryption processing according to claim 14, wherein the encryption processing unit receives the input X, Y, and N, and sets A = 1, B = X, and A = A ² modN.
And performed alternately calculation of A = ABmodN, as viewed by one bit from the Y level in such operations, the uptake in the memory circuit at its output timing the operation result of the A ² modN as valid data is logic 0, logic If 1, the operation result of A ² modN and AB mod N is taken into the storage circuit at the output timing as valid data, and after the operation result of A = A ² mod N is output, the operation of A = AB mod N is output. The operation of A = A ² modN is continued until A is started, and A = A
A ² modN the operation result of BmodN from being output including change decision bits of Y corresponding to the next bit
The microcomputer is characterized in that the operation of A = ABmodN is continued even before the calculation of (1) is started. 17. The cryptographic processing unit according to claim 14, wherein the encryption processing operation unit receives the input X, Y, and N, and sets A = 1, B = X, and A = A ² modN.
, And A = ABmodN, and an overflow operation is performed on each of them.
Looking at each bit, if the logic is 0, the result of the A ² modN operation is taken into the storage circuit as valid data, and if the logic is 1, the result of the A ² mod N and AB mod N operation is taken as valid data in the storage circuit. And
A microcomputer characterized in that the arithmetic operation of A = ABmodN when the logic is 0 and the unnecessary overflow operation in each arithmetic operation is the dummy processing operation for the purpose of the disturbance. 18. The encryption processing unit according to claim 3, wherein the encryption processing operation unit receives the input X, Y, and N, sets A = 1, B = X, and sets A = A ² R ^-1 mod N, A = ABR ^-1 mod N
And a normal operation of subtracting N from the operation result W if the operation result overflows,
Even when overflow does not occur in each operation result, a dummy operation for the purpose of disturbance for generating invalid data by the operation corresponding to the subtraction WN is performed, and valid data is output according to the presence or absence of the overflow. Characteristic IC card. 19. The method according to claim 18, wherein the operation result W of the A ² R ⁻¹ modN or the ABR ⁻¹ mod N is stored in a first storage circuit, and the presence or absence of an overflow flag OV of the arithmetic unit is stored. After the multiplication, a subtraction WN of N from the operation result W of the first storage circuit is performed, and the operation result is stored in the first storage circuit when the overflow flag OV exists, and the overflow flag OV does not exist. An IC card which is sometimes written in a second storage circuit different from the first storage circuit as the dummy operation for the purpose of confusion, and the operation result of the first storage circuit is output as valid data. 20. The arithmetic unit according to claim 18, wherein the operation result W of A ² R ⁻¹ modN or ABR ⁻¹ mod N is stored in a first storage circuit, and the presence or absence of an overflow flag OV of the arithmetic unit is stored. After the multiplication, a subtraction WN of N from the operation result W of the first storage circuit is performed, and an overflow flag O
When V is present, the operation result WN is selected by the selector, and when there is no overflow flag OV, the operation result W of the first storage circuit is selected by the selector and stored in the second storage circuit to store valid data. An IC card, which is output as a message. 21. The method according to claim 18, wherein the operation result W of the A ² R ⁻¹ modN or the ABR ⁻¹ mod N is stored in a first storage circuit, and the presence or absence of an overflow flag OV of the arithmetic unit is stored. After the multiplication, a subtraction WN of N from the operation result W of the first storage circuit is performed, and the overflow flag OV
Is present, the subtraction W−N is stored in the second storage circuit, and if there is no overflow flag OV, the subtraction W−N is stored.
N is stored in the third storage circuit, and when the overflow flag OV is present, the data in the second storage circuit is output as valid data. When the overflow flag OV is not present, the data in the first storage circuit is valid. An IC card output as data. 22. The arithmetic unit according to claim 18, wherein the operation result W of the A ² R ⁻¹ modN or the ABR ⁻¹ mod N is stored in a first storage circuit, and the presence or absence of an overflow flag OV of the arithmetic unit is stored. After the multiplication, the subtraction result W-N of N from the operation result W of the first storage circuit is stored in the second storage circuit, and when there is no overflow flag OV, the first storage circuit and the second storage circuit are selected. Reverse the lowest address
The first storage circuit is selected by the address for selecting the second storage circuit and is output as valid data, and the lowest address for selecting the first storage circuit and the second storage circuit when the overflow flag OV is present. Wherein the calculation result of the second storage circuit is output as valid data while keeping the same as it is. 23. The arithmetic unit according to claim 18, wherein the operation result W of A ² R ⁻¹ modN or ABR ⁻¹ mod N is stored in a first storage circuit, and the presence or absence of an overflow flag OV of the arithmetic unit is stored. After the multiplication, the addresses of the first storage circuit and the second storage circuit are exchanged, and N is subtracted from the operation result value W selected by the address for selecting the second storage circuit.
The subtraction result W-N is stored in the second memory circuit selected by the address for selecting the first memory circuit after N is performed, and the address is exchanged again only when the overflow flag OV is present. An IC card which outputs data of the first or second storage circuit selected by an address for selecting the storage circuit as valid data. 24. The operation result of the first storage circuit according to claim 18, wherein the operation result W of A ² R ⁻¹ modN or ABR ⁻¹ mod N is stored in a first storage circuit, and the operation result of the first storage circuit after the remainder multiplication. Value W
, N is subtracted from N, and the result is stored in the second storage circuit. The borrow flag BR is stored in the arithmetic unit at the time when the WN is subtracted, and when the borrow flag BR is present, the first By inverting the lowest address for selecting the storage circuit and the second storage circuit,
The operation result W of the first storage circuit is output based on the address for selecting the second storage circuit, and when there is no borrow flag BR, the lowest address for selecting the first storage circuit and the second storage circuit is left as it is. The second address is selected by the address for selecting the second memory circuit.
Wherein the operation result of the storage circuit is output. 25. The encryption processing unit according to claim 14, wherein the encryption processing operation unit receives the input X, Y, and N, sets A = 1, B = X, and sets A = A ² R ^-1 mod N, A = ABR ^-1 mod N
And a normal operation of subtracting N from the operation result W if the operation result overflows,
Even when overflow does not occur in each operation result, a dummy operation for the purpose of disturbance for generating invalid data by the operation corresponding to the subtraction WN is performed, and valid data is output according to the presence or absence of the overflow. Characteristic microcomputer. 26. The method according to claim 25, wherein the operation result W of A ² R ⁻¹ modN or ABR ⁻¹ mod N is stored in a first storage circuit, and the presence or absence of an overflow flag OV from a processing unit is stored. After the remainder multiplication, a subtraction W−N of N is performed from the operation result W of the first storage circuit, and the operation result is stored in the first storage circuit when the overflow flag OV is present, and the overflow flag OV is set. When there is no microcomputer, the data is written as a dummy operation for the purpose of confusion in a second storage circuit different from the first storage circuit, and the operation result of the first storage circuit is output as valid data. . 27. The arithmetic unit according to claim 25, wherein the operation result W of the A ² R ⁻¹ modN or the ABR ⁻¹ mod N is stored in a first storage circuit, and the presence or absence of an overflow flag OV of the arithmetic unit is stored. After the multiplication, a subtraction WN of N from the operation result W of the first storage circuit is performed, and an overflow flag O
When V is present, the operation result WN is selected by the selector, and when there is no overflow flag OV, the operation result W of the first storage circuit is selected by the selector and stored in the second storage circuit to store valid data. A microcomputer characterized by being output as a. 28. The method according to claim 25, wherein the operation result W of the A ² R ⁻¹ modN or the ABR ⁻¹ mod N is stored in a first storage circuit, and the presence or absence of an overflow flag OV of the arithmetic unit is stored. After the multiplication, a subtraction WN of N from the operation result W of the first storage circuit is performed, and the overflow flag OV
Is present, the subtraction result W-N is stored in the second storage circuit. When there is no overflow flag OV, the subtraction result W-N is stored in the third storage circuit. When the overflow flag OV is present, the second storage is performed. A microcomputer wherein data of the circuit is output as valid data, and data of the first storage circuit is output as valid data when there is no overflow flag OV. 29. The arithmetic unit according to claim 25, wherein the operation result W of A ² R ⁻¹ modN or ABR ⁻¹ mod N is stored in a first storage circuit, and the presence or absence of an overflow flag OV of the arithmetic unit is stored. After the multiplication, the subtraction result W-N of N from the operation result W of the first storage circuit is stored in the second storage circuit, and when there is no overflow flag OV, the first storage circuit and the second storage circuit are selected. Reverse the lowest address
The first storage circuit is selected by the address for selecting the second storage circuit and is output as valid data, and the lowest address for selecting the first storage circuit and the second storage circuit when the overflow flag OV is present. A microcomputer that outputs the operation result of the second storage circuit as valid data while keeping the same as it is. 30. The arithmetic unit according to claim 25, wherein the operation result W of the A ² R ⁻¹ modN or the ABR ⁻¹ mod N is stored in a first storage circuit, and the presence or absence of an overflow flag OV of the arithmetic unit is stored. After the multiplication, the addresses of the first storage circuit and the second storage circuit are exchanged, and N is subtracted from the operation result value W selected by the address for selecting the second storage circuit.
The subtraction result W-N is stored in the second memory circuit selected by the address for selecting the first memory circuit after N is performed, and the address is exchanged again only when the overflow flag OV is present. Wherein the data of the first or second storage circuit selected by the address for selecting the storage circuit is output as valid data. 31. The operation result of the first storage circuit according to claim 25, wherein the operation result W of A ² R ⁻¹ modN or ABR ⁻¹ mod N is stored in a first storage circuit, and the operation result of the first storage circuit after the remainder multiplication. Value W
, N is subtracted from N, and the result is stored in the second storage circuit. The borrow flag BR is stored in the arithmetic unit at the time when the WN is subtracted, and when the borrow flag BR is present, the first By inverting the lowest address for selecting the storage circuit and the second storage circuit,
The operation result W of the first storage circuit is output based on the address for selecting the second storage circuit, and when there is no borrow flag BR, the lowest address for selecting the first storage circuit and the second storage circuit is left as it is. The second address is selected by the address for selecting the second memory circuit.
A microcomputer that outputs the operation result WN of the storage circuit.