JP2001265591A - Cpu - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CPU by which an existent assembler can be used as it is and an address space is extended by simple circuit constitution while the increase of instruction is suppressed. SOLUTION: The address signal A <15:0> of 16 bits generated when a jumping instruction is performed is decoded by a decoder 20, fixed data from outside is selected in accordance with a decoded 3-bit decode data by a selector 30 to be inputted to a CPU core 10 to output an extension address signal A<17:16> from the CPU core 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CPU that fetches an instruction and executes the fetched instruction.

[0002]

2. Description of the Related Art With the development of LSI technology in recent years, the capacity of memories has been increased, and accordingly, it has been required that CPUs also handle a wide address space. Conventionally, the following two methods have been known for handling a wide address space. The first method is CPU
In this method, a new instruction for handling a wide address space is added by changing the instruction decoding part of the instruction. In the second method, the CPU is used as it is, and the MMU (Memory
y Management Unit) to expand the address space.

[0003]

However, in the first method, it is necessary to change the instruction decoding part of the CPU.
In general, the instruction decoding portion of the CPU has a complicated circuit configuration for decoding a wide variety of instructions. If the instruction decoding portion is changed to add a new instruction, the instruction decoding portion is accompanied by the change. It is necessary to verify whether or not the operation of another instruction is executed correctly, which is a very enormous amount of work and has a problem that the development period is lengthened. It is not always easy to add a new instruction. For example, a new instruction is added in an 8-bit CPU in which instructions are defined over all instruction codes 00h to FFh ("h" indicates hexadecimal notation). In this case, for example, the 1-byte instruction code needs to be changed to a 2-byte instruction code such that the conventional instruction code FFh is “FFh + 00h” and the new instruction code is “FFh + 01h”. Therefore, compatibility at the machine language level cannot be maintained, and it is difficult to use the existing assembler as it is.

In the second method, a part or all of the memory space is banked by the MMU to expand the address space. In this case, it is necessary to insert a bank switching program. The inserted program is complex and therefore has the disadvantage of increasing the instruction code.

In view of the above circumstances, an object of the present invention is to provide a CPU in which an existing assembler can be used as it is and an address space is expanded with a simple circuit configuration while suppressing an increase in instruction codes. And

[0006]

According to a first aspect of the present invention, there is provided a CPU for fetching an instruction and executing the fetched instruction, comprising: an address generating circuit for generating an address to be accessed; And an extension address adding circuit for adding an extension address to the address generated by the address generation circuit.

The CPU of the present invention adds an extension address to an address generated at a predetermined timing. For example, as described in the following embodiment, a CPU generated at the timing of a conventional jump instruction is used. By adding an extension address to a jump address, a wide address space can be handled. Therefore, the existing assembler can be used as it is, and the address space can be expanded with a simple circuit configuration while suppressing an increase in instruction codes.

Here, the extended address adding circuit may add an extended address generated according to the predetermined address at a timing generated based on a timing at which the predetermined address is accessed. preferable.

By doing so, it is possible to generate an extension address corresponding to the predetermined address only by accessing the predetermined address of the memory.

[0010]

Embodiments of the present invention will be described below.

FIG. 1 is a circuit diagram of a CPU according to an embodiment of the present invention.

The CPU 100 shown in FIG. 1 includes a CPU core 10, a decoder 20, and a selector 30.

The CPU core 10 outputs a 16-bit address signal A <15: 0> and a 2-bit extended address signal A <17:16>.

The decoder 20 decodes the 16-bit address signal A <15: 0> output from the CPU core 10 and outputs 3-bit decoded data. In this decoder 20, when an address signal A <15: 0> representing addresses FF00h to FFFFh is input, 3
Bit decoded data '111' is output. When an address signal A <15: 0> representing addresses FE00h to FEFFh is input, 3-bit decoded data '110' is output, and addresses FD00h to FEFFh are output.
When an address signal A <15: 0> representing FDFFh is input, 3-bit decoded data '101' is output. Further, when address signal A <15: 0> representing addresses FC00h to FCFFh is input, 3-bit decoded data '100' is output, and address signals A <15: 0 representing addresses FB00h to 0000h other than the above. When> is input, 3-bit decoded data '000' is output.

The input terminal 30a of the selector 30 has a CP
2-bit extended address signal A <1 from U core 10
7:16> is input. In addition, each input terminal 30b, 3
To 0c, 30d, and 30e, 2-bit fixed data '11', '10', '01', and '00' are input from outside. Here, the select terminal 30f of the selector 30
When the decoded data '111' is input from the decoder 20, the fixed data '11' input to the input terminal 30b of the selector 30 is selected, and the fixed data '11' is set to the jump address signal JPA <17. : 16
> Are output. When the decoded data '110' is input from the decoder 20, the fixed data '10' input to the input terminal 30c of the selector 30 is selected, and the fixed data '10' is used as the jump address signal JPA <17: 16>. Further, when the decoded data '101' is input from the decoder 20, the fixed data '01' input to the input terminal 30d of the selector 30 is selected, and the fixed data '01' is selected.
Is output as the jump address signal JPA <17:16>. Also, the decoder 20 outputs the decoded data '1
When 00 ′ is input, the input terminal 30e of the selector 30
Is selected, and the fixed data '00' is input to the jump address signal JPA <1.
7:16>. Further, when decode data '000' is input from the decoder 20, the extension address signal A <17:16> input to the input terminal 30a of the selector 30 is selected, and the extension address signal A <17:16> is selected. Is the jump address signal JPA <1
7:16>.

FIG. 2 is a diagram showing a configuration of a memory connected to the CPU core shown in FIG.

The memory 40 shown in FIG. 2 is connected to the CPU core 10 shown in FIG. This memory 40 is 64K
B (byte) × 1 memory unit 40a
It is a 64 KB (byte) × 4 memory. The four memory units 40a are divided into pages 0, 1, 2, and 3. As shown on the left side of FIG. 2, each memory unit 40a has a program area (addresses 0000h to FBFFh) for storing programs and a page 0 designation area (addresses FC00h to FCFF) for designating page 0.
h), a page 1 designation area (addresses FD00h to FDFFh) for designating page 1 and a page 2 designation area (addresses FE00h to FDFFh) for designating page 2.
FEFFh) and a page 3 designation area (addresses FF00h to FFFFh) for designating page 3. Here, when the jump instruction JPnnnnn stored in the program area jumps to the address nnnnh in the program area, a conventional normal jump instruction is executed. As will be described later in detail, the jump instruction JPnn stored in the program area
Page 0 of the memory 40 is designated at the timing when nnh jumps into the page 0 designation area. Also, page 1 is specified at the timing of jumping to the page 1 specified area, page 2 is specified at the timing of jumping to the page 2 specified area, and page 3 is specified at the timing of jumping to the page 3 specified area. .

FIG. 3 is a diagram showing a part of the circuit of the CPU core shown in FIG.

The CPU core 10 shown in FIG. 3 is provided with an incrementer 11, registers 12, 14 and a selector 13. The registers 12 and 14 have an “L” level reset signal RES at an initial time such as when power is turned on.
Reset terminals 12d and 14d to which ET is input for a predetermined time
Is provided.

The incrementer 11 and the register 12
And the selector 13 correspond to an address generation circuit according to the present invention. The register 14, the decoder 20 and the selector 30 shown in FIG. 1 correspond to the extended address adding circuit according to the present invention.

The incrementer 11 receives the 16-bit address signal A <15: 0> output from the output terminal 13d of the selector 13, and inputs the input address signal A <15: 0>.
15: 0> is incremented and 16-bit address data is output.

The 16-bit address data from the incrementer 11 is input to the data terminal 12a of the register 12. A clock pulse CK_P from an internal circuit (not shown) is connected to a clock terminal 12b of the register 12.
C is input. The register 12 takes in the 16-bit address data input to the data terminal 12a with a clock pulse CK_PC, and outputs the data to a PC (Program
Counter) data PC <15: 0> is output.

The input terminal 13b of the selector 13 has a PC
Data PC <15: 0> is input. Further, a jump address signal JPA <15: 0> is input to an input terminal 13a of the selector 13 from an internal circuit (not shown).
This jump address signal JPA <15: 0>
When a jump instruction is executed by the U core 10, this is an address signal for designating a jump address generated by the jump instruction. Also, the select terminal 1 of the selector 13
The select signal SELJP is input to 3c. The select signal SELJP is a signal that goes to “H” level when a jump command is executed and goes to “L” level when another command other than the jump command is executed. Since the select signal SELJP is at “L” level in the normal execution state, the selector 13 outputs the PC data PC <15: 0 input to the input terminal 13b.
> To the outside as an address signal A <15: 0>. On the other hand, when the jump instruction is executed, the select signal S
When ELJP goes high, the jump address signal JPA <15: 0> input to the input terminal 13a is input.
As an address signal A <15: 0>.
The operation so far is the same as the operation of the conventional CPU. Less than,
FIGS. 1 to 3 and FIGS.
This will be described with reference to FIG.

FIG. 4 is a timing chart of the CPU core shown in FIG.

As described above, the memory 40 (see FIG. 2) divided into pages 0, 1, 2, and 3 is connected to the CPU core 10 of the present embodiment. Addresses m, m + 1, and m + 2 in the program area (addresses 0000h to FBFFh) of the memory unit 40a corresponding to page 0 of the memory 40 include a 3-byte jump instruction JP.
nnnnnh (C3, nnnnn (L), nnnnn (H))
Is stored. Note that this jump instruction JPnnnn
h jumps to a predetermined address in the page 1 designated area (addresses FD00h to FDFFh) in the memory unit 40a.

Here, a description will be given from a state where the program stored in page 0 has advanced to address m. Time t0
In this case, it is assumed that the select signal SELJP is at the “L” level. Therefore, the selector 13 outputs the address signal A <15: 0> from the output terminal 13 d of the selector 13.
Address signal P input to the input terminal 13b
C <15: 0>, that is, an address signal A <15: 0> representing the address m is output.

The data terminal 14a of the register 14 receives a 2-bit jump address signal JPA <17:16> from the selector 30 shown in FIG. Address signal A <1 representing address m is provided from CPU core 10.
5: 0> is output, and since this address m is within the addresses 0000h to FBFFh, the decoded data '000' is output from the decoder 20, whereby the selector 30 inputs the page data input to the input terminal 30a. Extended address signal A <17:16> representing 0 is output as jump address signal JPA <17:16>. Therefore, the jump address signal JPA <17:16> having the fixed data '00' is input to the data terminal 14a of the register 14. The jump signal JPNNNN is input from an internal circuit to the enable terminal 14e of the register 14. This jump signal J
PNNNNN is “H” when the above-described page 0, 1, 2, 3 designated area (FC00h to FFFFh) is designated.
Level, and the normal program area (0000h-F
When (BFFh) is specified, the level becomes “L” level. Here, an “L” level jump signal JPNNNN is input.

At time t0, when the read signal RD falls, one byte of data C3 stored at the address m is taken into the CPU core 10. The CPU core 10 interprets the data C3 as a jump command, and raises the read signal RD after a predetermined time has elapsed. Further, it increments the value of the incrementer 11 and outputs a clock pulse CK_PC. Then register 1
2, the value incremented by the incrementer 11 is fetched.
Address signal A <15: 0> representing 1 is output.
Further, time t0 shifts to time t1.

At time t1, when the read signal RD falls, one byte of data nnnn (L) stored at the address m + 1 is taken into the CPU core 10. Next, the read signal RD rises. Further, the value of the incrementer 11 is incremented, and then the clock pulse CK_PC is output. Then, the incremented value is taken into the register 12, whereby the selector 13 outputs the address signal A <15: 0> representing the address m + 2. Also, at time t1
Shifts to time t2.

At time t2, when the read signal RD falls, one byte of data nnnn (H) stored at the address m + 2 is taken into the CPU core 10. The CPU core 10 fetches a 3-byte jump instruction (C3, nnnn (L), nnnn (H)) and executes a JMP instruction (JPnnnnh). Then, the jump signal JPNNN changes from “L” level to “H” level. Further, jump address signal JPA <15: 0> representing address nnnnnh is output. Further, the select signal SELJP changes from “L” level to “H” level. Thus, the selector 13 supplies the address signal A <representing the address nnnnnh.
15: 0> is output. Address signal A <15: 0> representing address nnnnnh is applied to address FD00.
h to FDFFh, that is, an address signal A <15: 0> for designating page 1, and therefore, the decoder 20 outputs decoded data '101'. Thereby, in the selector 30, the input terminal 30
External 2-bit fixed data '01' input to d is selected, and a jump address signal JPA <17:16> having the data '01' is output.
In this manner, the data terminal 14a of the register 14
Jump address signal JP having fixed data '01'
A <17:16> will be input.

In the CPU core 10, the value of the incrementer 11 is incremented and the clock pulse CK_
Output PC. The clock pulse CK_PC is input to the clock terminal 12 b of the register 12, whereby the value of the incrementer 11 is stored in the register 12. The clock pulse CK_PC is also input to the clock terminal 14b of the register 14. Here, register 14
Since the “H” level jump signal JPNNNN is input to the enable terminal 14 e of the
4a input to the jump address signal JPA <1
7:16> is captured by the clock pulse CK_PC,
Thereby, the extension address signal A <17:16> having the fixed data '01' is output from the output terminal 14c of the register 14.
Is output. Thus, from CPU core 10, address signal A <1 representing address nnnnnh is output.
5: 0> and an extended address signal A <1 representing page 1
7:16>, thereby specifying the address nnnnh in page 1 of the memory 40. Also,
Time t2 shifts to time t3.

At time t3, when the read signal RD falls, the data stored in the address nnnnnh of page 1 is taken into the CPU core 10, and the jump signal JPNNNN changes from "H" level to "L".
Change to a level. After a lapse of a predetermined time, the process shifts from time t3 to time t4.

At time t4, when the read signal RD falls, the data stored at the address nnnn + 1h of page 1 is taken into the CPU core 10. In this way, by executing the jump instruction JPnnnnh stored in page 0, the program shifts to page 1 and the program stored in the page 1 at the address nnnnh can be executed.

FIG. 5 shows an existing assembler (16 bits)
FIG. 9 is a diagram showing a state where an address space extended to 18 bits is executed by a program described in FIG.

In the conventional CPU, as shown on the right side of FIG. 5, when a jump instruction JPIST (DIST is defined as address 4567h) stored at address 2345h of page 1 is executed, so,
That is, the address jumps from the address 12345h to the address 14567h. As described above, in the conventional CPU, the program is executed only in the 16-bit address space.

On the other hand, in this embodiment, according to the program described in the existing assembler shown on the left side of FIG. 5, when the jump instruction JPFF00h stored at the address 2345h of page 1 is executed, the page 1 Jump to address FF00h of This address FF
00h is a page 3 designation area (addresses FF00h to F
FFFh), and when the jump instruction JPFF00h is executed, the jump address signal JPA <having fixed data '11' for designating page 3 via the decoder 20 and the selector 30 as described above. 1
7:16> is output to the CPU core 10, whereby the CPU core 10 outputs an extended address signal <17:16> representing page 3. Then, the memory 40
Page 3 is specified, and the address FF in the page 3
The data stored in 00h is read. Here, at address FF00h in page 3,
Jump instruction JPIST (DIST is address 456
7h) is stored, so that the jump instruction JP4567 is executed in page 3. Therefore, the address 345h is changed to the address 345h.
It will shift to 67h. As described above, when accessing the memory 40 in which the address space is expanded to 18 bits, the data can be stored in 16 bits by inserting an indirect jump. Therefore, a program can be described using an existing assembler.

In the present embodiment, an example has been described in which an extension address is added to an address generated at the timing of a jump instruction. However, the present invention is not limited to a jump instruction, but is generated at a predetermined timing. What is necessary is just to add an extended address to the address.

[0038]

As described above, according to the present invention,
The existing assembler can be used as it is, and the address space can be expanded with a simple circuit configuration while suppressing an increase in instruction codes.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a CPU according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a memory connected to a CPU core shown in FIG. 1;

FIG. 3 is a diagram illustrating a part of a circuit of a CPU core illustrated in FIG. 1;

FIG. 4 is a timing chart of the CPU shown in FIG. 1;

FIG. 5 is a diagram showing how a program described in an existing assembler (16 bits) executes an address space extended to 18 bits.

[Explanation of symbols]

Reference Signs List 10 CPU core 11 Incrementor 12, 14 Register 12a, 14a Data terminal 12b, 14b Clock terminal 12c, 14c, 13d Output terminal 12d, 14d Reset terminal 14e Enable terminal 13 Selector 13a, 13b, 30a, 30b, 30c, 30d, 3
0e Input terminal 13c, 30f Select terminal 20 Decoder 30 Selector 40 Memory 40a Memory unit 100 CPU

Claims (2)

[Claims] An address generation circuit for generating an address to be accessed in a CPU that fetches an instruction and executes the fetched instruction, and an extension address is added to the address generated by the address generation circuit at a predetermined timing. A CPU comprising: 2. The method according to claim 1, wherein the extension address adding circuit adds an extension address generated according to the predetermined address at a timing generated based on a timing at which the predetermined address is accessed. The CPU according to claim 1, wherein