JP2001257653A - Carrier wave selection device and its method and receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a carrier wave selection device that can select a carrier wave component of prescribed frequency from a received signal. SOLUTION: The carrier selection device is provided with an HBF circuit 20 that limits the band of a signal S19 that is over-sampled with respect to a prescribed frequency, a down-sampling circuit 21 that down-samples the signal 20, a pre-filter circuit 22 that eliminates frequency components other than the frequency components of the carrier to be selected, and an interpolation circuit 23 that converts a sampling frequency of an output signal S22 of the circuit 22, which is a frequency higher than twice the symbol rate of the selected carrier and below a multiple of 2n (n is an integer being 2 or over), into a frequency twice the symbol rate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a carrier selecting apparatus for performing a carrier selecting process on a signal of a satellite broadcasting system or the like, a method thereof, and a receiving apparatus.

[0002]

2. Description of the Related Art In satellite communication, multiple access is usually used in which a communication path is simultaneously established between a plurality of earth stations using a single or a plurality of onboard satellite transponders. As one of such multiple access, there is an SCPC (Single Channel Per Carrier) system using one carrier for transmission of one channel. In the SCPC system, frequency division multiple access (FDM
A: A type of Frequency Division Multiple Access, in which one channel is transmitted using a carrier having a relatively small band and power, and a plurality of carriers are arranged at equal intervals in a satellite repeater. In the SCPC system, for example, individual information is transmitted via a plurality of carriers having a symbol rate lower than 10 MHz to 30 MHz, which is a normal television broadcast band, to effectively utilize the frequency.

In such a satellite communication receiver using the SCPC system, in order to select a predetermined carrier from a received signal and demodulate it at an appropriate bit rate, the sampling rate of the received signal is band-limited to a low frequency. Frequency conversion. For such frequency conversion, for example, a decimator circuit is used. The decimator circuit is configured, for example, by connecting a half-band filter circuit and a down-sampling circuit in series, limits the band of the received signal by the half-band filter circuit, and sets the frequency of the band-limited received signal to 1 by the down-sampling circuit. / 2. In a conventional receiving apparatus, a decimator circuit is connected in multiple stages to select a signal of a predetermined frequency from a received signal. In the receiving device, by connecting the decimator circuits in n stages, a signal having a frequency of (（) ⁿ times the frequency of the received signal can be selected from the received signal.

[0004]

However, as described above, in the conventional receiving apparatus, the frequency of the received signal is (1).
/ 2) Although a signal of ⁿ times frequency can be selected from the received signal, a signal of an arbitrary frequency cannot be selected from the received signal.

[0005] By the way, FMGardner describes "IEEE TRANSACT
IONS ON COMMUNICATIONS, VOL.41.NO.3.MARCH 1993 p5
01-507 "(hereinafter, referred to as a document). There is an interpolation method in a digital modem.
An output signal converted to an arbitrary frequency of 1/4 is generated. However, in the interpolation method, the frequency conversion ratio is as small as 1/2 to 1/4, and cannot be used as it is in the above-mentioned receiver for the SCPC satellite communication. That is, since the interpolation method has no band limiting capability,
When applied to a PC type receiving apparatus, there is a problem that a carrier to be selected receives interference (effect) from a plurality of interfering waves (unselected carriers).

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above-described problems of the related art, and has as its object to provide a carrier selection device and a reception device capable of selecting a carrier component of a predetermined frequency from a received signal with high quality.

[0007]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art and achieve the above-mentioned object, a carrier selection apparatus of the present invention selects a carrier having a predetermined frequency from a predetermined frequency band. A carrier selection device, comprising: a first filter circuit for band-limiting a signal oversampled for the predetermined frequency; a down-sampling circuit for down-sampling the band-limited signal; and the down-sampled signal. By limiting the bandwidth
A second filter circuit for removing a frequency component other than the frequency component of the selected carrier; and a sampling frequency of a signal processed by the second filter circuit, which is larger than twice the symbol rate of the selected carrier, 2 ⁿ And an interpolator for converting a frequency less than or equal to twice (n is an integer of 2 or more) to a double frequency.

The operation of the carrier selection device according to the present invention is as follows. In the first filter circuit, the band of the signal oversampled for the predetermined frequency within a predetermined frequency band is limited. Next, the down-sampled circuit down-samples the band-limited signal. Next, in the second filter circuit, the down-sampled signal is band-limited,
Frequency components other than the frequency component of the selected carrier are removed. Next, in the interpolation circuit, the sampling frequency of the signal processed by the second filter circuit is changed from a frequency that is more than twice the symbol rate of the selected carrier and 2 ⁿ times (n is an integer of 2 or more) or less. It is converted to twice the frequency. As described above, in the carrier selection device of the present invention, the signal is frequency-converted using the first filter circuit and the down-sampler circuit, and the signal is selected in the second filter circuit before being processed by the interpolation circuit. Frequency components other than the frequency component of the carrier are removed. Therefore, it is possible to effectively prevent the frequency component of the selected carrier from being affected by the interference wave in the processing in the interpolation circuit.

In the carrier selection apparatus of the present invention, preferably, the signal processed by the second filter circuit is larger than twice the symbol rate of the selected carrier.
so that the frequency is ⁿ times (n is an integer of 2 or more) or less,
A plurality of circuit modules including the first filter circuit and the down-sampling circuit are connected in series.

In the carrier selection apparatus of the present invention, preferably, the second filter circuit limits a band of the down-sampled signal to remove a carrier other than the selected carrier and a frequency component of imaging thereof. I do.

In the carrier selection apparatus of the present invention, preferably, the interpolation circuit includes k as a natural number, i as an index, k · Ti as a sampling timing of the output signal y,
When m is an index, the sampling timing of the input signal x is m · Ts, 0 ≦ μ _k <1, and hi (t) is an impulse response at time t, the arithmetic processing represented by the following equation (5) is performed. , Index i, m _k and μ _k are defined by the following equations (6), (7) and (8), respectively.

[0012]

(Equation 5)

[0013]

(Equation 6)

[0014]

(Equation 7)

[0015]

(Equation 8)

Further, in the carrier selection apparatus of the present invention, preferably, the interpolation circuit sets the sampling frequency of the signal output from the second filter circuit to more than twice and four times the symbol rate of the selected carrier. The following frequency is converted into a double frequency.

Further, in the carrier selection apparatus of the present invention, preferably, the first filter circuit limits a band of the signal in a system including a plurality of carriers of different frequencies in the predetermined frequency band.

Further, the receiving apparatus of the present invention comprises a receiving means for receiving a signal containing a plurality of carriers having different frequencies within a predetermined frequency band, and an A / D converter for converting the received signal into a digital signal. Circuit, a first filter circuit for band-limiting the signal obtained by the conversion, a down-sampling circuit for down-sampling the band-limited signal, and a carrier for selecting the carrier wave by band-limiting the down-sampled signal. A second filter circuit for removing a frequency component other than the frequency component of the second filter circuit; and setting the sampling frequency of the signal processed by the second filter circuit to be greater than twice the symbol rate of the selected carrier wave, 2 ⁿ
And an interpolator for converting a frequency less than or equal to twice (n is an integer of 2 or more) to a double frequency.

The operation of the receiving apparatus according to the present invention is as follows. In the receiving means, a signal including a plurality of carriers having different frequencies within a predetermined frequency band is received. Next, A
In the / D conversion circuit, the received signal is converted into a digital signal. Next, in the first filter circuit, the band of the converted signal is limited. Next, the down-sampled circuit down-samples the band-limited signal. Next, in the second filter circuit, the down-sampled signal is band-limited, and frequency components other than the frequency component of the selected carrier are removed. Next, in the interpolation circuit, the sampling frequency of the signal processed by the second filter circuit is changed from a frequency that is more than twice the symbol rate of the selected carrier and 2 ⁿ times (n is an integer of 2 or more) or less. 2
It is converted to double the frequency. As described above, in the receiving apparatus of the present invention, the frequency conversion of the signal is performed using the first filter circuit and the downsampling circuit, and the carrier wave to be selected in the second filter circuit before being processed by the interpolation circuit. Are removed. Therefore, it is possible to effectively avoid the influence of the interference wave on the frequency component of the selected carrier wave by the processing in the interpolation circuit, and to perform the subsequent processing in the demodulation circuit accurately.

Further, the receiving apparatus of the present invention preferably
The apparatus further includes a demodulation circuit that demodulates the signal converted by the interpolation circuit.

Further, the carrier selection method of the present invention is a carrier selection method for selecting a carrier having a predetermined frequency from a predetermined frequency band, wherein a band of an oversampled signal is limited for the predetermined frequency. Down-sampling the band-limited signal, band-limiting the down-sampled signal to remove frequency components other than the frequency component of the selected carrier, and selecting the sampling frequency of the signal from which the frequency component has been removed. Interpolation is performed to convert a frequency that is greater than twice the symbol rate of the carrier wave to be used and 2 ⁿ times (n is an integer of 2 or more) or less to twice the frequency.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a carrier selection apparatus 1 according to the background art of the present invention. As shown in FIG. 1, the carrier selection device 1
alf Band Filter) Circuit 10, Down Sampling (Down Samp)
le) Circuit 11 and interpolation (Interpolati
on) The circuit 12 is configured by connecting the circuits 12 in series. FIG.
FIG. 3 is a diagram for explaining an operation example of the carrier selection device 1 shown in FIG. 1. In the carrier selection device 1, for example, FIG.
As shown in (A), the sampling frequency Fs is 16 /
3 (# 5.3) received signal S0. Received signal S
0, the frequency component Ma of the carrier selected as a demodulation target in the frequency domain as shown in FIG.
in, the frequency component Adjc of the adjacent carrier, the frequency component Main and the imaging component Ima of the Adjc
g (Main) and imag (Adjc) are included.

The HBF circuit 10 is a filter having an asymmetric characteristic of a pass band and a stop band around an angular frequency ω = π / 2. The HBF circuit 10 performs a band limitation on the input received signal S0 shown in FIG. 2A as shown by a bold line in FIG. 2B to generate a signal S10. Signal S10
As shown in FIG. 2 (B), the frequency of the received signal S0 shown in FIG. 2 (A) from which almost half of the Nyquist frequency Nyq side of the frequency component Adjc of the adjacent carrier and the imaging component Imag (Adjc) has been removed. The signal has characteristics.

The down-sampling circuit 11 is an HBF circuit 1
The sampling frequency Fs of the signal S10 shown in FIG.
A signal S11 shown in (C) is generated.

The interpolation circuit 12 is a circuit for performing the interpolation of the above-mentioned document, and forcibly sets the sampling frequency (= about 2.7) of the signal S11 to 2.0, as shown in FIG. A signal S12 shown in FIG.

However, the signal S1 shown in FIG.
2 includes a frequency component Adjc of an adjacent carrier and an imaging component imag (Adjc) other than the frequency component Main of the carrier selected as a target of demodulation. If demodulation processing is performed as it is, the selected carrier is used. The transmitted signal cannot be demodulated accurately,
There is a problem that the BER (Bit Error Rate) of the demodulated signal increases.

First Embodiment of the Present Invention FIG. 3 is a configuration diagram of a carrier selection device 9 according to an embodiment of the present invention. As shown in FIG.
Is, for example, an HBF circuit 20, a down-sampling circuit 2,
1, a pre-filter circuit 22, an interpolation circuit 23, a roll-off filter circuit 24, and a down-sampling circuit 25 are connected in series. here,
The HBF circuit 20 corresponds to the first filter circuit of the present invention, the down-sampling circuit 21 corresponds to the down-sampling circuit of the present invention, the pre-filter circuit 22 corresponds to the second filter circuit of the present invention, The translation circuit 23 corresponds to the interpolation circuit of the present invention.

[HBF Circuit 20] The HBF circuit 20 is a filter having an odd-symmetric characteristic of a pass band and a stop band around an angular frequency ω = π / 2. FIG. 4 is a diagram illustrating an example of the configuration of the HBF circuit 20. As shown in FIG.
The circuit 20 is, for example, a 7-tap (Tap) filter, and includes delay circuits 30 ₁ to 30 ₆ , coefficient multiplication circuits 31 _{1 to} 3 _1.
17 and adder circuits 32 _{1 to} 32 ₆ . In the HBF circuit 20, when the n-th input signal is x _n and the signal x _n is input to the input terminal 33, the delay circuit 3
From signals 0 ₁ , 30 ₂ , 30 ₃ , 30 ₄ , 30 ₅ , and 30 ₆ , signals x _n−1 , x _n−2 , x _n−3 , x _n−4 , x
_n-5 and _xn-6 are output. Then, the coefficient multiplying circuit 31
In _{1-31 7,} respectively multiplies the signal x _n ~x _n-6 and the coefficient a ₁ ~a ₇ is performed. Here, for example, a _{1
= A 7 = -0.0351, a 2} = a 6 = 0, a 3 = a 5
= 0.2848 and a ₄ = 0.5.

The addition circuit 32 ₁ includes a coefficient multiplication circuit 31 ₁
A calculation result of addition of the operation result of the coefficient multiplication circuit 31 ₂ is performed, the addition result is output to the adding circuit 32 _2. The addition circuit 32 _2, addition of the calculation results of the coefficient multiplication circuit 31 ₃ and the addition result of the adding circuit 32 ₁ is performed, the addition result is output to the adding circuit 32 _3. The adding circuit 32 _3, the addition of the operation result of the coefficient multiplication circuit 31 ₄ and the addition result of the adder 32 ₂ is performed, the addition result is output to the adder circuit 32 _4. The adder circuit 32 _4, the addition of the operation result of the coefficient multiplying circuit 31 ₅ and the addition result of the adder circuit 32 ₃ is performed,
The addition result is output to the adding circuit 32 _5. Adder circuit 32
In _5, the operation result of the coefficient multiplying circuits 31 ₆ and the adder circuit 32
₄ is added to the result of addition, and the result of addition is
Output to ₂₆ . The adder circuit 32 _6, carried out the addition of the result of the coefficient multiplying circuit 31 ₇ and the addition result of the adder circuit 32 _5, the addition result is output to the output terminal 34 as an output signal y.

The operation in the HBF circuit 20 can be expressed, for example, by the following equation (9).
As shown in FIG.

[0031]

(Equation 9)

[Downsampling circuit 21] The downsampling circuit 21 sets the sampling frequency Fs of the input signal to 1
/ 2 is down-sampled to generate an output signal.

[Pre-filter circuit 22] The pre-filter circuit 22 band-limits the input signal to remove a carrier other than the selected carrier and the frequency component of the imaging thereof to generate an output signal. FIG. 6 is a diagram illustrating an example of the configuration of the down-sampling circuit 21. As shown in FIG. 6, the down sampling circuit 21 has, for example, 11 taps (T
ap) a filter, a delay circuit 30 ₁₁ ～～30 _20, coefficient multiplying circuits 31 ₁₁ to 31 ₂₁ and the adding circuit 32 _{11-32
Has 20} . The down-sampling circuit 21, the n-th input signal when the x _n, when the signal x _n is input to the input terminal 43, is from the delay circuit 30 _{11-30 20,} respectively signals x _n-1 ~ _xn-10 is output. Then, in the coefficient multiplying circuit 31 _{11-31 21,} respectively signals x _n ~
multiplication of x _n-10 and the coefficient a ₁₁ ~a ₂₁ is performed. here,
For example, a ₁₁ = a ₂₁ = −0.0063, a ₁₂ = a ₂₀ = −
_{0.0649, a 13 = a 19 =} -0.0319, a 13 = a
₁₈ = 0.1073, a ₁₅ = a ₁₇ = 0.3001, a ₁₆ =
0.3917.

The addition circuit 32 ₁₁ includes a coefficient multiplication circuit 31 ₁₁
A calculation result of addition of the operation result of the coefficient multiplication circuit 31 ₁₂ is performed, the addition result is output to the adding circuit 32 _12. The adding circuit 32 _12, addition of the addition result of the arithmetic operation result and adding circuit 32 ₁₁ of the coefficient multiplying circuit ₃₁₃ is performed, the addition result is output to the adding circuit 32 _13. The adding circuit 32 _13, addition of the addition result of the arithmetic operation result of the coefficient multiplying circuits 31 ₁₄ and adder circuit 32 ₁₂ is performed, the addition result is output to the adding circuit 32 _14. The adder circuit 32 _14, addition of the addition result of the arithmetic operation result of the coefficient multiplying circuits 31 ₁₅ and the adder circuit 32 ₁₃ is performed, the addition result is output to the adding circuit 32 _15. Adder circuit 32 ₁₅
In, addition the calculation result of the coefficient multiplying circuits 31 ₁₆ circuit 32 ₁₄
Is added to the result of addition, and the result of addition is
Output to ₁₆ . In the addition circuit 32 ₁₆ , the coefficient multiplication circuit 3
The addition of the result of the 1 ₁₇ and the addition result of the adding circuit 32 ₁₅ is performed, the addition result is output to the adding circuit 32 _17. The adding circuit 32 _17, addition of the addition result of the arithmetic operation result of the coefficient multiplying circuits 31 ₁₈ and the adder circuit 32 ₁₆ is performed, the addition result is output to the adding circuit 32 _18. The adder circuit 32 _18, the addition of the operation result of the coefficient multiplying circuits 31 ₁₉ and the addition result of the adder 32 ₁₇ is performed, the addition result is output to the adding circuit 32 _19. The adder circuit 32 _19, addition of the addition result of the arithmetic operation result of the coefficient multiplying circuits 31 ₂₀ and the adder circuit 32 ₁₈ is performed, the addition result is output to the adding circuit 32 _20. Adder circuit 32 ₂₀
In the calculation result of the coefficient multiplying circuit 31 ₂₁ and the adding circuit 32 ₁₉
Is added to the result of addition, and the result of addition is output to the output terminal 44 as an output signal y.

The operation in the pre-filter circuit 22 can be expressed, for example, by the following equation (10).
For example, as shown in FIG.

[0036]

(Equation 10)

[Interpolation Circuit 23] The interpolation circuit 12 is a circuit for performing the interpolation described in the above-mentioned document, and sets the sampling frequency of the input signal to a frequency greater than twice the symbol rate and less than 2 ⁿ times. To twice the frequency. n = is an integer of 2 or more. In the present embodiment, the interpolation circuit 23 that converts the sampling frequency of the input signal from a frequency that is greater than twice the symbol rate to four times or less to a frequency that is twice the symbol rate is exemplified.

Here, the sampling timing of the symbol of the output signal of the interpolation circuit 23 is set to time t.
= K · Ti, and the output signal obtained by the sampling is y (t). Here, k is a natural number.
Also, the impulse response at time t is h _I (t). Further, the input signal of the interpolation circuit 23 is x
(M), and the sampling timing of the symbol of the input signal is m · Ts. Here, m is an index. The index i is calculated by the following equation (1).
Defined as 1).

[0039]

[Equation 11]

In the above equation (11), int [z]
Is the largest integer value not exceeding z. The base point index m _K is defined by the following equation (12).

[0041]

(Equation 12)

Also, the fractional interval (fra
ctional interval) μ _k is defined by the following equation (13).
Here, 0 ≦ μ <1 is satisfied.

[0043]

(Equation 13)

The relationship between the input signal x and the output signal y in the interpolation circuit 23 is expressed by the following equation (14).

[0045]

[Equation 14]

The relationship between the sampling timing of the input signal and the sampling timing of the output signal in the interpolation circuit 23 is shown, for example, in FIG.

[Roll-off filter circuit 24 and down-sampling circuit 25]
In order to reduce intersymbol interference, the input signal is multiplied by a frequency characteristic according to the Nyquist characteristic at the time of transmission. Here, the original signal of the symbol rate frequency is restored by the combination of the roll-off filter circuit 24 and the down-sampling circuit 25.

Hereinafter, an operation example of the carrier selection device 9 will be described. For example, as shown in FIG. 9A, the reception signal S1 having a sampling frequency rate Fs of 16/3 (≒ 5.3)
9 is input to the HBF circuit 20. Here, the reception signal S
Assume that the symbol rate of 19 is 1. As shown in FIG. 9A, in the received signal S19, in the frequency domain, the frequency components Main,
The frequency component Adjc of the adjacent carrier and the frequency component M
ain and Adjc imaging components Imag (M
ain) and imag (Adjc).
In the HBF circuit 20, as shown by the bold line in FIG. 9B, a frequency component having a frequency rate of about 1.5 to about 4.0 in the received signal S19 is removed, and the signal S20 is generated. The signal S20 is, as shown in FIG.
In the received signal S19 shown in (A), the frequency component Adjc of the adjacent carrier and the imaging component Imag (Ad
Jc) has a frequency characteristic in which approximately half of the Nyquist frequency Nyq side has been removed.

Next, in the down sampling circuit 21,
The signal S output from the HBF circuit 20 and shown in FIG.
The sampling frequency Fs of 20 is down-sampled to １ ／, and a signal S21 shown in FIG. 9C is generated.

Next, in the pre-filter circuit 22, of the frequency components of the signal S21 output from the down-sampling circuit 21 shown in FIG. 9C, as shown by the bold line in FIG. And other imaging frequency components Adjc and Imag
(Adjc) is removed and the signal S22 shown in FIG.
Is generated.

Next, in the interpolation circuit 23, the output of the pre-filter circuit 22 shown in FIG.
The sampling frequency Fs of the signal S22 shown in FIG. 9 is converted from a frequency that is more than twice the symbol rate to four times or less to twice the frequency, and a signal S23 shown in FIG. 9E is generated. Thereafter, the signal S23 is processed by using the roll-off filter circuit 24 and the down-sampling circuit 25,
The original signal of the symbol rate frequency is restored (selected).

As described above, according to the carrier selection device 9, the signal S22 input to the interpolation circuit 23 by providing the pre-filter circuit 22 has a frequency component other than the frequency component Main of the carrier selected as a demodulation target. Is not included. That is, according to the carrier selection device 9, the influence of the aliasing phenomenon when the adjacent carrier exists can be removed. Therefore, when performing demodulation processing at a subsequent stage, the frequency component Main in the signal S23 is not affected by the interference wave, and the demodulation processing of the received signal can be performed with high accuracy. Error Rat
e) can be reduced as compared with the case where the carrier selection device 1 of the background art described above is used. Also, according to the carrier selection device 9, the interpolation circuit 2 can be configured with a simple circuit configuration by combining a plurality of decimator circuits constituted by the HBF circuit 20 and the down-sampling circuit 21.
The frequency rate of the received signal can be reduced to match the frequency conversion ratio of 3. Further, according to the carrier selection device 9, the frequency conversion can be reduced by using the interpolation circuit 23 that converts the frequency of the input signal from a frequency that is more than twice the symbol rate to four times or less to twice the frequency. It can be realized with a large-scale configuration.

Second Embodiment of the Present Invention Hereinafter, a receiving apparatus according to an embodiment of the present invention will be described. FIG. 10 is a configuration diagram of the receiving device 90 of the present embodiment. The receiving apparatus 90 uses, for example, frequency division multiple access such as the SCPC method, and uses BPSK (Binary Phase Shift
t Keying) and QPSK (Quadrature Phase ShiftKey)
ing) is used for a receiving apparatus that receives a signal subjected to phase shift modulation through a satellite repeater and demodulates a received signal.

As shown in FIG. 10, the receiving apparatus 90 includes, for example, an input terminal 110, a local oscillation circuit 111, an in-phase detection circuit 112, a phase shift circuit 113, a quadrature detection circuit 114, analog amplification circuits 115 and 116, and an LPF circuit. 118,1
19, A / D conversion circuits 120 and 121, oscillation circuit 12
2. HBF circuits 220 ₁ and 220 ₂ , down-sampling circuits 221 ₁ and 221 ₂ , pre-filter circuits 222 ₁ and 222
22 ₂ , interpolation circuit paths 223 ₁ , 223
₂ , complex multiplication circuit 130, roll-off filter circuit 22
4 _1, 224 _2, phase detector 133, loop filter circuit 134, the numerical control oscillation circuit 135, the signal conversion circuit 1
36, 137, a symbol decode circuit 145, a sample timing decision circuit 161, a loop filter circuit 16
2. Timing error detection circuit 163, AGC (Automated
atic Gain Control) circuit 147, PWM signal generation circuit 1
48 and a low-pass filter 149. here,
The input terminal 110 and the like correspond to the receiving means of the present invention, and the A / D
The conversion circuits 120 and 121 correspond to the A / D conversion circuit of the present invention, the HBF circuits 220 ₁ and 220 ₂ correspond to the first filter circuit of the present invention, and the down-sampling circuits 221 ₁ and 221.
221 ₁ corresponds to the down-sampling circuit of the present invention,
The pre-filter circuits 222 ₁ and 222 ₂ correspond to the second filter circuit of the present invention, and the interpolation circuit 22 1
3 _1, 223 ₂ corresponding to the interpolation circuit of the present invention, the symbol decoding circuit 145 corresponds to the demodulation circuit of the present invention.

The local oscillation circuit 111 receives the received signal S110
A local oscillation signal S111 having an intermediate frequency serving as a carrier of the in-phase detection circuit 112 and the phase shift circuit 11
Output to 3. Here, the reception signal S110 is the SPCP
This is the signal of the system. The in-phase detection circuit 112 outputs the local oscillation signal S111 and the QPSK input from the input terminal 110.
The in-phase component of the carrier is detected by multiplying by the modulated intermediate frequency reception signal S110, and the baseband I
A signal S112 is generated, and the signal S112 is
Output to The phase shift circuit 113 shifts the phase of the local oscillation signal S111 from the local oscillation circuit 111 by 90 degrees to generate a local oscillation signal S113.
4 is output. The quadrature detection circuit 114 outputs the local oscillation signal S
By multiplying 113 and the QPSK-modulated received signal S110 input from the input terminal 110, a quadrature component of the carrier is detected to generate a baseband Q signal S114, which is output to the analog amplifier circuit 116. .

The analog amplifier circuit 115 is an LPF circuit 1
The I signal S112 is amplified based on the amplification factor control signal S149 from S49 to generate an I signal S115, which is
Output to the PF circuit 118. Analog amplifier circuit 116
Amplifies the Q signal S114 based on the amplification factor control signal S149 from the LPF circuit 149, generates a Q signal S116, and outputs this to the LPF circuit 119.

The LPF circuit 118 removes the high frequency component of the I signal S115 to generate an I signal S118,
Output to the D conversion circuit 120. The LPF circuit 119 has Q
A high-frequency component of the signal S116 is removed to generate a Q signal S119, which is output to the A / D conversion circuit 121.

The oscillation circuit 122 generates an oscillation signal S122 having the same frequency as the predetermined sampling frequency of the reception signal S110,
0, 121. Here, the sampling frequency is larger than twice the symbol rate Rs for the sake of symbol timing reproduction (carrier reproduction).

The A / D conversion circuit 120 includes an oscillation circuit 122
Based on the oscillation signal S122 from to generate a digital I signal S120 by performing the A / D conversion of the I signal S118, and outputs it to the HBF circuit 220 _1. The A / D conversion circuit 121 receives the oscillation signal S122 from the oscillation circuit 122.
, An A / D conversion of the Q signal S119 is performed to generate a digital Q signal S121.
0 output _2.

The HBF circuit 220 ₁ limits the band of the I signal S 120 to generate an I signal S 220 _1, and outputs this to the down-sampling circuit 221 ₁ . HBF circuit 220 ₂
Generates a Q signal S220 ₂ with band-limited Q signal S121, and outputs it to the down-sampling circuit 221 _2. The HBF circuits 220 ₁ and 220 ₂ are, for example, the same as the HBF circuit 20 of the first embodiment described above, and have the configuration shown in FIG. 4 and the filter characteristics shown in FIG.

[0061] downsampling circuit 221 _1, I signal S
The sampling frequency Fs of 220 ₁ is down-sampled to _{１ ／} to generate an I signal S221 ₁ , which is output to the pre-filter circuit 222 ₁ . The down-sampling circuit 221 ₂ calculates the sampling frequency F of the Q signal S220 _2.
s is down-sampled to １ ／ and the Q signal S221 ₂
, And outputs it to the pre-filter circuit 222 _2.

The pre-filter circuit 222 ₁ receives the I signal S2
21 ₁ is band-limited to remove a carrier other than the carrier to be selected and its imaging frequency component to remove the I signal S
222 ₁ is generated and the interpolation circuit 2
And outputs it to the 23 _1. The pre-filter circuit 222 ₂ band-limits the W signal S221 ₂ to remove a carrier other than the carrier to be selected and its imaging frequency component to remove the carrier.
A signal S222 ₂ is generated and output to the interpolation circuit 223 ₂ . The pre-filter circuit 222 ₁ ,
222 _2, for example, is the same as the pre-filter circuit 22 of the first embodiment described above, it has a filter characteristic shown in arrangement and 7 shown in FIG.

[0063] interpolation circuit 223 _1, as the symbol decoding circuit 145 perform the determination of the symbol at the right time, the sampling timing determination signal from the sample timing decision circuit 161 S161
To generate an I signal S223 ₁ performs interpolation processing of the I signal S222 ₁ based on. Interpolation circuit 22
3 ₂ interpolates the Q signal S222 ₂ based on the sampling timing determination signal S161 from the sample timing determination circuit 161 so that the symbol decoding circuit 145 can determine a symbol at an appropriate timing, and performs the Q signal S223 _2. Generate As the interpolation circuit 223, for example, the above-described interpolation circuit 23 of the first embodiment is used.

The complex multiplying circuit 130 is connected to the signal converting circuit 13
Using signals S136 and S137 for carrier reproduction (for frequency pull-in and phase synchronization) from S.6, 137, I signal S223 ₁ and Q signal S223 ₂ are subjected to frequency pull-in processing based on the following equation (15). A phase synchronization process is performed, and the I signal S130a and the Q signal S130
Generate b.

[0065]

(Equation 15)

The roll-off filter circuit 224 ₁ performs a filtering process on the I signal S 130 a to reduce intersymbol interference to generate an I signal S 224 _1, and outputs the I signal S 224 ₁ to the phase detection circuit 133, symbol decoding circuit 145, timing error Output to the detection circuit 163 and the AGC circuit 147. The roll-off filter circuit 224 ₂ outputs the Q signal S13
0b is subjected to filter processing to reduce intersymbol interference to generate a Q signal S224 ₂ , which is
3, output to the symbol decode circuit 145, the timing error detection circuit 163, and the AGC circuit 147. In the present embodiment, the roll-off filter circuit 22
4 ₁ and 224 ₂ are configured in the Costas loop 155, but these are connected to the interpolation circuit 2.
23 _1, 223 ₂ may be installed immediately.

The phase detection circuit 133 outputs the I signal S224 ₁
And the phase determined by the Q signal S224 ₂ and
The phase signal S133 indicating the phase is output to the loop filter circuit 134.

The loop filter circuit 134 generates the phase signal S
The high frequency component 133 is removed to generate a phase signal S134, which is output to the numerically controlled oscillation circuit 135.

The numerically controlled oscillation circuit 135 is a cumulative addition circuit that does not inhibit overflow,
Of the phase signal S134, the signal S135 having an oscillation frequency corresponding to the value of the phase signal S134 is generated, and is output to the signal conversion circuits 136 and 137. That is, the numerically controlled oscillator 135 digitally performs the same operation as the voltage controlled oscillator (VCO) in the analog circuit.

The signal conversion circuit 136 has, for example, a ROM in which a signal having an 8-bit resolution having a SIN characteristic is stored, and a signal S136 having the SIN characteristic read out from the ROM in response to the signal S135 from the numerical control oscillation circuit 135. Output to the complex multiplication circuit 130. The signal conversion circuit 137
For example, it has a ROM storing an 8-bit resolution signal having a COS characteristic, and outputs a COS characteristic signal S137 read from the ROM to the complex multiplying circuit 130 in accordance with a signal S135 from the numerical control oscillation circuit 135.

Here, the Costas loop is formed by the complex multiplication circuit 130, the roll-off filter circuits 131 and 224, the phase detection circuit 133, the loop filter circuit 134, the numerical control oscillation circuit 135, and the signal conversion circuits 136 and 137.
(Costas Loop) A circuit 155 is configured.

The symbol decode circuit 145 demodulates (decodes) the symbols of the carrier reproduced I signal S131 and Q signal S224 input from the roll-off filter circuits 131 and 224 using a predetermined correspondence table. The symbol decoding circuit 145 outputs the result of the decoding process to the subsequent error correction circuit.

[0073] The timing error detection circuit 163, a timing error signal by detecting the timing error of the symbol using the I signal S224 ₁ and Q signal S224 ₂ S
163 is generated. The loop filter circuit 162 generates a timing error signal S162 by removing a noise component from the timing error signal S163 input from the timing error detection circuit 163, and outputs this to the sample timing determination circuit 161. The sample timing determination circuit 161 determines a new sample timing based on the timing error signal S162 input from the loop filter circuit 162 so as to eliminate or suppress the timing error detected by the timing error detection circuit 163. A sample timing determination signal S161 indicating the determined sample timing is output to the interpolation circuits 223 ₁ and 223 ₂ .

The AGC circuit 147 includes the A / D conversion circuit 12
The I signals S224 ₁ and Q224 are processed so that the circuit at the subsequent stage of 0, 121 can perform processing using a stable and appropriate amplitude.
Using the amplitude value of the signal S224 ₂ , the analog amplification circuit 1
A digital gain control signal S 147 for controlling the gains of the gains 15 and 116 is generated with, for example, an 8-bit resolution, and is output to the PWM signal generation circuit 148.

The PWM signal generation circuit 148 converts the digital gain control signal S147 into a gain control signal S148, which is a PWM signal for obtaining an analog signal, and outputs this to the low-pass filter 149. The low-pass filter 149 removes a high-frequency component of the gain control signal S148 to generate an analog gain control signal S149.
This is output to analog amplifier circuits 115 and 116.

The operation of receiving apparatus 90 shown in FIG. 10 will be described below. Received signal S11 received via satellite repeater
The in-phase component of 0 is detected by the in-phase detection circuit 112 using the local oscillation signal S111, and a baseband I signal S112 is generated. At the same time, the quadrature component of the received signal S110 is detected by the quadrature detection circuit 114 using the locally generated signal S113 having a 90-degree phase difference from the local oscillation signal S111, and the baseband Q signal S114 is generated. Is done.

The amplification processing based on the amplification rate control signal S149 in the analog amplification circuit 115 causes the I signal S
An I signal S115 is generated from 112. LPF circuit 1
Through the LPF processing at 18 and the A / D conversion processing at the A / D conversion circuit 120, the I signal S120 is generated from the I signal S115. Next, the I signal S120 changes to H
After being band-limited by BF circuit 220 _1, is down-sampled in a down-sampling circuit 221 _1, I signal S222 ₁ is generated is removed components other than the frequency component of the carrier selecting the prefilter circuit 222 _1.

Next, the interpolation circuit 223 ₁
In, as the symbol decoding circuit 145 perform the determination of the symbol at the right time, the interpolation processing of the I signal S222 ₁ based on the sample timing determination signal S161 is performed I signal S223 ₁ from the sample timing decision circuit 161 Generated.

The following Q signal processing is performed in parallel with the above-described I signal processing. That is, the amplification process based on the amplification factor control signal S149 in the analog amplification circuit 116 causes the Q signal S114 to change to the Q signal S1.
16 is generated. LPF processing in LPF circuit 119, A / D conversion processing in A / D conversion circuit 121, H
Band-limiting process in the BF circuit 220 _2, through the filtering in the down-sampling processing and pre-filter circuit 222 ₂ in the down-sampling circuit 221 _2, Q signal S222 ₂ is generated from the Q signal S116. Next, in the interpolation circuit 223 ₂ , the sample timing determination signal S 16 from the sample timing determination circuit 161 is set so that the symbol decode circuit 145 can determine a symbol at an appropriate timing.
1 to perform Q signal S222 ₂ interpolation processing.
A signal S223 ₂ is generated.

Then, in the Costas loop circuit 155, the frequency pull-in processing and the phase synchronization processing of the I signal S223 ₁ and the Q signal S223 ₂ are performed. In the process, the I signal S224 ₁ and the Q signal S224 ₂ from the roll-off filter circuits 224 ₁ and 224 ₂ are output to the AGC circuit 147. In the AGC circuit 147, a digital amplification factor control signal S147 for controlling the amplification factors of the amplification circuits 115 and 116 is generated with, for example, 8-bit resolution. The digital amplification factor control signal S147 is PWM
The signal generation circuit 148 converts the signal into an amplification factor control signal S148, which is a PWM signal for obtaining an analog signal, and outputs the signal to the low-pass filter 149. 1 When the high-frequency component is removed by the low-pass filter 149, the analog gain control signal S148 becomes the analog gain control signal S148.
149 and output to the amplifier circuits 115 and 116.

[0081] Further, in parallel with the process described above, based on the roll-off filter circuit 224 ₁ and 224 ₂ from the carrier reproduction is input to the timing error detecting circuit 163 I signal S224 ₁ and Q signal S224 _2,
The timing error signal S163 is generated in the timing error detection circuit 163. The timing error signal S163 is output from the timing error signal S16 after the noise component is removed in the loop filter circuit 162.
2 is output to the sample timing determination circuit 161. The sample timing determination circuit 161 determines a new sample timing based on the timing error signal S162 so as to eliminate or suppress the timing error detected by the timing error detection circuit 163, and indicates the determined sample timing. The sample timing determination signal S161 is output to the interpolation circuits 223 ₁ and 223 ₂ .

As described above, according to the receiver 90, the same effects as in the first embodiment can be obtained by providing the pre-filter circuits 222 ₁ and 222 ₂ . As a result, the receiving device 90 has a small device configuration,
It is possible to demodulate a received signal in a wide frequency band from a low bit stream to a high bit stream without deteriorating the BER characteristic, which is particularly effective when processing a received signal of the SCPC system.

The present invention is not limited to the above embodiment. In the above-described embodiment, the HBF circuits 20, 22
0 ₁ , 220 ₂ and down-sampling circuits 21, 221
_Although a case where a single-stage decimator circuit composed of ₁ and 221 ₂ is provided is illustrated, the interpolation circuit 23 and
A plurality of stages of decimator circuits may be provided according to the frequency conversion ratios of 223 ₁ and 223 ₂ . That is, interpolation circuit 23,223 _1, 223 ₂ within the range of convertible frequency, as the frequency of the input signal of the interpolation circuit falls, determines the number of the previous decimator circuit. That is, in the above-described embodiment, the case where the interpolation circuits 23, 223 ₁ , and 223 ₂ convert a frequency that is greater than twice and less than or equal to four times the symbol rate of the selected carrier into a frequency that is twice as large is described. The present invention is also applicable to the case where the frequency is converted from a frequency that is more than twice the symbol rate of the selected carrier to ²ⁿ times (n is an integer of 2 or more) and twice the frequency.

[0084]

As described above, according to the carrier selecting apparatus, the method and the receiving apparatus of the present invention, a carrier component of a predetermined frequency can be selected in a high quality state without being affected by an interference wave. Therefore, demodulation processing can be performed with high accuracy in the subsequent demodulation circuit.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a carrier selection device according to the background art of the present invention.

FIG. 2 is a diagram for explaining an operation of the carrier selection device shown in FIG. 1;

FIG. 3 is a configuration diagram of a carrier selection device according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating an example of a configuration of an HBF circuit illustrated in FIG. 3;

FIG. 5 is a diagram illustrating a filter characteristic of the HBF circuit illustrated in FIG. 4;

FIG. 6 is a diagram illustrating an example of a configuration of a prefilter circuit illustrated in FIG. 3;

FIG. 7 is a diagram illustrating filter characteristics of the pre-filter circuit illustrated in FIG. 6;

FIG. 8 is a diagram illustrating a relationship between a sampling timing of an input signal and a sampling timing of an output signal in the interpolation circuit illustrated in FIG. 3;

FIG. 9 is a diagram for explaining an operation of the carrier selection device shown in FIG. 3;

FIG. 10 is a configuration diagram of a receiving device according to a second embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Carrier wave selection device, 10 ... HBF, 11 ... Down sampling circuit, 12 ... Interpolation circuit, 9 ... Carrier wave selection device, 20 ... HBF circuit, 21 ... Down sampling circuit, 22 ... Pre-filter circuit, 23 ... Interpo 24, a roll-off filter circuit, 25, a down-sampling circuit, 110, an input terminal, 111, a local oscillation circuit, 112, an in-phase detection circuit, 113, a phase shift circuit, 1
14: Quadrature detection circuit, 115, 116: Analog amplifier circuit, 118, 119: LPF circuit, 120, 121 ... A
/ D conversion circuit, 112 oscillation circuit, 133 phase detection circuit, 134 loop filter circuit, 135 numerical control oscillation circuit, 136, 137 signal conversion circuit, 145 symbol decode circuit, 161 sample timing determination circuit, 162: loop filter circuit, 163: timing error detection circuit, 147: AGC circuit, 148: PWM
Signal generation circuit, 149... Low-pass filter, 220 ₁ ,
220 ₂ … HBF circuit, 221 ₁ , 221 ₂ … Dun sample circuit, 222 ₁ , 222 ₂ … Pre-filter circuit, 2
23 ₁ , 223 ₂ ... interpolation circuit, 13
0: complex multiplying circuit, 224 ₁ , 224 ₂ ... roll-off filter circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (reference) H04L 27/22 H04L 27/22 FF term (reference) 5K004 AA05 FA03 FA05 FG02 5K020 AA02 AA05 DD02 FF00 HH11 HH12 HH13 5K022 AA04 AA10 AA24

Claims (11)

[Claims] 1. A carrier selection apparatus for selecting a carrier having a predetermined frequency from a predetermined frequency band, comprising: a first filter circuit for limiting a band of an oversampled signal with respect to the predetermined frequency; A down-sampling circuit for down-sampling the band-limited signal; a second filter circuit for band-limiting the down-sampled signal to remove a frequency component other than a frequency component of the selected carrier; and a second filter. An interpolating circuit for converting the sampling frequency of the signal processed by the circuit from a frequency greater than twice the symbol rate of the selected carrier to 2 ⁿ times (n is an integer of 2 or more) to twice the frequency. Selection device. 2. The method according to claim 1, wherein the signal processed by the second filter circuit has a frequency that is greater than twice the symbol rate of the selected carrier and 2 ⁿ times (n is an integer of 2 or more) or less. 2. The carrier selection device according to claim 1, wherein a plurality of circuit modules each including a first filter circuit and the down-sampling circuit are connected in series. 3. The carrier selection device according to claim 1, wherein the second filter circuit limits a band of the down-sampled signal to remove a carrier other than the selected carrier and a frequency component of the imaging thereof. 4. The carrier selection device according to claim 1, wherein the downsampling circuit downsamples the frequency of the band-limited signal to half. 5. The interpolation circuit according to claim 1, wherein k is a natural number, i is an index, and k · Ti is an output signal y.
, M is an index, the sampling timing of the input signal x is m · Ts, and 0 ≦ μ _k <
1, in the case where hi (t) is the impulse response at time t, performs arithmetic processing of the following formula (1), the index i, m _k and mu _k are respectively the following formulas (2),
It is defined by (3) and (4). (Equation 1) (Equation 2) (Equation 3) (Equation 4) The carrier selection device according to claim 1. 6. The interpolation circuit converts a sampling frequency of a signal output from the second filter circuit from a frequency that is greater than twice and less than or equal to four times the symbol rate of the selected carrier to a frequency that is twice as high. The carrier selection device according to claim 1. 7. The carrier selection apparatus according to claim 1, wherein the first filter circuit performs band limitation of the signal in a system including a plurality of carriers of different frequencies in the predetermined frequency band. 8. A receiving means for receiving a signal including a plurality of carriers having different frequencies within a predetermined frequency band, and an A / A for converting the received signal into a digital signal.
A D conversion circuit; a first filter circuit that limits the band of the signal obtained by the conversion; a downsampling circuit that downsamples the band-limited signal; A second filter circuit for removing a frequency component other than the frequency component of the carrier to be processed; and a sampling frequency of the signal processed by the second filter circuit being more than twice the symbol rate of the selected carrier and 2 ⁿ times ( an interpolating circuit for converting a frequency less than or equal to (n is an integer of 2 or more) to a double frequency. 9. The receiving apparatus according to claim 8, further comprising a demodulation circuit for demodulating the signal converted by said interpolation circuit. 10. The signal processing apparatus according to claim 1, wherein the signal processed by the second filter circuit has a frequency that is more than twice the symbol rate of the selected carrier and 2 ⁿ times (n is an integer of 2 or more) or less. The receiving device according to claim 8, wherein a plurality of circuit modules including the first filter circuit and the down-sampling circuit are connected in series. 11. A carrier selection method for selecting a carrier having a predetermined frequency from a predetermined frequency band, wherein a band of an oversampled signal is limited for the predetermined frequency, and the band-limited signal is down-converted. Sampling, band-limiting the down-sampled signal to remove frequency components other than the frequency component of the selected carrier, and setting the sampling frequency of the signal from which the frequency component has been removed to twice the symbol rate of the selected carrier. A carrier selection method for performing interpolation for converting a frequency larger than 2 ⁿ times (n is an integer of 2 or more) to a double frequency.