JP2001256001A - Disk array device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that an I/O processing function is remarkably lowered when a writing request to cause misalign is made. SOLUTION: An Alignment judging processing part 23 judges whether or not a writing processing of data is Alignment by a logical address to indicate a starting position of writing of the received data and data size. When the Alignment judging processing part 23 judges the processing as Misalign, an Alignment state is set by supplementing invalid data so that the data size of the data becomes integer multiples of a parity calculation block when the data size is not the integer multiples of the parity calculation block by an invalid data supplement processing part 24 and converting the logical address so that the logical address coincides with offset when the logical address does not coincide with the offset of the parity calculation block by an address conversion/ address management processing part 25.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk array device which controls data reading and writing by operating a plurality of disk devices in parallel.

[0002]

2. Description of the Related Art As a conventional technique, for example, Japanese Unexamined Patent Publication No.
There is a technique disclosed in Japanese Patent Publication No. 305328. Less than,
A conventional example will be described with reference to the drawings.

FIG. 13 shows a block diagram of a conventional disk array device.

[0004] When viewed from the host 1301, blocks after the disk array controller 1303 appear as a single disk device via the host adapter 1302. The host 1301 transmits data to the disk array controller 1303 via the host adapter 1302. In this case, the disk array controller 1303 divides the received data into four, transmits each data to the device controllers 1304a to 1304d, generates parity data for the divided data, and transmits the parity data to the device controller 1304e. Device controller 130
4a to 1304d record the received divided data in the data storage disk devices 1305a to 1305d, respectively, and the device controller 24e records the received parity data in the parity data storage disk device 25e.

As described above, the conventional disk array device is
By using multiple disk devices (hard disk devices), a large amount of data can be accessed at high speed, and data redundancy can be realized in the event of a disk failure, resulting in higher reliability and performance than a single disk device Has been realized. This was published in 1987 by David U. of the University of California, Berkeley. A. Patterson (Dav
id.A.Patterson) RAID (Redundan
t Arrays of Inexpensive Disks). That is, RAID is David. A. It is derived from the paper by Professor Patterson and others.

[0006] Disk array RAID is 1 to 5
Up to the level (hereinafter, RAID 1 and R in order from level 1)
AID2, RAID3, RAID4, and RAID5).
Parity data for recovering data in the event of a disk device failure is held. For example, in RAID 3, input data is divided (striped), interleaved and divided data is stored in a plurality of disk devices in a distributed manner. In this case, the disk device that stores the error correction code for the divided data is a redundant disk device, and the data of the redundant disk device is the parity data.

Hereinafter, the flow of data write processing in RAID3 will be described with reference to FIGS. FIG.
FIG. 15 is a detailed block diagram of the disk array controller 1303, and FIG.
13 is a flowchart showing the flow of the process of FIG.

First, the writing process will be described.

The command processing unit 1402 includes a host 1301
Is received (step 150 in FIG. 15).
1) It is determined that the request from the host 1301 is a write request (step 1502 in FIG. 15), and processing necessary for data write processing is performed. Command processing unit 14
02 requests the host 1301 to transmit a logical address indicating a data write start position and data. Host 1
Upon receiving the request from the command processing unit 1402, the command processing unit 301 immediately stores the logical address and data in the command processing unit 1402.
02. The command processing unit 1402 is a host 1
The write request, logical address, and data transmitted from 301 are transmitted to Alignment determination processing unit 1404 via host data reception / transmission processing unit 1403.

Alignment determination processing unit 1404
According to the received logical address and the data size of the data, the processing at the time of data writing is performed according to the following (1) and (2)
It is determined whether or not the condition is satisfied. (Step 1503 in FIG. 15). (1) The data size block is an integral multiple of the minimum unit of one sector (512 bytes) of the hard disk, and is an integral multiple of the parity calculation block (the integral multiple of 512 bytes). (2) The address indicating the data write start position matches the offset which is the alignment boundary of the parity calculation block.

Alignment determination processing unit 1404
States that the above two conditions are satisfied.
t, Missing if any one is not satisfied
n (misalignment). After performing the alignment determination, the alignment determination processing unit 1404 transmits a write request, a logical address, data, and a determination result to the host data division / combination processing unit 1405.

Hereinafter, the Alignment determination processing unit 14
4 KB (1 KB = 1024 bytes) for the processing after 04
An example in which 4 KB fixed-length data is written in the parity calculation block of FIG. In FIG. 16, the parity calculation block is 4 KB,
The parity calculation block is composed of eight data size blocks, and one data size block is 512B (B
yte). Arrows indicate write start positions.

First, the processing when the determination result is Alignment will be described.

FIG. 16A shows an example of the alignment data. Alignment determination processing unit 140
4 indicates that the data of FIG. 16A has a data size of 4 KB (=
512 × 8B), the condition (1) is satisfied, and the write start position is Alignnm of the parity calculation block.
It is determined that the condition (2) is also satisfied because it matches the offset that is the ent boundary, and the alignment is determined.
Is determined. Alignment determination processing unit 14
04 transmits the determination result, the write request, the logical address, and the data to the host data division / combination processing unit 1405.

The host data division / combination processing unit 1405 transmits the received logical address and the determination result to the address designation processing unit 1406, and at the same time, divides the received data and sends it to the address designation processing unit 1406 (step in FIG. 15). 1504). In this case, since four disk devices are connected, the data is divided into four. The address specification processing unit 1406 performs address conversion of the logical address according to the received determination result. In this case, the determination result is Ali
address designation processing unit 14
Reference numeral 06 does not perform an address conversion process on the received logical address, allocates an address only to the parity data, and transmits the received determination result, write request, logical address, parity data address, and data to the parity processing unit 1407. (Step 1505 in FIG. 15).
Here, no parity data exists at this time,
Since the parity data size is a fixed size, only the address is allocated first. Parity processing unit 1407
Creates parity data from the received divided data,
The divided data, parity data, write request, logical address, and parity data address are
5 (step 1506 in FIG. 15). The disk device 1305 records the received divided data and parity data according to the specified address.

Next, the processing when the judgment result is Misalign will be described. In this case, two consecutive 4K
The case where data B, data 1 and data 2 are sequentially written will be described as an example.

First, the process of writing data 1 will be described.

Data 1 is shown in the shaded portion of FIG. As shown in the figure, data 1 is 4 KB data, and the write start position indicated by the arrow is [0001h]. When 4 KB of data is written from the address [0001h], the block [01h] is written as shown in FIG.
Is recorded over block [02h].

Alignment determination processing unit 1404
Since the data 1 has a data size of 4 KB, the condition (1) is satisfied. Since the write start position [0001h] is at the position indicated by the arrow in FIG. 16B, the offset that is the alignment boundary of the parity calculation block is set. Therefore, it is determined that the alignment condition (2) is not satisfied. That is, Alignmen
The t determination processing unit 1404 determines that the write processing of the data 1 is Mi.
It is determined that the data is “align”, and the determination result, the write request, the logical address [0001h], and data 1 are transmitted to the host data division / combination processing unit 1405 (FIG.
Step 1503).

Host data division / combination processing unit 1405
Transmits the received logical address [0001h], the determination result, and the write request to the address designation processing unit 1406, and at the same time, executes division processing of data 1, and then transmits the divided data to the address designation processing unit 1406 ( Step 1507 in FIG. 15). Address designation processing unit 140
No. 6 designates an address (real address) indicating the actual recording destination of the divided data and the parity data from the received logical address [0001h], and holds the logical address and the real address in the address management table (FIG. 15). Step 1508). (Table 1) shows the address designation processing unit 1406
2 shows an address management table held by.

[0021]

[Table 1]

As shown in Table 1, the address management table is composed of a logical address transmitted from the host 1301 and a real address indicating a block number to be actually written to the disk. As shown in (Table 1), the logical address of data 1 is [00001h], the real address,
That is, the block number is [01h].

The address designation processing unit 1406 sends the write request, the real address [01h], the divided data, and the determination result to the parity processing unit 1407. Parity processing unit 14
07 generates parity data from the divided data, and transmits the divided data, the parity data, the write request, and the real address [01h] to the disk device 1305 (FIG. 1).
5, Steps 1509 and 1510). In this case, since data 1 is the first write, and no parity data exists in the parity calculation block to be written, parity data is generated only from the divided data. The disk device 1305 receives the write request,
The division data and the parity data are recorded according to the real address.

Next, the data 2 writing process will be described.

Data 2 is shown in the hatched portion of FIG. As shown in FIG. 16C, data 2 is 4 KB data, the logical address indicating the write start position address is [0009h] indicated by the arrow, and the block [0]
2h] and block [03h].

Alignment determination processing unit 1404
Since the data size of the data 2 is 4 KB, the condition (1) is satisfied, and the write start position [0009h] shown in FIG.
Ali does not match the offset that is the ent boundary.
It is determined that the condition (2) of the G.ment is not satisfied.
Therefore, the Alignment determination processing unit 1404 sets the Mi
It is determined that the data is “align”, and the determination result, the write request, the logical address [0009h], and the data 2 are transmitted to the host data division / combination processing unit 1405 (FIG. 1).
5 step 1503).

Host data division / combination processing unit 1405
Transmits the received logical address [0009h], the determination result, and the write request to the address designation processing unit 1406, and at the same time, executes the division processing of the data 2, and then transmits the divided data to the address designation processing unit 1406 (FIG. 5 step 1507). Address designation processing unit 1406
Specifies the real addresses of the divided data and the parity data from the address management table shown in (Table 1) and the logical address [0009h] of the data 2, and stores the address information in the address management table (step in FIG. 5). 1
508). (Table 2) shows the address management table updated by the address designation processing unit 1406.

[0028]

[Table 2]

As shown in Table 2, following the address information of data 1, the logical address [0009h], which is the address information of data 2, and the block number [02h] of the block where the data 2 write start position is located ] Is stored as the real address.

The address designation processing unit 1406 transmits the judgment result, the real address [02h], the write request, and the divided data to the parity processing unit 1407. The parity processing unit 1407 calculates parity data of the data 2 from the received divided data, the determination result, and the real address [02h]. First, the parity calculation block shown in FIG.
The data A which is a part of the data 1 recorded in [0001h] and the parity data of the parity calculation block [02h] are read (step 1509 in FIG. 5). Next, the parity processing unit 1407 creates parity data from the read data A and the divided data of the data 2 stored in the parity calculation block [02h] (step 1510 in FIG. 5). The parity processing unit 1407 transmits the data A, the divided data of the data 2 stored in the parity calculation block [02h], the newly generated parity data, and the real address [02h] to the disk device 1305. The disk device 1305 records the divided data, the data A, and the parity data of the received data 2 according to the received real address.

The parity processing unit 1407 generates parity data for the remaining divided data of the data 2 recorded in the parity calculation block [03h] and the data existing in the seven data size blocks in which no data is stored. , The write request, the remaining divided data of data 2, the generated parity data, and the real address [03h] are transmitted to the disk device 1305. The disk device 1305 records the received data 2 and parity data according to the real address.

As described above, in the conventional disk array device, the data write processing is Misaligned, and
If there is data already recorded in the parity calculation block to which the data is to be written, the data and the parity data for the data are read, and then the parity data is generated again.

[0033]

However, in the above-mentioned conventional disk array device, the I / O processing is not performed by the Alig.
For a disk array device that exhibits the highest performance at the time of
When processing is performed, Misalign occurs when the fixed data size is not an integral multiple of the parity calculation block size, or when the address indicating the data write start position does not match the offset of the parity calculation block. In some cases, data read processing that is not performed in the case of Alignment is required, which causes a problem that the I / O processing performance is significantly reduced.

The present invention solves the above-mentioned conventional problems, and provides a disk array apparatus which enables subsequent I / O processing to be performed in Alignment with respect to I / O processing in which Misalignment occurs.

[0035]

In order to achieve this object, a disk array device according to the present invention is designed such that when a write request that causes a misalignment is made, the data is complemented or the address is written so that the subsequent data write becomes alignment. It has an alignment processing function for performing conversion.

With this configuration, the disk array device of the present invention, when receiving a write request that causes a Misalignment, writes the subsequent data to the Align
nt.

[0037]

A first aspect of the present invention is a disk array device that performs data processing in accordance with a request from a host, using a predetermined data size as a processing unit, wherein a write start position received from the host is determined. The disk array device having an alignment processing means for converting and storing the conversion information so as to match the alignment boundary of the processing unit, and by making the write start position coincide with the alignment boundary of the parity calculation block, I / O processing can be performed in alignment.

According to a second aspect of the present invention, there is provided a disk array apparatus for performing data processing in accordance with a request from a host using a predetermined data size as a processing unit, wherein the data size of data received from the host is the same as that of the first embodiment. A disk array device having an alignment processing means for adding invalid data independent of the data so as to be an integral multiple of the data size of a processing unit, wherein the data size is set to an integral multiple of a parity calculation block, and Data I / O processing can be performed in alignment.

According to a third aspect of the present invention, there is provided a disk array apparatus for performing data processing in accordance with a request from a host using a predetermined data size as a processing unit, wherein the write start position received from the host is determined by the data processing unit. A disk array device having an alignment processing means for shifting by a predetermined shift value so as to coincide with an alignment boundary of a processing unit, wherein the shift value is set to a value that matches an alignment boundary of an error correction parity calculation block. This allows the I / O processing of the subsequent data to be performed in alignment.

Hereinafter, a disk array device according to the present invention will be described with reference to the accompanying drawings.

(Embodiment 1) In Embodiment 1, Al
A case will be described in which an assignment processing function is provided outside the disk array controller, and a write request generated by Misalign is made an alignment write request.

FIG. 1 is a block diagram showing a configuration of a disk array device according to an embodiment of the present invention.

In FIG. 1, reference numeral 11 denotes a host for instructing I / O processing, 12 a host adapter for controlling a device connected to the host 11, and 13 an Alignment process for data input from the host adapter 12. The Alignment processing unit 14 divides the data input from the Alignment processing unit 13 at the time of writing, generates parity data of the divided data, and integrates the parity check of the data and the divided data into one data at the time of reading. An array controller, 15a to 15e are device controllers for controlling I / O processing of data input from the disk array controller 14, and 16a to 16e are data controllers for performing data I / O processing under the control of the device controllers 15a to 15e, respectively. It is a disk apparatus.

The disk array device configured as described above will be described with reference to the drawings.

The host 11 sends a write request and a data write start position (hereinafter referred to as a “write start position”) via the host adapter 12.
Logical address), and Alignm
This is transmitted to the nt determination processing unit 13. The Alignment determination processing unit 13 receives a write request from the host 11, and determines whether the data write process is an Alignment from the logical address and the data of the received data.

Hereinafter, a detailed operation of the alignment processing unit 13 will be described with reference to FIGS. Figure 2 shows Ali
FIG. 3 is a block diagram illustrating a detailed configuration of the alignment processing unit 13, and FIG. 3 is a flowchart illustrating processing of the alignment processing unit 13.

In FIG. 2, reference numeral 21 denotes a command processing unit for processing a command received from the host 11, and 22 receives data output from the command processing unit 21 and aligns the received data with the data write process.
host data reception / transmission processing unit for transmitting to the Alignment determination processing unit 23 for performing nt determination;
The invalid data complementing processing unit that complements the invalid data output from the alignment determination processing unit 23 according to the determination result output from the alignment determination processing unit 23, and the invalid data complement processing unit 25 according to the determination result output from the alignment determination processing unit 23. To convert the logical address of the data output from the invalid data complement processing unit 24 into a real address,
An address conversion / address management processing unit that manages both addresses.

The command processing unit 21 determines whether the access request transmitted from the host 11 is a write process or a read process. In the case of write processing, the respective processing is performed in the remaining four processing blocks according to the procedure. In the case of read processing, the processing is not performed in the four processing blocks, and the data received from the host 11 is transmitted to the disk array controller 14. You. (Steps 301 to 302 in FIG. 3).

Hereinafter, a case where the request from the host 11 is a write processing request will be described.

The command processing section 21 transmits a write request, a logical address, and data input from the host 11 to the Alignnm via the host data reception / transmission processing section 22.
ent determination processing unit 23.

The Alignment determination processing unit 23 transmits the received data to the invalid data complement processing unit 24 and, at the same time, determines whether the data write processing is Alignment based on the received logical address and the data size of the data. The determination result is transmitted to the invalid data complement processing unit 24 (Step 303 in FIG. 3).

Here, "Alignment" indicates a state satisfying the following conditions (1) and (2). (1) The data size block is an integral multiple of the minimum unit 1 sector (512B) of the hard disk and an integral multiple of the parity calculation block (the integral multiple size of 512B). (2) The address indicating the data write start position matches the offset that is the alignment boundary of the parity calculation block.

A state in which any one of the two conditions is not satisfied is defined as Misalign.

If the alignment is determined by the alignment determination unit 23 to be alignment, no processing is performed in the remaining two processing blocks, and the received data is used as is in the disk array controller 1.
4 is transmitted. If it is determined to be Misalign, processing is performed in the remaining two processing blocks according to the state of Misalign.

The invalid data complement processing unit 24 is provided with an Align
If the data satisfies the condition (1) based on the determination result transmitted from the ment determination processing unit 23, the write request, the data, the logical address, and the determination result are immediately converted to the address conversion / address management processing unit 25. Send to When the data does not satisfy the condition (1), that is, when the data is in the Misaligned state, the invalid data complement processing unit 24 complements the data with invalid data,
Processing is performed so as to be an integral multiple of the parity calculation block, and an access request, new data to which invalid data is added, a logical address, and a determination result are transmitted to the address conversion / address management processing unit 25 (step 304 in FIG. 3) ~ Step 305).

Address conversion / address management processing unit 25
When the received data satisfies the condition (2) from the received determination result, the write request, the data, the logical address, and the data are immediately transmitted to the disk array controller 14 and, at the same time, the data is retained from the logical address. Update the address management table that was used.
If the condition (2) is not satisfied, a real address for changing the data write start position to the offset of the parity calculation block next to the parity calculation block to be written is allocated. The address conversion / address management processing unit 25 has an address management table for managing address information indicating the correspondence between the logical address and the virtual address (steps 306 to 309 in FIG. 3).

The processing of the alignment determination processing unit 23, invalid data complement processing unit 24, and address conversion / address management processing unit 25 in the three cases of the Missing state will be described in detail below.

First, Mis not satisfying only the condition (1)
The case of the algin state will be described.

An example of the data in this case is shown in a shaded portion in FIG. In FIG. 4, the parity calculation block size as a processing unit is 4 KB, and the size of each data block in the parity calculation block is 512 B
It is. 4A is a logical address [00].
00h], and the data size is 6 KB.

The Alignment determination processing unit 23 immediately transmits the received data to the invalid data complement processing unit 24, and at the same time, determines whether the data write processing is Alignment based on the received logical address and data size. Alignment determination processing unit 2
3 is that the logical address [0000h] matches the block number [00h] indicating the offset value of the parity calculation block, but since the data size 6 KB is not a multiple of 4 KB of the parity calculation block size, the condition (1) The determination result A of Misaligning that does not satisfy only
The data is transmitted to the invalid data complement processing unit 24.

The invalid data complementing processing unit 24
judgment result A transmitted from the ment judgment processing unit 23
Accordingly, it is determined that the misalignment does not satisfy the condition (1), and 2 KB of invalid data is complemented and written so that the 6 KB data shown in FIG. 4A becomes the least common multiple of 8 KB of the parity calculation block 4 KB. Request, 8 KB data with invalid data added, logical address [00]
00h], and transmits the determination result A to the address conversion / address management processing unit 24. FIG. 4B shows 8 KB data to which invalid data has been added. As shown in the figure,
The data in FIG. 4B is data that is an integral multiple (2 times) of the parity calculation block by supplementing the data in FIG. 4A with 2 KB of invalid data indicated by hatching.

Address conversion / address management processing unit 25
Determines from the received determination result A that the condition (2) is satisfied, and immediately, determines that the write request, 8 KB data,
The logical address [0000h] is transmitted to the disk array controller 14 at the same time as the logical address [0000h].
Then, real addresses are assigned and the address management table held is updated. (Table 3) shows an address management table held by the address conversion / address management processing unit 25.

[0063]

[Table 3]

As shown in (Table 3), the address management table is composed of data logical addresses and real addresses. As shown in (Table 3), since the data received from the determination result A satisfies the condition (2), the logical address [0000h] matches the real address [00h].

Next, Mis which does not satisfy only the condition (2)
The case of align will be described.

An example of the data in this case is shown in a shaded portion in FIG. In FIG. 5, the parity calculation block size as a processing unit is 4 KB, and the size of each data block in the parity calculation block is 512 B. The data size of FIG. 5A is 4K.
B, data whose logical address is [0001h].

The Alignment determination processing unit 23 immediately transmits the received data to the invalid data complementing processing unit 24, and in accordance with the received logical address and the data size of the data, the Alignment processing unit 23
It is determined whether or not t. The Alignment determination processing unit 23 determines that the data size 4 KB is an integer multiple of the parity calculation block size 4 KB,
Since [0001h] does not match the block number [00h] indicating the offset value of the parity calculation block, the determination result B of the Misaligned state that does not satisfy only the condition (2) is transmitted to the invalid data complement processing unit 24. I do.

The invalid data complementing processing unit 24
Based on the determination result B transmitted from the ment determination processing unit 23, it is determined that the received data satisfies the condition (1), so that it is not necessary to perform the complementing process, and the transmitted write request, data, and logical address [ 0001h] and the determination result B to the address conversion / address management processing unit 24.

Address conversion / address management processing unit 25
Determines from the received determination result B that the received data does not satisfy the condition (2), and performs address conversion on the received logical address. The address conversion / address management processing unit 25 stores the logical address of the received data.
In order to shift [0001h] to the block number [01h] indicating the offset value of the parity calculation block next to the parity calculation block [00h] to be written, seven data are added to the logical address [0001h]. Real address shifted by size block [0008h]
And the translation information is held in the address management table.

Table 4 shows an address management table held by the address conversion / address management processing unit 25.

[0071]

[Table 4]

As shown in (Table 4), the real address corresponding to the logical address [0001h] of data 1 is [00
08h] is assigned.

After updating the address management table, the address conversion / address management processing unit 25 sends a write request, data, and information on the real address [0008h] to the disk array controller 14.

Finally, the case of the Misalgin state which does not satisfy the conditions (1) and (2) will be described.

An example of the data in this case is shown in a shaded portion in FIG. In FIG. 6, the parity calculation block size as a processing unit is 4 KB, and the size of each block in the parity calculation block as a processing unit is 512B. The data in FIG. 6A is data having a logical address [0001h] and a data size of 6 KB.

The Alignment determination processing unit 23 immediately transmits the received data to the invalid data complementing processing unit 24, and at the same time, based on the received logical address [0001h] and the data size of the data, the data writing processing is performed in the Al.
It is determined whether or not the current item is an image identification. Align
Since the data size 6 KB is not a multiple of 4 KB of the parity calculation block size and does not match the logical address [0001h] and the block number [00h] indicating the offset value of the parity calculation block, Misali that does not satisfy (1) and (2)
gn as the invalid data complement processing unit 2
Send to 4.

The invalid data complement processing unit 24
judgment result C transmitted from the ment judgment processing unit 23
From the above, it is determined that the misaligned state does not satisfy the condition (1), and 2 KB of invalid data is complemented such that the 6 KB data shown in FIG. 6A is the least common multiple of 8 KB with the parity calculation block 4 KB, A write request, new 8 KB data to which invalid data is added, a logical address [0001h], and a determination result C are transmitted to the address conversion / address management processing unit 25. FIG. 6B shows 8 KB data to which invalid data has been added. As shown in the figure, the data of FIG. 6B is supplemented with the data of FIG. 6A by 2 KB of invalid data indicated by hatching.
The data is an integral multiple (twice) of the parity calculation block.

Address conversion / address management processing unit 25
Determines from the received determination result C that the received data does not satisfy the condition (2), and performs address conversion on the received logical address. The address conversion / address management processing unit 25 stores the logical address of the received data.
To shift [0001h] to the block number [01h] indicating the offset value of the parity calculation block next to the parity calculation block [00h] to be written, seven data are added to the logical address [0001h]. The real address [0008h] shifted by the size block is assigned, and the conversion information is held in the address management table.

Table 5 shows an address management table held by the address conversion / address management processing unit 25.

[0080]

[Table 5]

As shown in (Table 5), the logical address [0
001h] is described as conversion information indicating that [0008h] is assigned as a real address.

After the address conversion / address management processing section 25 completes the update of the address management table, the address
The data of the KB and the information of the real address [0008h] are transmitted to the disk array controller 14.

The disk array controller 14 divides the received data, generates parity data from the divided data, and transmits the real address, the divided data, the parity data, and the write request to the device controller 15a.
~ 15e. In this case, since four disk devices are connected, the disk array controller divides the data into four. The device controllers 15a to 15d record the divided data in the disk devices 16a to 16d according to the received real addresses, and
e causes the disk device 16e to record the parity data.

Hereinafter, the case of the reading process will be described.

The disk array controller 14 receives the read request and the logical address of the host 11 transmitted via the host adapter 12 and the alignment determination processing unit 13, and the received logical address is held by the address conversion / address management processing unit 25. The address is converted to a real address by referring to the address management table. (Step 310 in FIG. 3).

Table 3 shows an address management table held by the address conversion / address management processing unit 25.
The disk array controller 14 obtains the real address [0008h] corresponding to the logical address [0001h] from the address management table of (Table 3), and sends a read request and the real address [0008h] to the device controllers 15a to 15e.
The device controllers 15a to 15e read the divided data and parity data recorded in the disk devices 16a to 16e according to the received real addresses, and transmit the data to the disk array controller 14. The disk array controller 14 performs a parity check on the received parity data, combines the divided data,
alignment determination processing unit 13, host adapter 12
The read data is transmitted to the host 11 via the.

(Embodiment 2) In Embodiment 2, Al
A case will be described in which an assignment processing function is provided inside the disk array controller, and a write request in which a misalignment occurs is made an alignment write request.

FIG. 7 is a block diagram showing a configuration of a disk array device according to an embodiment of the second invention of the present invention.

In FIG. 7, reference numeral 71 denotes a host for instructing I / O processing; 72, a host adapter for controlling a device connected to the host 71; 73, an alignment process for data input from the host adapter 72 at the time of writing; Thereafter, the disk array controller 74 divides the data, generates parity data of the divided data, performs a parity check at the time of reading, and combines the divided data, and 74a to 74e are disk array controllers 73.
The device controllers 75a to 75e for controlling the I / O processing of the input data are controlled by the device controllers 74a to 74e.
This is a disk device that performs processing.

The disk array device configured as described above will be described with reference to the drawings.

The host 71 transmits a write request, a logical address of data, and data to the disk array controller 73 via the host adapter 72. The disk array controller 73 adds Ali to the received data.
Gnent processing, division processing and the like are performed.

Hereinafter, the processing of the disk array controller 73 will be described in detail with reference to FIGS. FIG. 8 is a detailed block diagram of the disk array controller 73, and FIG.
9 is a flowchart showing the processing of the disk array controller 73.

In FIG. 8, reference numeral 81 denotes a command processing unit for processing a command received from the host 71, and 82 receives data output from the command processing unit 81 and performs an alignment determination on the data write processing.
a host data reception / transmission processing unit for transmitting to the alignment determination processing unit 83; 84, a host data division / combination processing unit for dividing the data output from the alignment determination processing unit 83; and 85, an output from the alignment determination processing unit 83 An invalid data complementing processing unit that complements the divided data with invalid data according to the determination result.
an address conversion / address management processing unit that converts a logical address of the data output from the invalid data complement processing unit 85 into a real address according to the determination result output from the identification determination processing unit 83, and manages both addresses; 8
A parity processing unit 7 generates parity data for the data output from the address conversion / management processing unit 86.

Hereinafter, the case of the writing process will be described.

The command processing unit 81 determines whether the access request transmitted from the host 71 is a write process or a read process, and transmits the determination result and the data received from the host 71 to the host data reception / transmission process. It is transmitted to the Alignment determination processing unit 83 via the unit 82 (steps 901 to 902 in FIG. 9).

The Alignment determination processing unit 83 determines whether or not the data write processing is Alignment based on the received logical address and the data size of the data, and determines the host data division / combination processing unit together with the received data. 84 (step 9 in FIG. 9).
03).

Here, the Alignment state indicates a case where the following conditions (1) and (2) are satisfied. (1) The data size block is an integral multiple of the minimum unit 1 sector (512B) of the hard disk and an integral multiple of the parity calculation block (the integral multiple size of 512B). (2) The address indicating the data write start position matches the offset that is the alignment boundary of the parity calculation block.

A state in which any one of the two conditions is not satisfied is defined as Misalign.

When the alignment determination processing unit 83 determines that the write processing of the received data is the alignment, the alignment determination processing unit 83 transmits the received data and the determination result to the host data division / integration processing unit 84.

The host data division / combination processing unit 84 performs division processing on the received data in units of parity calculation blocks (step 904 in FIG. 9), and transmits the determination result and the divided data to the invalid data complement processing unit 85. I do. The invalid data complement processing unit 85 determines that the data satisfies the condition (1) based on the received determination result, and transmits the received data to the address conversion / translation processing unit 86 as it is (step 905 in FIG. 9). The address translation / management processing unit 86
It is determined from the received determination result that the data satisfies the condition (2) (step 907 in FIG. 9), and the received data is transmitted to the parity processing unit 87 (step 90 in FIG. 9).
9). When the determination result is Alignment, FIG.
The address conversion shown in step 909 is not performed.
The parity processing unit 87 generates parity data from the received data (step 910 in FIG. 9),
The divided data, the parity data, and the logical address are transmitted to the device controllers 74a to 74e.

Hereinafter, the processing of each processing unit in the three cases of the Misalign state will be described in detail.

First, Mis not satisfying only the condition (1)
The case of the algin state will be described.

An example of the data in this case is shown in FIG.
Is shown in the shaded area. In FIG. 10, the parity calculation block size as a processing unit is 4 KB, and the size of each block in the parity calculation block is 512 B. The data in (a) of FIG.
00h], and the data size is 6 KB.

The Alignment determination processing section 83 determines whether the data write processing is Alignment based on the received logical address and data size (step 903 in FIG. 9). In the alignment determination processing 83, since the logical address [0000h] matches the block number [00h] indicating the offset value of the parity calculation block, since the data size 6 KB is not a multiple of 4 KB of the parity calculation block size, the condition A data, a logical address, and a write request are transmitted to the host data division / combination processing unit 84 together with the determination result A of Missing that does not satisfy (1).

The host data division / combination processing unit 84 divides the received data into 4 KB parity calculation blocks, and transmits the determination result A, the write request, the logical address, and the divided data to the invalid data complement processing unit 85. (Step 904 in FIG. 9). In this case, since four disk devices for data are prepared, the host data division / combination processing unit 84 divides the data into four.

The invalid data complementing processing unit 85 determines from the determination result A transmitted from the host data dividing / combining processing 84 that the misalignment does not satisfy the condition (1), and is shown in FIG. 10A. 2 so that 6 KB of data is the least common multiple of the parity calculation block.
A write request, 8 KB data to which invalid data is added, and a logical address [0000] supplementing the invalid data of KB.
h], and transmits the determination result A to the address translation / address management processing unit 86 (steps 905 and 90 in FIG. 9).
6). 8 KB with invalid data added to (b) in FIG.
The data of is shown. As shown in the figure, the data of FIG. 10B is the same as the data of FIG.
Is complemented by invalid data, the data becomes an integer multiple (twice) of the parity calculation block.

Address conversion / address management processing unit 86
Determines from the received determination result A that the condition (2) is satisfied, immediately transmits the write request, the divided data complementing the invalid data, and the logical address [0000h] to the parity processing unit 87, and simultaneously Address [000
[0h], real addresses are assigned, and the address management table held is updated (steps 907 and 909 in FIG. 9). (Table 4)
5 shows an address management table held by the address management processing unit 86.

[0108]

[Table 6]

As shown in (Table 6), the address management table is composed of data logical addresses and real addresses. In this case, since the data received from the determination result A satisfies the condition (2), the logical address and the real address match.

After the updating of the address management table is completed, the address conversion / address management processing unit 86 transmits a write request, divided data, and information on the real address [0000h] to the parity processing unit 87.

The parity processing section 87 generates parity data from the received data, and transmits a write request, data, parity data, and a real address to the device controllers 74a to 74e (step 910 in FIG. 9).

Next, Mis which does not satisfy only the condition (2)
The case of align will be described.

An example of the data in this case is shown in FIG.
Is shown in the shaded area. In FIG. 11, one block indicates a data size block of 512B, and the data of FIG.
B, data whose logical address is [0001h].

The Alignment determination processing unit 83 immediately converts the received data into the host data division / combination processing unit 8.
4, the data writing process is performed based on the received logical address and data size.
t is determined (step 90 in FIG. 9).
3). The Alignment determination processing unit 83 determines that the data size 4 KB is an integer multiple of the parity calculation block size of 4 KB, but the logical address [0001h] and the block number [00h] indicating the offset value of the parity calculation block.
Are not coincident with each other, the determination result B indicating the Missing state that does not satisfy only the condition (2) is transmitted to the host data division / combination processing unit 84.

The host data division / combination processing unit 84 divides the received data into 4 KB parity calculation blocks, and sends the invalid data complement processing unit 85 the judgment result A, the write request, the logical address [0001h], and The data is transmitted (step 904 in FIG. 9). In this case, since four disk devices for data are prepared, the host data division / combination processing unit 84 divides the data into four.

The invalid data complement processing unit 85 determines the determination result B transmitted from the host data division / combination processing unit 84.
Therefore, it is determined that the received data satisfies the condition (1), and thus it is not necessary to perform the complementing process. (Step 905 in FIG. 9).

Address conversion / address management processing unit 86
Determines from the received determination result B that the received data does not satisfy the condition (2), and performs address conversion on the received logical address. The address conversion / address management processing unit 86 calculates the logical address of the received data.
In order to shift [0001h] to the block number [01h] indicating the offset value of the parity calculation block next to the parity calculation block [00h] to be written, seven data are added to the logical address [0001h]. Real address shifted by size block [0008h]
And the translation information is held in the address management table (steps 907 to 90 in FIG. 9).
9).

Table 7 shows an address management table held by the address conversion / address management processing unit 86.

[0119]

[Table 7]

As shown in (Table 7), [000] is set as the real address corresponding to the logical address [0001h] of the data.
8h] is described. After the update of the address management table is completed, the address conversion / address management processing unit 86 transmits the write request, the divided data, and the information of the real address [0008h] to the parity processing unit 8.
7

The parity processing section 87 generates parity data from the received data, and transmits a write request, data, parity data, and a real address to the device controllers 74a to 74e (step 910 in FIG. 9).

Finally, the case of the Misalgin state which does not satisfy the conditions (1) and (2) will be described.

An example of the data in this case is shown in FIG.
Is shown in the shaded area. In FIG. 12, the parity calculation block size as a processing unit is 4 KB, and the size of each block in the parity calculation block is 512 B. The data in (a) of FIG.
01h], and the data size is 4 KB.

The Alignment determination processing unit 83 immediately converts the received data into the host data division / combination processing unit 8.
4, the data writing process is performed based on the received logical address and data size.
t is determined (step 90 in FIG. 9).
3). The Alignment determination processing unit 83 determines that the data size is not a multiple of 4 KB of the parity calculation block size and does not match the logical address [0001h] and the block number [00h] indicating the offset value of the parity calculation block. M that does not satisfy 1) and (2)
The determination result C indicating that the command is isalign is transmitted to the host data division / combination processing unit 84.

The host data division / combination processing unit 84 divides the received data into 4 KB parity calculation blocks, and sends the invalid data complement processing unit 85 the judgment result A, the write request, the logical address [0001h], and the division The data is transmitted (step 904 in FIG. 9). In this case, since four disk devices for data are prepared, the host data division / combination processing unit 84 divides the data into four.

The invalid data complement processing unit 85 determines the judgment result C transmitted from the host data division / combination processing unit 84.
From the above, it is determined that the misaligned state does not satisfy the condition (1), and 2 KB of invalid data is complemented so that the 6 KB data shown in FIG. 12A becomes the least common multiple of the parity calculation block, After performing processing to indicate that the data is invalid data, the write request, the divided data to which the invalid data has been added, the logical address [0001h], and the determination result C are converted to an address conversion / address management processing unit 8.
6 (steps 905 and 90 in FIG. 9).
6). 8 KB with invalid data added to (b) of FIG.
The data of is shown. As shown in FIG. 12, the data shown in FIG. 12B is obtained by complementing the data shown in FIG. 6A with invalid data indicated by hatching, so that the data is an integer multiple (twice) of the parity calculation block. It has become.

Address conversion / address management processing unit 86
Determines from the received determination result C that the received data does not satisfy the condition (2), and performs address conversion on the received logical address (step 90 in FIG. 9).
7, step 908). The address translation / address management processing unit 86 stores the logical address [0001
h] is shifted to the block number [01h] indicating the offset value of the parity calculation block next to the parity calculation block [00h] to which writing is to be performed. The virtual address [0008h] shifted by the block is assigned, and the conversion information is held in the address management table (step 909 in FIG. 9).

Table 8 shows an address management table held by the address conversion / address management processing unit 86.

[0129]

[Table 8]

As shown in (Table 8), the logical address [0001h] of the data is [0008] as the real address.
h] is described. After updating the address management table, the address conversion / address management processing unit 86 transmits the write request, the divided data, and the information of the real address [0008h] to the parity processing unit 87.

The parity processing section 87 generates parity data from the received divided data, and transmits the write request, the divided data, the parity data, and the real address to the device controllers 74a to 74e (step 9 in FIG. 9).
10).

The device controllers 74a to 74d record the divided data in the disk devices 74a to 74d in accordance with the received real addresses, and
e causes the parity data to be recorded in the disk device 74e.

Hereinafter, the case of the reading process will be described.

The disk array controller 73 receives the read request and the logical address of the host 71 transmitted via the host adapter 72, and converts the received logical address into an address management table held by the address translation / address management processing unit 86. And convert it to a real address.
(Step 911 in FIG. 9).

Table 8 shows an address management table held by the address conversion / address management processing unit 86.
The disk array controller 73 obtains the real address [0008h] corresponding to the logical address [0001h] from the address management table of (Table 8), and sends a read request and the real address [0008h] to the device controllers 74a to 74e.
The device controllers 74a to 74e read the divided data and parity data recorded in the disk devices 75a to 75e according to the received real addresses, and transmit the data to the disk array controller 73. The disk array controller 73 performs a parity check on the received parity data, combines the divided data, and transmits the read data to the host 71 via the host adapter 72.

In the present invention, when Misalign does not satisfy the condition (1), the address conversion / address management unit sets the write start position of the next data by the address translation / address management unit without complementing the invalid data. Operationally, by matching the offset of the parity calculation block next to the last parity calculation block of data, A
Processing similar to the alignment state (pseudo Align
ment) can be realized.

Further, in the present invention, when Misalign does not satisfy both of the conditions (1) and (2), the address conversion / management processing section sets the data to be recorded for the first time as the address indicating the data write start position. However, since the data does not match the offset of the parity calculation block, the data write start position is changed to the offset of the parity calculation block next to the parity calculation block for which data was to be written, and the write start position of the next data is changed. Is consistent with the offset of the parity calculation block next to the last parity calculation block of the previously written data.
Processing similar to the ent state (pseudo Alignment)
Can be realized.

In the present invention, an invalid data complement processing unit and an address conversion /
Although the management processing unit is provided, if there is a precondition that always satisfies either the condition (1) or (2), it is not always necessary to provide both processes.

Further, in the present invention, the case where an address management table for performing address management is provided as a method of address conversion, but when a fixed-length address is shifted, address conversion is performed using a register or the like. The same effect can be obtained even when it is implemented.

In the present invention, the parity calculation block size serving as a processing unit has been described as 4 KB, but the present invention is not limited to this, and may be any integer multiple of 512 B.

In the present invention, the logical address and the corresponding real address are described in the address management table, but the present invention is not limited to this.

[0142]

As is apparent from the above description, according to the disk array system of the present invention, when there is a write request in which Misalignment occurs, data complement and address can be performed so that subsequent data can be written by Alignment. By having the alignment processing function for performing the conversion, the subsequent I / O processing can be performed in the alignment, and the same performance as in the alignment state can be exhibited.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a disk array device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of the Alignment processing unit.

FIG. 3 is a flowchart for explaining the operation of the Alignment processing unit;

FIG. 4 is a view for explaining an example of the invalid data complementing process.

FIG. 5 is a view for explaining an example of the address conversion process.

FIG. 6 is a view for explaining an example of the invalid data complementing process and the address conversion process;

FIG. 7 is a block diagram illustrating a configuration of a disk array device according to a second embodiment of the present invention.

FIG. 8 is a block diagram showing a detailed configuration of the Alignment processing unit.

FIG. 9 is a flowchart for explaining the operation of the Alignment processing unit;

FIG. 10 is a view for explaining an example of the invalid data complementing process.

FIG. 11 is a view for explaining an example of the address conversion process.

FIG. 12 is a diagram illustrating an example of the invalid data complementing process and the address conversion process.

FIG. 13 is a block diagram showing the configuration of a conventional disk array device.

FIG. 14 is a block diagram showing a detailed configuration of a conventional disk array controller.

FIG. 15 is a flowchart illustrating the operation of a conventional disk array controller.

FIG. 16 is a diagram illustrating a write process of a conventional disk array device.

[Explanation of symbols]

11, 71 Host 12, 72 Host Adapter 13 Alignment Processing Unit 14 73 Disk Array Controller 15a to 15e, 74a to 74e Device Controller 16a to 16e, 75a to 75e Disk Device

Claims (5)

[Claims] 1. A disk array device for controlling writing and reading of data from a host using a plurality of disk devices, wherein a request for writing a data comprising a data write start address and data from the host is provided. Receiving the data and dividing the data into data blocks of a predetermined data size and writing the data to a plurality of disk devices, the write start address matches a block number indicating an offset value of the data block to which the data is to be written Determine whether or not, if they do not match, shift the write start address of the data to match the block number indicating the offset value of the data block located next to the data block to be written data, Update the write start address, Alignment processing means for storing update information of a write start address; and controlling to divide the data for each data size of the data block from the write start address updated by the alignment processing means and to write the divided data to the plurality of disk devices. A disk array device having a disk array controller. 2. A disk array device that controls writing and reading of data from a host using a plurality of disk devices, and receives a write request including a data write start address and data from the host, When dividing the data into data blocks of a predetermined data size and writing the data to a plurality of disk devices, it is determined whether the data size of the data is an integral multiple of the data size of the data block. If not, alignment processing means for adding invalid data independent of the data to the data so that the data size of the data is an integral multiple of the data size of the data block; and invalid data by the alignment processing means. Is added to the write start address. A disk controller for controlling the data to be written to the plurality of disk devices by dividing the data block into data sizes of the data blocks. 3. A disk array device that controls writing and reading of data from a host using a plurality of disk devices, and receives a write request including a data write start address and data from the host, When the data is divided into data blocks of a predetermined data size and written to a plurality of disk devices, the write start address is a block number indicating the write start address and an offset value of a data block to be written with the data. Alignment processing means for updating the write start address by shifting by a predetermined shift amount so as to match the data size of the data block from the write start address updated by the alignment processing means And a disk array controller for controlling writing to the plurality of disk devices by dividing the disk array into a plurality of disk devices. 4. A disk array controller having a function of an alignment processing means.
Disk array device. 5. The disk array controller is a RAID
5. The disk array device according to claim 4, wherein the disk array device is a controller.