JP2001255859A - Flat display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flat display device capable of preventing degradation of display characteristics due to the DC drive of a display panel caused by the abnormality of a signal which is to be supplied from a display control part or the like. SOLUTION: Signal management control parts 471 to 47n of respective scanning drivers LSIs are cascaded and they have the same constitution. The signal to be detected of the control part 471 is a data signal latching clock LP which is to be impressed on a terminal CKB1 and the signal to be detected of the control part 472 is a frame starting signal SP which is to be impressed on a terminal CKB2 and the signal to be detected of the control part 47n is an alternating clock FR which is to be impressed on a terminal CKBn. The control part 471 has a sequence processing circuit 51 consisting of a signal stoppage detecting circuit 48 detecting the stoppage of the signal to be detected of the part 471, a signal delaying circuit 49 and a logical circuit 50. When the oscillation of the signal SP is stopped, outputs T1 to Tn of the circuit 51 are changed to L levels and a display-off signal, the inverse of DF becomes to be in an L level and a liquid crystal panel is forcibly set into a display-off mode. Thus, even when the signal SP is stopped by some cause, since a liquid crystal application voltage is dropped to zero, the DC drive of liquid crystal is avoided and the degradation or the like of liquid crystal are prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display (LC).
D), a flat display such as a plasma display panel (PDP) and an application device thereof, and more particularly, in a flat display device having a form in which a display module unit and a display control unit for controlling the display are separately arranged. The present invention relates to a signal management technique on the display module side.

[0002]

2. Description of the Related Art Conventionally, portable personal computers and word processors, which are generally called laptops, generally have an openable and closable flat display unit. As shown in FIG. 9, a liquid crystal display control unit 10 built in the apparatus main body and a flat liquid crystal display module unit 20 provided inside the opening / closing lid are separate and independent arrangements. The liquid crystal display controller 10 has a liquid crystal module controller 12 and a microprocessor unit (MPU) (not shown). The liquid crystal module controller 12 sends various control signals and clocks to the liquid crystal display module 20 side. Supply signal.

The liquid crystal display module section 20 includes, for example, a liquid crystal display panel (matrix liquid crystal display element) 22 of a simple matrix type and a TA in a peripheral (frame) area of the panel 22.
It has a signal electrode drive circuit (X driver) 24 and a scan electrode drive circuit (Y driver) 26 mounted in B, and a liquid crystal power supply circuit 28 for generating high liquid crystal drive voltages (reference voltages) V _{0 to} V _5. ing. The signal electrode drive circuit 24 includes a plurality of signal electrode driver semiconductor integrated circuits 24 _{1 to} 24 _m.
For example, a driver output is supplied for each line of a screen to a total of M signal electrodes. That is, the data signals D0 to D7 are sequentially taken into the shift register in the signal electrode drive circuit 24 by the pixel clock (shift clock pulse) XSCL, and when the signal (M bits) for one line of the screen is taken, scanning is performed. Line synchronization signal YSCL (data signal latch clock LP)
As a result, the data signal in the shift register is sent in parallel to the data latch circuit, and the data signal is subjected to serial / parallel conversion. In the data latch circuit, the signal voltage for one line is held for one scanning period, and based on the signal voltage, the selection switch circuit sets the driver output voltage connected to the signal electrode to either a selected or non-selected state. I do. The AC conversion clock FR is a clock that converts the above-described voltages into AC waveforms in order to prevent the liquid crystal element from being deteriorated due to DC driving. The forced blank display signal DF (bar) is a signal for forcibly bringing the liquid crystal screen into a blank display state. The scan electrode drive circuit 26 is configured as a cascade connection of a plurality of scan electrode driver semiconductor integrated circuits 26 _{1 to} 26 _n . For example, the selection voltage is applied to only one of the total N scan electrodes, and the other (N−1) Operate to apply a non-selection voltage to the scan electrodes. One scanning line period is started by the scanning start pulse (frame start signal) SP, and every time the scanning line synchronizing signal YSCL (data signal latch clock LP) is received, the selection voltage is changed from the first scanning electrode to the Nth row. It is successively applied to the scanning electrodes of the eyes (line order display). The liquid crystal power source circuit 28 disposed on the liquid crystal display module unit 20 side so as to generate a plurality of liquid crystal driving voltages V ₀ ~V ₅ to select the selection switch of the signal electrode driving circuit 24 and the scanning electrode driving circuit 26, The power is turned on / off by the forced blank display signal DF (bar).

[0004]

By the way, the liquid crystal display control section 10 built in the apparatus main body and the flat liquid crystal display module section 20 provided inside the opening / closing lid are generally connected via a hinge-coupled movable section. Are connected by a flexible cable 30. Therefore, each time the opening / closing lid on the side of the flat liquid crystal display module unit 20 is opened / closed, the cable 30 itself is bent, and the signal line of the cable 30 is likely to be damaged or broken due to physical factors. If a part of the signal line is broken, for example, the AC drive is not performed in a state where the DC voltage (DC component) is applied to the liquid crystal display panel 22, and it is expensive and difficult to replace as compared with other parts. The liquid crystal display panel 22 may be deteriorated. Such deterioration of the liquid crystal is a factor that hinders the life and display quality, and is an important problem for a display device based on visibility.

Here, the liquid crystal module controller 1
Among the signals supplied from the second to the liquid crystal display module unit 20 side, the signals that may cause the DC drive deterioration of the liquid crystal display panel 22 include a scan start pulse SP, a scan line synchronization signal YSCL (data signal latch clock L
P), AC clock FR and logic side power supply voltage V _C
C. In addition, even when any operation abnormality occurs in the liquid crystal module controller 12 and the microprocessor unit (MPU), the above-described signals may be abnormal, and the same situation as described above may occur.

By the way, the problem of the DC drive of the liquid crystal display can be generalized to the problem of signal abnormality on the liquid crystal module side. In addition, when assuming a wall-mounted television, since the display control unit and the display panel are remotely located, there is a problem of display quality deterioration due to signal level attenuation and noise influence while stopping signals. You. Further, the problem is not limited to the liquid crystal display but also to a plasma display.

Further, even if an abnormality occurs in a signal (control signal) supplied from the display control unit to the display module unit side and the display of the liquid crystal panel is set to the off state in response to the abnormality, the control signal Is restarted, abnormal driving due to a power supply abnormality induced by the rush current becomes a problem.

Therefore, an object of the present invention is to solve the above-described problems, and to solve the above-mentioned problems, the deterioration of the display characteristics due to the DC drive of the display panel caused by the abnormality of the signal supplied from the display control section to the display module section. And a display drive device capable of preventing abnormal driving due to a power supply abnormality induced by a rush current even when the abnormal signal is restarted. It is in.

[0009]

In order to solve the above-mentioned problems, a flat display device according to the present invention comprises a flat display body driven by a display drive potential and a display for selecting the display drive potential on the flat display body. And a driving unit, wherein the display driving unit detects a potential of a logic circuit and a logic power source for driving the logic circuit, and performs power control after a predetermined time after detecting a change in the potential of the logic power source. And a display power supply circuit for controlling the supply of the display drive potential to the display drive means based on the power control signal.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. 1 is a block diagram showing the entire configuration of a liquid crystal display device according to Embodiment 1 of the present invention. In FIG. 1, the same portions as those shown in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted.

[0011] The scan electrode driving circuit of the liquid crystal display module unit 40 in this embodiment (Y driver) scan driver semiconductor integrated circuit constituting a 46 _(LSI) 46 1 ~46
_n has a signal management control unit 47.

First scan driver semiconductor integrated circuit 46 ₁
Signal management control unit 47 _first detects the stop of the scanning line synchronization signal YSCL applied to the terminal CKB1 (data signal latch clock LP). Second signal management control unit 47 ₂ of the scan driver semiconductor integrated circuit 46 ₂ terminal CKB
2 to detect the stop of the scan start pulse (frame start signal) SP applied to the switch 2. The signal management controller 4 of the n-th (eg, third) scan driver semiconductor integrated circuit 46 _n
7 _n is an alternating clock FR applied to the terminal CKBn.
Detect stoppage. Each signal management control unit 47 ₁
To 47 _n has a signal stop detection control terminal _S 1 to S _n and the signal stop detection terminal _T 1 through T _n. Force blank display signal DFF the normally high voltage (bar) is supplied from the control circuit 10 side to the first scan driver semiconductor integrated circuit ₄₆₁ of the signal stop detection control terminal S ₁ of the signal management control unit 47 _1, the signal stop detection terminal T ₁ is connected to the signal stop detection control terminal S ₂ of the second scan driver semiconductor integrated circuit 46 ₂ of the signal management control unit 47 _2. The second scan driver semiconductor integrated circuit 46 ₂
Signal stop detection terminal _{T 2} of the signal management control unit 47 ₂
It is connected to the next stage of the signal stop detection terminal (e.g., signal stop detection control terminal S _n of the signal management control unit 47 _n of the _n). The signal stop detection terminal _{T n} of the signal management control unit 47 _n of the n is connected to a scan driver ₄₆ 1 -46 _n and the signal driver ₂₄ 1 to 24 _n of the forced blank control terminals DF (bar).

[0013] The signal management control unit 47 ₁ of the scan driver
To 47 _n, as shown in FIG. 2 are cascade-connected, configuration of each signal management control unit ₄₇ 1 to 47 _n are identical. Data signal to be detected signal of the signal management control unit 47 ₁ is applied to terminal CKB ₁ latch clock L
P, the detected signal of the signal management control unit 47 ₂ terminal CKB
₂ to the applied scanning start pulse (frame start signal) SP, the detected signal of the signal management control unit 47 _n is AC clock FR applied to the terminal CKB _n.

[0014] Here, by paying attention to the signal management control unit 47 ₁ will be described the configuration. Signal management control unit 47 ₁ includes a signal stop detection circuit 48 as a signal detecting means for detecting the stop of the detected signal, the signal delay circuit 49 and logic circuit 50
Is provided.

The signal stop detecting circuit 48 is switched by a latch clock LP as a signal to be detected, is a first N-type MOS transistor Tr ₁ constituting a transfer gate, an inverter INV ₁ for inverting the phase of the latch clock LP, The second N-type MOS transistor Tr ₂ , which switches by a reverse phase signal of the latch clock LP to form a transfer gate,
The first capacitor C ₁₁ charged and discharged by the opening and closing operation of the N-type MOS transistor Tr ₁ , the second N-type MOS transistor Tr ₁
The second capacitor _{C 12} is charged and discharged by the opening and closing operation of the transistor Tr _2, the discharge resistor _{R 1} discharges the charge of the capacitor _{C 12,} and a second capacitor _{C 12}
By comparing the charging voltage and the threshold V _TH and an inverter INV ₂ for outputting a charge level judgment signal. First N-type MOS transistor Tr ₁ , inverter INV _1, and second N-type MOS transistor Tr ₂
Constitutes a series exclusive switching circuit. And the first
N-type MOS transistor Tr ₁ constitutes a selective charge switch for the first capacitor C ₁₁ , and
The N-type MOS transistor Tr ₂ constitutes a selective charge switch for distributing transferring the charges of the first capacitor _{C 11} to the second capacitor _{C 12.}

The signal delay circuit 49 includes an inverter INV ₂
Have connected the reset terminal R the output of the (bars) and grounded input terminal D (bar), a frame start signal SP and the D-type flip-flop 49a to the clock input CK, the output of the inverter INV ₂ Connected reset terminal R (bar) and flip-flop 49a
Having an input terminal D (bar) connected to the output Q (bar) of the frame, and having the frame start signal SP as a clock input.
And a mold flip-flop 49b. The logic circuit 50 receives the forced blank signal DF from the control circuit 10.
It is composed of an AND circuit AND having two inputs of F (bar) and Q output of flip-flop 49b.

[0017] Figure 3 a typical scan electrode driving circuit except the signal management control unit 47 ₁ of the scan driver 46 ₁ (logic unit)
FIG. In this logic section, multi-bit scan electrode drive cells 46 ₁₁ , 46 ₁₂ ... Which apply voltages in a line order corresponding to a large number of scan electrodes are formed in an array. FIG. 3 shows the scan electrode driving cells 46 ₁₁ and 46 _{12 of} the first bit and the second bit and their peripheral circuits.

[0018] Here focusing on the scan electrode driving cell 46 ₁₁ explaining the configuration, the scanning electrode driving cell 46
Reference numeral ₁₁ denotes a D-type flip-flop 46a in a shift register which is activated by the frame start signal SP and transfers the frame start signal SP to the next stage every time the scanning synchronization signal YSCL is input, and an n-th flip-flop 46 for the bit selection output Q.
Force blank display signal DF and row forced blank display control circuit 46b for performing a logic operation in consideration of the (bar), a logic system power source voltage and the output (V _{CC =} 5 v supplied from the terminal T _n of the scan drivers 46 _n of ) Is converted to a high-voltage logic amplitude by a row unit voltage level shift circuit 46c.
And the forced blank display signal DF
A total line forced blank display control circuit 46d that performs a logical operation in consideration of (bar), and a high-voltage AC clock FR having a high-voltage logic amplitude from a logic system power supply voltage (V _CC = 5V) a voltage level shift circuit 46e for AC clock to be converted to _H, the high pressure AC clock FR high voltage AC of _H reverse phase clock FR _H
Forward / reverse two-phase clock generation circuit 46f for inverting to (bar)
And a pair of the high-voltage alternating clock FR _H and the opposite-phase high-voltage alternating clock FR _H (bar) and a pair of the outputs O and O (bar) of the row unit voltage level shift circuit 46c in a cross-linked combination. a selection control signal generation circuit 46g for generating a selection control signal _C 1 -C _4, each selection control signals _C 1,
The scan electrode driving voltage V _{5 is determined} by C ₂ , C ₃ and C ₄ .
, V ₁ , V ₀ , and V ₄ are selectively transmitted to the scan electrodes. Here, the row unit forced blank display control circuit 46b and the total row forced blank display control circuit 46d constitute a forced blank display control circuit. Incidentally, INV ₃ is an inverter to adjust the logic to the row unit forced blank display control circuit 46b of the forced blank display control signal DF (bar).

Next, the operation of this embodiment will be described with reference to FIG. When at time t ₀ is logic supply V _CC of the liquid crystal display device is turned on, similarly to the conventional reset signal of the power-on reset terminal number μs~ several ms pulse width to the RS of the liquid crystal module controller 12 MP
The liquid crystal module controller 12 is supplied from the U (not shown) side and is initialized. During this initialization period, various signals output from the liquid crystal module controller 12 are generally in a stopped state. In this period, since the forced blank display signal DFF (bar) is at a low voltage level (hereinafter, referred to as L level), the liquid crystal power supply circuit 28 is in a power-off state, and the liquid crystal drive power supply voltages V _{0 to} V ₅ are not applied. It is an occurrence state. Therefore, no DC component is applied between the liquid crystal electrodes during the initialization period, and the deterioration of the liquid crystal element is prevented.

[0020] Beyond this period, as shown in FIG. 4, the forced blank display signal at time t ₁ DFF (bar) is a high voltage level from the L level changes (hereinafter, H-level hereinafter), also a liquid crystal module controller Reference numeral 12 generates a frame start signal SP, a data signal latch clock LP, and an AC conversion clock FR. Now first the operation of the scan driver 46 ₁ of the signal management control unit 47 _1, the input terminal CKA _first signal delay circuit 49 is supplied with a frame start signal SP, also detection terminal CKB _first signal stop detection circuit 48 Is supplied with a data signal latch clock LP.

H level of data signal latch clock LP
In the period, the transistor of the signal stop detection circuit 48
Tr₁ Is turned on and the transistor Tr₂ Is off
It is in. Therefore, during this period, the capacitor C₁₁Is charged
Is done. L level period of data signal latch clock LP
, The transistor Tr of the signal stop detection circuit 48
₂ Is turned on and the transistor Tr₁ Is off
You. Therefore, during this period, the capacitor C₁₁Is charged
A part of the charge₁₂It is transferred to and charged. De
Data signal latch clock LP repeat pulse is generated
Capacitor C₁₂Since the charging voltage of
Inverter INV₂ Input voltage is threshold V_THBelow
At time t₂ Inverter INV₂ Output INV
_OUT Becomes H level. Time t₂ Previously
Inverter INV₂ Output INV _OUT Is L level
Therefore, the D flip-flop of the signal delay circuit 49
The output Q of 49a is at the L level.
Output T of 0₁ Is at the L level. Here, the output INV
_OUT Is at the H level,₂ Then go out
The force Q does not go to the H level. D flip flop 49
b, 49a, frame star
1 frame period (T_F ) ~ 2 frames around
Period (2T_F ), The output Q is maintained at the L level.
At time t₃And the output T of the logic circuit 50₁ Is H level
become.

The signal stop detection circuit of the signal in the scan driver 46 ₂ management control unit 47 ₂ 48 ₂ detection terminal C
The KB ₂ frame start signal SP is supplied, and the signal delay circuit 49 and _second input terminals CKA ₂ cascade input DI ₂ serving frame start signal coming from a cascade output terminal DO of the scan driver 46 ₁ to SP
Is supplied. The output _{T 1} of the logic circuit 50 of the scan driver 46 ₁ is cascaded to the logic circuit 50 of the scan driver 46 _2. Signal stop detection circuit 4
8 ₂ of the capacitor _{C 21} is the frame start signal SP
Is charged by the repetition pulse. Similarly, the detection terminal CKB _n of the scan driver 46 signal stop detection circuit of the signal management control unit 47 _n in _n 48 _n is supplied with the alternating signal FR, also to the input terminal CKA _n of the signal delay circuit 49 _n is cascade input DI _n serving frame start signal SP coming from the cascade output terminal DO of the scan driver 46 ₂ is supplied. The output _{T 2} of the logic circuit 50 of the scan driver 46 ₂ are cascaded to the logic circuit 50 of the scan driver 46 _n. Signal stop detection circuit 48 _n capacitors C of
_n2 is charged by the repetition pulse of the alternating signal FR. Data signal latch clock L as detected signal
Since the cycle and the duty ratio of P, the frame start signal SP, and the AC conversion signal FR are different, the comparison determination time t of the inverters INV _{1 to} INV _n in each scan driver is determined.
_{3 and the} like, the capacitors C ₁₁ -C
_n1, it is preferable _{to C} 12 _-C keep _n2 and the values of the discharge resistor _R 1 to R _n (the time constant) and the mutual adjustable.
For this purpose, in this embodiment, as shown in FIG. 1, external terminals for connecting external capacitors and resistors are provided in the scan driver.

As described above, the logic power supply V_CCWhen throwing
Point t₀ From the output T of the logic circuit₁~ T_n To H level
Time t₃ In the period until, each scan driver and
And signal driver forced display blank control terminal DF (bar)
ー) has an L level output T _n Is supplied
Thus, the liquid crystal display panel 22 is in a blank display state. One
In other words, the forced display blank control signal DF (bar) is at L level.
The forced blank display control circuit shown in FIG.
The scanning electrode driving cell 46 is controlled by controlling the paths 46b and 46d.
Of the selection switch 46h of the transistor F₁ Only on
In the state, the voltage V is applied to the scan electrode.₅ (0v) is applied
Thus, the voltage between the liquid crystal electrodes (liquid crystal applied voltage) is 0 V.
Time t₀ ~ Time t₃ Period corresponds to the LCD drive prohibition period.
Hit. Time t₁ The LCD power supply circuit 28
And the liquid crystal drive voltage V₀ ~ V₅These occur
The voltage is supplied to the scan and signal drivers,
At the time of raising, shift in scanning and signal driver
Registers, etc. are in an undefined state. However, at time t₃
 LCD display is blank controlled until
The abnormal driving of the tunnel can be avoided.

Next, when the output T _n becomes H level at time t _3, the voltage of H level is supplied to the forced display blank control terminals DF of each scanning driver and signal driver (bar), the scan driver and The liquid crystal display panel 22 is AC driven by the normal operation of the signal driver, and a display screen is drawn on the liquid crystal panel 22. B shown in FIG. 4 represents a liquid crystal driving period. And logic power-on of the scan and signal drivers and the liquid crystal power source circuit 28 at time t _1, which liquid crystal display panel 22 is driven from when t ₃ when delayed. Therefore, since power-on does not occur at the same time, an excessive power-rush current is suppressed. This is because the delay action of the signal delay circuit 49 having a delay time of 1 to 2 frame periods effectively functions in addition to the delay operation of the signal stop detection circuit 48 itself.

Now, in the liquid crystal driving period B,
Point t₄ Sent from the LCD module controller 12 side.
The output of the output data signal latch clock LP
For example, suppose that it stopped. Data signal latch clock LP
Scan driver 46 during output of ₁ Signal stop detection circuit 4
8₁ Of the second capacitor C₁₂Is fully charged
However, when the clock LP stops, the second capacity
TA C₁₂To the first capacitor C₁₁Charge transfer from side
Or the second capacitor C₁₂The charge of
Discharge resistance R₁ Through a predetermined time constant
Inverter INV₂ Input voltage gradually rises
You. Its input voltage is equal to its threshold V_THExceeds
Force voltage INV_OUT At time t₅ At L level.
This logic change causes the signal delay circuit 49₁ Is reset
Since the output Q is at the L level, the forced display
Link control signal DF (bar) is at L level
Instead of the logic circuit 50₁ Output T₁ Is the time t₅ In L
Level. This output T₁Is the scanning driver 46₂ of
Logic circuit 50₂ Cascade input to
Even when the frame start signal SP is being output, its logic circuit 50
₂ Output T₂ Becomes L level. Further, the output T₂ 
Is the scanning driver 46_n Logic circuit 50_nCascade to
Input, so that the
Logic circuit 50_n Output T_n Becomes L level. this
Output T_n Indicates forced display on the LCD module 46 side
Since it corresponds to the blank control signal DF (bar),
LCD blanking circuits 46b and 46d
The channel 22 enters a blank display state. That is, as shown in FIG.
Of the selection switch 46h of the scan electrode driving cell 46.
Jista F₁ Only in the ON state, and the voltage V₅
 (0v) is supplied, so that the voltage between the liquid crystal electrodes becomes 0v.
Will be maintained. Therefore, the data signal latch clock LP
If the LCD stops for some reason, the liquid crystal device
Since it is not driven in minutes, deterioration of the liquid crystal is prevented beforehand.
In addition, the frame start signal SP or the AC conversion signal FR
Even if it stops for some reason, the output T_n Is L level
Therefore, similarly, the deterioration of the liquid crystal is prevented beforehand.
During the liquid crystal driving prohibition period A, the frame
As long as the signal SP and the alternating signal FR continue,
Second capacitor C₂₂And C_n1Is charged,
Inverter INV₂ , INV_n Output at H level
is there.

[0026] Data signal latch clock LP at time t ₆ begin to appear again, as described above, the second
Capacitor _{C 12} is charged, the inverter INV ₁
Output INV _OUT goes high. Output INV
After one or two frame periods from the time when _OUT goes to the H level, a signal delay circuit 49 ₁ functioning as a timer
Output Q becomes H level at time _{t 7} in. Thus, the logic circuit ₅₀ 2 in conjunction with this with the output _{T 1} of the logic circuit 50 ₁ becomes H level, 50 _n output T of the
₂ , _Tn becomes H level. Accordingly, the forced display blank control signal DF (bar) on the liquid crystal display module section 22 changes to the H level, so that the liquid crystal display panel 22 enters the liquid crystal driving period B.

[0027] Finally, when the forced display blank control signal DFF of the liquid crystal display controller 12 side (bar) becomes the L level at time _{t 8,} the output _{T 1} of the logic circuit 50 ₁ is L
Therefore, the outputs T ₂ and T _{n of} the logic circuits 50 ₂ and 50 _n are also at the L level. Therefore, the forced display blank control signal DF on the liquid crystal display module unit 20 side
(Bar) becomes L level, and the liquid crystal display panel 22 enters the display off period C.

[0028]

Embodiment 2 FIG. 5 is a block diagram showing a liquid crystal display device according to Embodiment 2 of the present invention. In FIG. 5, the same portions as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

The plurality of scan drivers 76 _{1 to} 76 _n constituting the scan electrode drive circuit (X driver) 76 of the liquid crystal display module 70 of this embodiment are similar to the signal management controller of the first embodiment. 77 _{1 to} 77 _n , but as shown in FIG.
₁ to 77 _n in the liquid crystal drive voltage _V 0 ~V ₅ controls the timing of the power-on / off of the liquid crystal power source circuit 28 should generate a power supply power on / off control circuit ₇₈ 1 -
78 _n are added.

Power supply power on / off control circuit 78₁ ~
78_n Is a logic circuit 50₁ Input terminal S₁ ~ S_n
 INV that inverts the signal coming into the inverter₃ 
And two-stage D flip-flops 78a and 78b
And its output Q and terminal P₁ ~ P _n Signal coming from
And a logic circuit 78c that takes the logic of
The signal delay circuit 79 of each signal management control unit 77 is implemented as
The two-stage D flip-flop of the signal delay circuit 49 according to Example 1
The third stage D flip-flop is attached to flops 49a and 49b.
This is a configuration in which a step 79c is additionally connected.

First scan driver 76₁ Logic circuit 7
8c input terminal P₁ Is the logic side power supply voltage V_CCof
A power on / off signal is supplied and the second scan
Liver 76₂ Terminal P₂ Has a first scanning driver 7
6₁ Power supply on / off control circuit 78₁ 
Output PF₁Are supplied in cascade. Also the
n scan drivers 76_n Terminal P_n The first
2 scan driver 76 ₂ Power on / off
Control circuit 78₂ Output PF₂Supplied in cascade
Have been. Then, the n-th scan driver 76_n No electricity
Source power on / off control circuit 78_n Output PF_n Is
To the power off terminal POFF (bar) of the liquid crystal power supply circuit 28
Supplied.

The liquid crystal power supply circuit 28 has the same configuration as the conventional one,
As shown in FIG. 7, a voltage conversion circuit 2 that generates a high voltage (20 to 40 V) boosted based on a V _CC (5 V) power supply voltage
8a, an npn transistor 28b for controlling on / off depending on a voltage value supplied to a power-off terminal POFF (bar), and a power switch for turning on / off in conjunction with on / off operation of the transistor 28b Pnp
And type transistor 28c, a smoothing capacitor 28d interposed between the ground and its collector, voltage divider circuit 28 which outputs a liquid crystal driving voltage V ₀ ~V ₅ from the charging voltage
e.

Next, the operation of the above embodiment will be described with reference to FIG.
It will be explained while doing. Time t₀ At power switch S
W is closed and the logic power supply V of the liquid crystal display device is_CCThrow
Then, as in the first embodiment, the liquid crystal module controller
The power-on reset terminal RS of the roller 12 has several μs to several μs.
ms reset signal is supplied from MPU side.
Then, the liquid crystal module controller 12 is initialized.
Therefore, the output signal from the liquid crystal module controller 12 is
The signal is generally at rest. During this period,
Gic power supply voltage V_CCIs the first scan driver 76₁ of
It is supplied to one input of a logic circuit 78c as an AND circuit.
However, the data signal latch clock LP has not yet appeared.
The output PF₁ Is in the L level state. This result
As a result, the second scan driver 76₂ Output PF₂ Also L
And the nth scan driver 76 _n Output PF_n
 Is also at the L level, so that the power
Terminal POFF (bar) is maintained at the L level.
You. Therefore, the base of the transistor 28b shown in FIG.
Since the potential is at the L level (0 V), the boosted voltage is
The liquid crystal drive voltage V is not supplied to the capacitor 28d.
₀ ~ V₅ Does not occur. As in the first embodiment,
During the reset period, no DC component is applied between the liquid crystal electrodes
Deterioration of the element is prevented.

Next, as shown in FIG.₁ With liquid crystal
Various signals are generated from the module controller 12.
You. Is the forced blank display signal DFF (bar) at L level?
From the frame start signal SP,
Data signal latch clock LP and AC clock FR
Occurs. As described in the first embodiment, the data signal
Inverter INV by the start of appearance of the switch clock LP
₂ Output INV_OUTAt time t₂ At H level
You. Therefore, the output of the power on / off control circuit 78b
Q is time t₂ One or two frame periods later
t₃At the H level, the output PF of the logic circuit 78c
₁ Becomes H level. Thereby, the second and n-th scans
Driver 76₂ , 76_n Output P of the logic circuit 78c
F₁ , PF go to H level in conjunction with
Power off terminal POFF (bar) of circuit 28 is at H level
It is urged to. As a result, the transistor 28b is turned on.
The base-emitter of the transistor 28c.
The transistor 28c is also turned on by the voltage drop of the inter-resistance.
State, the smoothing capacitor 28d is charged, and the liquid crystal drive
Dynamic voltage V₀ ~ V₅ Occurs. Time t₃ From next
Time t when the frame start signal SP arrives₄ Until
Output Q of D flip-flop 79c remains at L level
It is. Signal delay circuit 79 in this embodiment₁ D
The number of flip-flop stages is the power on / off control circuit
78₁ One step higher than that of
The output Q of the flop 79c is the output Q of the D flip-flop 78b.
One frame period T_F Just delayed to H level
This is because that. As a result, the output T ₁ , T₂ , T_n 
Are both at the H level.
Blank display signal DF (bar) on display module side
Changes from the L level to the H level, which causes the liquid crystal display
The driving voltage V is applied to the scanning electrodes and signal electrodes of the panel 22. ₀ 
~ V₅ Is supplied with power to enter the liquid crystal display mode.

For example, if the liquid crystal display panel 22 is driven simultaneously with the generation of the liquid crystal drive voltages V _{0 to} V ₅ , a large charging rush current is generated in the liquid crystal display panel and the power supply of the scanning and signal driver. However, in the present embodiment, the liquid crystal driving voltage _V 0 at time _{t 3} ~V
₅ , the liquid crystal driving is started after one frame period _TF , so that the rush current can be dispersed due to the time difference of the power supply unit, the power supply can be prevented from being reduced, and the power supply capacity can be reduced. Contributes to protection of display panels and drivers. Further, the above-described power supply control reduces the development cost burden on the system side, and does not require an increase in signal wiring between the conventional system side and the LCD module.

Further, since the power supply capacity is reduced, an inexpensive power supply can be used.

Next, at the time point t in the liquid crystal driving period B,₅ 
Is transmitted from the liquid crystal module controller 12 side.
Oscillation of the data signal latch clock LP stopped
Then, as in the first embodiment, the inverter INV₂ of
The input voltage rises and its output voltage INV_OUT Is
t₆ At L level and the output T₁ , T₂ , T_nAlso
It becomes L level. As a result, the liquid crystal display module side
Of the forced display blank control signal DF (bar)
Therefore, the liquid crystal display panel 22 is in a blank display state.
You. The same effect as in the first embodiment is exhibited. Also Invar
TAINV₂Output voltage INV_OUT Becomes L level
And the output PF₁ , PF₂ , PF _n Also L level
And the power off terminal POFF of the liquid crystal power supply circuit 28
(Bar) changes to the L level, and the liquid crystal drive voltage V₀ ~
V₅ Stops occurring.

[0038] When the data signal latch clock LP at time _{t 7} begins to reappear in the same manner as in Example 1, the time the output voltage _{INV OUT} of the inverter INV ₂ is t
₈ at the H level, and as described above, at this time t
Output PF from ₈ at the time _{t 9} after a 1-2 frame period
₁ , PF ₂ and PF _n are also at the H level. As a result, the power-off terminal POFF (bar) of the liquid crystal power supply circuit 28 changes to the H level, so that the liquid crystal drive voltage V ₀ to
V ₅ is generated, they are applied to the driver side. Then, as described above, the outputs T ₁ , T ₂ , and T _n are delayed from the time t ₉ by one frame period _{TF at} the time t.
_{At 10} , the liquid crystal display panel 22 changes to the H level, and the scanning electrodes and the signal electrodes of the liquid crystal display panel 22 are supplied with the liquid crystal driving voltages V _{0 to} V ₅ , and the liquid crystal display mode is restarted.

[0039] When the forced display blank control signal of the liquid crystal display controller 12 side at the time _{t 11} DFF (bar) becomes the L level, the output _{T 1,} T 2, since _{T n} also becomes L level, the liquid crystal display module unit 70 side , The liquid crystal display panel 22 enters the display-off period C. The output Q of this from the time _{t 11} 1 to 2 frame period time _{t 12} after the power-on / off control circuit 78 ₁ D flip-flop 78b is changed to L level, the output _{PF 1, PF 2, PF n}
Also at L level. As a result, the power off terminal POFF (bar) of the liquid crystal power supply circuit 28 also becomes L level,
Generation of the liquid crystal drive voltage _V 0 ~V ₅ is stopped. As described above, when the forced display blank control signal DFF (bar) on the liquid crystal display controller 12 side becomes L level, the application of the liquid crystal voltage to the driver is stopped after a certain period of time after the liquid crystal driving is stopped. By such a power-off sequence, the logic power supply _VCC and the liquid crystal drive power supply V ₀
Potential relation ~V ₅ is maintained, the parasitic bipolar current or a through current of the driver is suppressed, it can be protected in the liquid crystal display panel and a driver.

In this embodiment, the power of the liquid crystal power supply circuit 28 is turned on after the clock is supplied to the liquid crystal module, and the power of the liquid crystal power supply circuit 28 is turned off by stopping the output of the clock. Since the rush current is dispersed or time-differenced by such an auto sequence of energizing the power supply, the liquid crystal panel, the driver, and the liquid crystal power supply circuit constituting the liquid crystal display module can be protected as described above.

In each of the above embodiments, the signal management control unit is incorporated in the scan driver LSI. This is because the number of input / output signal lines is smaller than that of the signal driver LSI and the display frame area is smaller. This is because the width is large, so that the circuit board on which the signal management control unit is mounted has a large area margin. Further, in this embodiment, the display device of the simple matrix liquid crystal panel has been described, but the present invention is not limited to this, and the active device is not limited thereto.
The invention can be applied to a matrix type liquid crystal display device. In such a case, it is preferable to provide a signal management control unit on the gate driver LSI side. In that case, when the clock stops, the gate driver LSI is controlled so that all gates are turned on, and the source driver is controlled so that the data side outputs the same potential as the common side,
All pixel electric fields are set so as to be in a non-applied state.
Furthermore, the present invention is applicable not only to displays but also to display devices whose display quality is degraded by DC driving, such as electronic devices using liquid crystal devices and plasma displays, such as liquid crystal optical arithmetic devices. is there.

In each of the above embodiments, means for detecting an abnormality of a signal supplied from the liquid crystal module controller 12 and means for removing an abnormal state of the signal before or afterward are provided on the liquid crystal module side. Has been
Some components of these means may be provided on the liquid crystal module side, and the remaining components may adopt a shared configuration provided on the system (controller) side. For example, a plurality of signals (S
P, LP, FR) have different frequencies and pulse duties.
The signal is converted to a single composite signal using a usive OR gate, sent back to the system side, monitored for an abnormal state by a decision circuit, and the output is used to remove the abnormal state.
It is possible to adopt a configuration in which an indicator is displayed by using a display body different from the LCD module side. The return output terminals T _n of the scan drivers 46 _n of the embodiment shown in FIG. 1 to the system side, the logic system and the liquid crystal-based system for controlling power on / off at a certain procedure (sequence) can alternatively employed.

[0043] As another cause for degrading the liquid crystal panel, the voltage value shift and a specific driver output failure of the liquid crystal driving voltage V ₀ ~V ₅ due to abnormal voltage divider circuit 28e of the liquid crystal power source circuit 28 shown in FIG. 7 For example, it is considered that the liquid crystal panel is driven by an effective DC component and deteriorates. Since these abnormalities can also be detected as fluctuations of the power supply current and the power supply voltage, the abnormal state can be removed by the above-described abnormality removing means.

[0044]

As described above, in the flat display device according to the present invention, when the signal transmitted from the display control unit stops oscillating, the DC drive of the liquid crystal is forcibly performed by the signal management control means on the display module side. Will be suspended. For this reason,
The display body can be prevented from being deteriorated due to the DC drive. Further, even when the signal that has become abnormal once is restarted and the display is turned on, it is possible to prevent abnormal driving due to power supply abnormality induced by the rush current. Also, the power supply rush current itself can be reduced. The present invention is applicable not only to liquid crystal display devices but also to plasma display devices and the like. The present invention is suitable for use in a display device in which the display quality and life of the display body cause irreparable deterioration due to an abnormality in the drive signal.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a signal management control unit of each scanning driver and a connection relationship between the drivers in the embodiment.

FIG. 3 is a circuit diagram showing a scan electrode drive cell of the scan driver in the embodiment.

FIG. 4 is a timing chart illustrating the relationship between various signals in the liquid crystal display module for explaining the operation of the embodiment.

FIG. 5 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a signal management control unit of each scanning driver and a connection relationship between the drivers in the embodiment.

FIG. 7 is a circuit diagram showing a configuration of a liquid crystal power supply circuit in the embodiment.

FIG. 8 is a timing chart showing the relationship among various signals in the liquid crystal display module for explaining the operation of the embodiment.

FIG. 9 is a block diagram illustrating a configuration of a conventional liquid crystal display device.

[Explanation of symbols]

10 ... LCD controller 12,40,70 ... liquid crystal module controller 20 ... flat-shaped liquid crystal display module unit 22 ... liquid crystal display panel (matrix liquid crystal display device) ₂₄ 1 to 24 m _... signal electrode driver semiconductor integrated circuits 24 ... Signal electrode drive circuit (X driver) 26, 46, 76... Scan electrode drive circuit (Y driver) 26 _{1 to} 26 _n , 46 _{1 to} 46 _n , 76 ₁ to
76 _n ... scanning electrode driver semiconductor integrated circuit 28 ... liquid crystal power supply circuit 28a ... voltage conversion circuit 28b ... npn transistor 28c ... pnp transistor 28d ... smoothing capacitor 28e ... voltage dividing circuit 30 ... cables 46 ₁₁ and 46 ₁₂ ... scanning electrodes D driving cells 46a, 49a, 49b, 78a, 78b, 79c ... D
Type flip-flop 46b ... row unit forced blank display control circuit 46c ... row unit voltage level shift circuit 46d ... total row forced blank display control circuit 46e ... voltage level shift circuit 46f ... forward / reverse two-phase clock generation circuit 46g ... selection control signal Generation circuit 46h selection switches 47, 47 _{1 to} 47 _n , 77 _{1 to} 77 _n signal management control section 48 signal stop detection circuits 49, 79 signal delay circuit 50 logic circuit 51 sequence processing circuit 78 _{1 to} 78 _n power supply power on / off control circuit 78c logic circuit Tr ₁ first N-type MOS transistor Tr ₂ second N-type MOS transistor INV ₁ , INV ₂ , INV ₃ inverter C ₁₁ first capacitor C _{12 ...} second capacitor R 1 _... discharge resistor the aND ... aND circuit CKB1 CKBn ... terminal S ₁ to S n _... signal stop detection control terminal T ₁ through T n _... signal stop detection terminal V ₀ ~V 5 _... liquid crystal driving voltages (reference voltages) D0 to D7 ... data signal XSCL ... pixel clock (shift clock Pulse) YSCL ... Scan line synchronization signal LP ... Data signal latch clock FR ... Alternating clock DF (bar) ... Display off signal (forced blank display signal) SP ... Scan start pulse (frame start signal) POFF (bar) ... Power OFF terminal

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] February 14, 2001 (2001.2.1)
4)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Name of invention

[Correction method] Change

[Correction contents]

[Title of the Invention] Flat display device

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction contents]

[0009]

Flat display devices of the present invention to solve the above problems SUMMARY OF THE INVENTION The selectively a flat display body driven by the display driving voltage, the display driving voltage to said flat display body given in a flat display device including a display driving unit, wherein the display drive means, which detects a logic circuit, the voltage of the logic power supply for driving the logic circuit, it detects a change in voltage of the logic power to a detecting means for outputting a power control signal to the time after, characterized in that it comprises a display power source circuit for controlling the supply of said display drive voltage to said display driving means on the basis of the power control signal.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 670 G09G 3/20 670K

Claims (1)

[Claims] 1. A flat display device comprising: a flat display body driven by a display drive potential; and a display drive unit for selecting the display drive potential for the flat display body, wherein the display drive unit is a logic circuit. And detecting a potential of a logic power supply for driving the logic circuit,
Detecting means for outputting a power control signal after a predetermined time after detecting a change in the potential of the logic power supply; and a display power supply circuit for controlling supply of the display drive potential to the display drive means based on the power control signal. A flat display device comprising: